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openpilot is an open source driver assistance system. openpilot performs the functions of Automated Lane Centering and Adaptive Cruise Control for over 200 supported car makes and models.
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openpilot_comma/tinygrad_repo/tinygrad/runtime/autogen/adreno.py

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# mypy: ignore-errors
# -*- coding: utf-8 -*-
#
# TARGET arch is: []
# WORD_SIZE is: 8
# POINTER_SIZE is: 8
# LONGDOUBLE_SIZE is: 16
#
import ctypes, os
A6XX_XML = True # macro
# def __struct_cast(X): # macro
# return (structX)
REG_CP_LOAD_STATE_0 = 0x00000000 # macro
CP_LOAD_STATE_0_DST_OFF__MASK = 0x0000ffff # macro
CP_LOAD_STATE_0_DST_OFF__SHIFT = 0 # macro
CP_LOAD_STATE_0_STATE_SRC__MASK = 0x00070000 # macro
CP_LOAD_STATE_0_STATE_SRC__SHIFT = 16 # macro
CP_LOAD_STATE_0_STATE_BLOCK__MASK = 0x00380000 # macro
CP_LOAD_STATE_0_STATE_BLOCK__SHIFT = 19 # macro
CP_LOAD_STATE_0_NUM_UNIT__MASK = 0xffc00000 # macro
CP_LOAD_STATE_0_NUM_UNIT__SHIFT = 22 # macro
REG_CP_LOAD_STATE_1 = 0x00000001 # macro
CP_LOAD_STATE_1_STATE_TYPE__MASK = 0x00000003 # macro
CP_LOAD_STATE_1_STATE_TYPE__SHIFT = 0 # macro
CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK = 0xfffffffc # macro
CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT = 2 # macro
REG_CP_LOAD_STATE4_0 = 0x00000000 # macro
CP_LOAD_STATE4_0_DST_OFF__MASK = 0x00003fff # macro
CP_LOAD_STATE4_0_DST_OFF__SHIFT = 0 # macro
CP_LOAD_STATE4_0_STATE_SRC__MASK = 0x00030000 # macro
CP_LOAD_STATE4_0_STATE_SRC__SHIFT = 16 # macro
CP_LOAD_STATE4_0_STATE_BLOCK__MASK = 0x003c0000 # macro
CP_LOAD_STATE4_0_STATE_BLOCK__SHIFT = 18 # macro
CP_LOAD_STATE4_0_NUM_UNIT__MASK = 0xffc00000 # macro
CP_LOAD_STATE4_0_NUM_UNIT__SHIFT = 22 # macro
REG_CP_LOAD_STATE4_1 = 0x00000001 # macro
CP_LOAD_STATE4_1_STATE_TYPE__MASK = 0x00000003 # macro
CP_LOAD_STATE4_1_STATE_TYPE__SHIFT = 0 # macro
CP_LOAD_STATE4_1_EXT_SRC_ADDR__MASK = 0xfffffffc # macro
CP_LOAD_STATE4_1_EXT_SRC_ADDR__SHIFT = 2 # macro
REG_CP_LOAD_STATE4_2 = 0x00000002 # macro
CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__MASK = 0xffffffff # macro
CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__SHIFT = 0 # macro
REG_CP_LOAD_STATE6_0 = 0x00000000 # macro
CP_LOAD_STATE6_0_DST_OFF__MASK = 0x00003fff # macro
CP_LOAD_STATE6_0_DST_OFF__SHIFT = 0 # macro
CP_LOAD_STATE6_0_STATE_TYPE__MASK = 0x0000c000 # macro
CP_LOAD_STATE6_0_STATE_TYPE__SHIFT = 14 # macro
CP_LOAD_STATE6_0_STATE_SRC__MASK = 0x00030000 # macro
CP_LOAD_STATE6_0_STATE_SRC__SHIFT = 16 # macro
CP_LOAD_STATE6_0_STATE_BLOCK__MASK = 0x003c0000 # macro
CP_LOAD_STATE6_0_STATE_BLOCK__SHIFT = 18 # macro
CP_LOAD_STATE6_0_NUM_UNIT__MASK = 0xffc00000 # macro
CP_LOAD_STATE6_0_NUM_UNIT__SHIFT = 22 # macro
REG_CP_LOAD_STATE6_1 = 0x00000001 # macro
CP_LOAD_STATE6_1_EXT_SRC_ADDR__MASK = 0xfffffffc # macro
CP_LOAD_STATE6_1_EXT_SRC_ADDR__SHIFT = 2 # macro
REG_CP_LOAD_STATE6_2 = 0x00000002 # macro
CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__MASK = 0xffffffff # macro
CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__SHIFT = 0 # macro
REG_CP_LOAD_STATE6_EXT_SRC_ADDR = 0x00000001 # macro
REG_CP_DRAW_INDX_0 = 0x00000000 # macro
CP_DRAW_INDX_0_VIZ_QUERY__MASK = 0xffffffff # macro
CP_DRAW_INDX_0_VIZ_QUERY__SHIFT = 0 # macro
REG_CP_DRAW_INDX_1 = 0x00000001 # macro
CP_DRAW_INDX_1_PRIM_TYPE__MASK = 0x0000003f # macro
CP_DRAW_INDX_1_PRIM_TYPE__SHIFT = 0 # macro
CP_DRAW_INDX_1_SOURCE_SELECT__MASK = 0x000000c0 # macro
CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT = 6 # macro
CP_DRAW_INDX_1_VIS_CULL__MASK = 0x00000600 # macro
CP_DRAW_INDX_1_VIS_CULL__SHIFT = 9 # macro
CP_DRAW_INDX_1_INDEX_SIZE__MASK = 0x00000800 # macro
CP_DRAW_INDX_1_INDEX_SIZE__SHIFT = 11 # macro
CP_DRAW_INDX_1_NOT_EOP = 0x00001000 # macro
CP_DRAW_INDX_1_SMALL_INDEX = 0x00002000 # macro
CP_DRAW_INDX_1_PRE_DRAW_INITIATOR_ENABLE = 0x00004000 # macro
CP_DRAW_INDX_1_NUM_INSTANCES__MASK = 0xff000000 # macro
CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT = 24 # macro
REG_CP_DRAW_INDX_2 = 0x00000002 # macro
CP_DRAW_INDX_2_NUM_INDICES__MASK = 0xffffffff # macro
CP_DRAW_INDX_2_NUM_INDICES__SHIFT = 0 # macro
REG_CP_DRAW_INDX_3 = 0x00000003 # macro
CP_DRAW_INDX_3_INDX_BASE__MASK = 0xffffffff # macro
CP_DRAW_INDX_3_INDX_BASE__SHIFT = 0 # macro
REG_CP_DRAW_INDX_4 = 0x00000004 # macro
CP_DRAW_INDX_4_INDX_SIZE__MASK = 0xffffffff # macro
CP_DRAW_INDX_4_INDX_SIZE__SHIFT = 0 # macro
REG_CP_DRAW_INDX_2_0 = 0x00000000 # macro
CP_DRAW_INDX_2_0_VIZ_QUERY__MASK = 0xffffffff # macro
CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT = 0 # macro
REG_CP_DRAW_INDX_2_1 = 0x00000001 # macro
CP_DRAW_INDX_2_1_PRIM_TYPE__MASK = 0x0000003f # macro
CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT = 0 # macro
CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK = 0x000000c0 # macro
CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT = 6 # macro
CP_DRAW_INDX_2_1_VIS_CULL__MASK = 0x00000600 # macro
CP_DRAW_INDX_2_1_VIS_CULL__SHIFT = 9 # macro
CP_DRAW_INDX_2_1_INDEX_SIZE__MASK = 0x00000800 # macro
CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT = 11 # macro
CP_DRAW_INDX_2_1_NOT_EOP = 0x00001000 # macro
CP_DRAW_INDX_2_1_SMALL_INDEX = 0x00002000 # macro
CP_DRAW_INDX_2_1_PRE_DRAW_INITIATOR_ENABLE = 0x00004000 # macro
CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK = 0xff000000 # macro
CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT = 24 # macro
REG_CP_DRAW_INDX_2_2 = 0x00000002 # macro
CP_DRAW_INDX_2_2_NUM_INDICES__MASK = 0xffffffff # macro
CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT = 0 # macro
REG_CP_DRAW_INDX_OFFSET_0 = 0x00000000 # macro
CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK = 0x0000003f # macro
CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT = 0 # macro
CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK = 0x000000c0 # macro
CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT = 6 # macro
CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK = 0x00000300 # macro
CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT = 8 # macro
CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK = 0x00000c00 # macro
CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT = 10 # macro
CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__MASK = 0x00003000 # macro
CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__SHIFT = 12 # macro
CP_DRAW_INDX_OFFSET_0_GS_ENABLE = 0x00010000 # macro
CP_DRAW_INDX_OFFSET_0_TESS_ENABLE = 0x00020000 # macro
REG_CP_DRAW_INDX_OFFSET_1 = 0x00000001 # macro
CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK = 0xffffffff # macro
CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT = 0 # macro
REG_CP_DRAW_INDX_OFFSET_2 = 0x00000002 # macro
CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK = 0xffffffff # macro
CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT = 0 # macro
REG_CP_DRAW_INDX_OFFSET_3 = 0x00000003 # macro
CP_DRAW_INDX_OFFSET_3_FIRST_INDX__MASK = 0xffffffff # macro
CP_DRAW_INDX_OFFSET_3_FIRST_INDX__SHIFT = 0 # macro
REG_A5XX_CP_DRAW_INDX_OFFSET_4 = 0x00000004 # macro
A5XX_CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__MASK = 0xffffffff # macro
A5XX_CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__SHIFT = 0 # macro
REG_A5XX_CP_DRAW_INDX_OFFSET_5 = 0x00000005 # macro
A5XX_CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__MASK = 0xffffffff # macro
A5XX_CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__SHIFT = 0 # macro
REG_A5XX_CP_DRAW_INDX_OFFSET_INDX_BASE = 0x00000004 # macro
REG_A5XX_CP_DRAW_INDX_OFFSET_6 = 0x00000006 # macro
A5XX_CP_DRAW_INDX_OFFSET_6_MAX_INDICES__MASK = 0xffffffff # macro
A5XX_CP_DRAW_INDX_OFFSET_6_MAX_INDICES__SHIFT = 0 # macro
REG_CP_DRAW_INDX_OFFSET_4 = 0x00000004 # macro
CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK = 0xffffffff # macro
CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT = 0 # macro
REG_CP_DRAW_INDX_OFFSET_5 = 0x00000005 # macro
CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK = 0xffffffff # macro
CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT = 0 # macro
REG_A4XX_CP_DRAW_INDIRECT_0 = 0x00000000 # macro
A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__MASK = 0x0000003f # macro
A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__SHIFT = 0 # macro
A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__MASK = 0x000000c0 # macro
A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__SHIFT = 6 # macro
A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__MASK = 0x00000300 # macro
A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__SHIFT = 8 # macro
A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__MASK = 0x00000c00 # macro
A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__SHIFT = 10 # macro
A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__MASK = 0x00003000 # macro
A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__SHIFT = 12 # macro
A4XX_CP_DRAW_INDIRECT_0_GS_ENABLE = 0x00010000 # macro
A4XX_CP_DRAW_INDIRECT_0_TESS_ENABLE = 0x00020000 # macro
REG_A4XX_CP_DRAW_INDIRECT_1 = 0x00000001 # macro
A4XX_CP_DRAW_INDIRECT_1_INDIRECT__MASK = 0xffffffff # macro
A4XX_CP_DRAW_INDIRECT_1_INDIRECT__SHIFT = 0 # macro
REG_A5XX_CP_DRAW_INDIRECT_1 = 0x00000001 # macro
A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__MASK = 0xffffffff # macro
A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__SHIFT = 0 # macro
REG_A5XX_CP_DRAW_INDIRECT_2 = 0x00000002 # macro
A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__MASK = 0xffffffff # macro
A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__SHIFT = 0 # macro
REG_A5XX_CP_DRAW_INDIRECT_INDIRECT = 0x00000001 # macro
REG_A4XX_CP_DRAW_INDX_INDIRECT_0 = 0x00000000 # macro
A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__MASK = 0x0000003f # macro
A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__SHIFT = 0 # macro
A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__MASK = 0x000000c0 # macro
A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__SHIFT = 6 # macro
A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__MASK = 0x00000300 # macro
A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__SHIFT = 8 # macro
A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__MASK = 0x00000c00 # macro
A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__SHIFT = 10 # macro
A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE__MASK = 0x00003000 # macro
A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE__SHIFT = 12 # macro
A4XX_CP_DRAW_INDX_INDIRECT_0_GS_ENABLE = 0x00010000 # macro
A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_ENABLE = 0x00020000 # macro
REG_A4XX_CP_DRAW_INDX_INDIRECT_1 = 0x00000001 # macro
A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__MASK = 0xffffffff # macro
A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__SHIFT = 0 # macro
REG_A4XX_CP_DRAW_INDX_INDIRECT_2 = 0x00000002 # macro
A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__MASK = 0xffffffff # macro
A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__SHIFT = 0 # macro
REG_A4XX_CP_DRAW_INDX_INDIRECT_3 = 0x00000003 # macro
A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__MASK = 0xffffffff # macro
A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__SHIFT = 0 # macro
REG_A5XX_CP_DRAW_INDX_INDIRECT_1 = 0x00000001 # macro
A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__MASK = 0xffffffff # macro
A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__SHIFT = 0 # macro
REG_A5XX_CP_DRAW_INDX_INDIRECT_2 = 0x00000002 # macro
A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__MASK = 0xffffffff # macro
A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__SHIFT = 0 # macro
REG_A5XX_CP_DRAW_INDX_INDIRECT_INDX_BASE = 0x00000001 # macro
REG_A5XX_CP_DRAW_INDX_INDIRECT_3 = 0x00000003 # macro
A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__MASK = 0xffffffff # macro
A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__SHIFT = 0 # macro
REG_A5XX_CP_DRAW_INDX_INDIRECT_4 = 0x00000004 # macro
A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__MASK = 0xffffffff # macro
A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__SHIFT = 0 # macro
REG_A5XX_CP_DRAW_INDX_INDIRECT_5 = 0x00000005 # macro
A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__MASK = 0xffffffff # macro
A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__SHIFT = 0 # macro
REG_A5XX_CP_DRAW_INDX_INDIRECT_INDIRECT = 0x00000004 # macro
REG_A6XX_CP_DRAW_INDIRECT_MULTI_0 = 0x00000000 # macro
A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE__MASK = 0x0000003f # macro
A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE__SHIFT = 0 # macro
A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT__MASK = 0x000000c0 # macro
A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT__SHIFT = 6 # macro
A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL__MASK = 0x00000300 # macro
A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL__SHIFT = 8 # macro
A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE__MASK = 0x00000c00 # macro
A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE__SHIFT = 10 # macro
A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE__MASK = 0x00003000 # macro
A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE__SHIFT = 12 # macro
A6XX_CP_DRAW_INDIRECT_MULTI_0_GS_ENABLE = 0x00010000 # macro
A6XX_CP_DRAW_INDIRECT_MULTI_0_TESS_ENABLE = 0x00020000 # macro
REG_A6XX_CP_DRAW_INDIRECT_MULTI_1 = 0x00000001 # macro
A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE__MASK = 0x0000000f # macro
A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE__SHIFT = 0 # macro
A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__MASK = 0x003fff00 # macro
A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__SHIFT = 8 # macro
REG_A6XX_CP_DRAW_INDIRECT_MULTI_DRAW_COUNT = 0x00000002 # macro
REG_INDIRECT_OP_NORMAL_CP_DRAW_INDIRECT_MULTI_INDIRECT = 0x00000003 # macro
REG_INDIRECT_OP_NORMAL_CP_DRAW_INDIRECT_MULTI_STRIDE = 0x00000005 # macro
REG_INDIRECT_OP_INDEXED_CP_DRAW_INDIRECT_MULTI_INDEX = 0x00000003 # macro
REG_INDIRECT_OP_INDEXED_CP_DRAW_INDIRECT_MULTI_MAX_INDICES = 0x00000005 # macro
REG_INDIRECT_OP_INDEXED_CP_DRAW_INDIRECT_MULTI_INDIRECT = 0x00000006 # macro
REG_INDIRECT_OP_INDEXED_CP_DRAW_INDIRECT_MULTI_STRIDE = 0x00000008 # macro
REG_INDIRECT_OP_INDIRECT_COUNT_CP_DRAW_INDIRECT_MULTI_INDIRECT = 0x00000003 # macro
REG_INDIRECT_OP_INDIRECT_COUNT_CP_DRAW_INDIRECT_MULTI_INDIRECT_COUNT = 0x00000005 # macro
REG_INDIRECT_OP_INDIRECT_COUNT_CP_DRAW_INDIRECT_MULTI_STRIDE = 0x00000007 # macro
REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_INDEX = 0x00000003 # macro
REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_MAX_INDICES = 0x00000005 # macro
REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_INDIRECT = 0x00000006 # macro
REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_INDIRECT_COUNT = 0x00000008 # macro
REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_STRIDE = 0x0000000a # macro
REG_CP_DRAW_AUTO_0 = 0x00000000 # macro
CP_DRAW_AUTO_0_PRIM_TYPE__MASK = 0x0000003f # macro
CP_DRAW_AUTO_0_PRIM_TYPE__SHIFT = 0 # macro
CP_DRAW_AUTO_0_SOURCE_SELECT__MASK = 0x000000c0 # macro
CP_DRAW_AUTO_0_SOURCE_SELECT__SHIFT = 6 # macro
CP_DRAW_AUTO_0_VIS_CULL__MASK = 0x00000300 # macro
CP_DRAW_AUTO_0_VIS_CULL__SHIFT = 8 # macro
CP_DRAW_AUTO_0_INDEX_SIZE__MASK = 0x00000c00 # macro
CP_DRAW_AUTO_0_INDEX_SIZE__SHIFT = 10 # macro
CP_DRAW_AUTO_0_PATCH_TYPE__MASK = 0x00003000 # macro
CP_DRAW_AUTO_0_PATCH_TYPE__SHIFT = 12 # macro
CP_DRAW_AUTO_0_GS_ENABLE = 0x00010000 # macro
CP_DRAW_AUTO_0_TESS_ENABLE = 0x00020000 # macro
REG_CP_DRAW_AUTO_1 = 0x00000001 # macro
CP_DRAW_AUTO_1_NUM_INSTANCES__MASK = 0xffffffff # macro
CP_DRAW_AUTO_1_NUM_INSTANCES__SHIFT = 0 # macro
REG_CP_DRAW_AUTO_NUM_VERTICES_BASE = 0x00000002 # macro
REG_CP_DRAW_AUTO_4 = 0x00000004 # macro
CP_DRAW_AUTO_4_NUM_VERTICES_OFFSET__MASK = 0xffffffff # macro
CP_DRAW_AUTO_4_NUM_VERTICES_OFFSET__SHIFT = 0 # macro
REG_CP_DRAW_AUTO_5 = 0x00000005 # macro
CP_DRAW_AUTO_5_STRIDE__MASK = 0xffffffff # macro
CP_DRAW_AUTO_5_STRIDE__SHIFT = 0 # macro
REG_CP_DRAW_PRED_ENABLE_GLOBAL_0 = 0x00000000 # macro
CP_DRAW_PRED_ENABLE_GLOBAL_0_ENABLE = 0x00000001 # macro
REG_CP_DRAW_PRED_ENABLE_LOCAL_0 = 0x00000000 # macro
CP_DRAW_PRED_ENABLE_LOCAL_0_ENABLE = 0x00000001 # macro
REG_CP_DRAW_PRED_SET_0 = 0x00000000 # macro
CP_DRAW_PRED_SET_0_SRC__MASK = 0x000000f0 # macro
CP_DRAW_PRED_SET_0_SRC__SHIFT = 4 # macro
CP_DRAW_PRED_SET_0_TEST__MASK = 0x00000100 # macro
CP_DRAW_PRED_SET_0_TEST__SHIFT = 8 # macro
REG_CP_DRAW_PRED_SET_MEM_ADDR = 0x00000001 # macro
# def REG_CP_SET_DRAW_STATE_(i0): # macro
# return (0x00000000+0x3*i0)
CP_SET_DRAW_STATE__0_COUNT__MASK = 0x0000ffff # macro
CP_SET_DRAW_STATE__0_COUNT__SHIFT = 0 # macro
CP_SET_DRAW_STATE__0_DIRTY = 0x00010000 # macro
CP_SET_DRAW_STATE__0_DISABLE = 0x00020000 # macro
CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS = 0x00040000 # macro
CP_SET_DRAW_STATE__0_LOAD_IMMED = 0x00080000 # macro
CP_SET_DRAW_STATE__0_BINNING = 0x00100000 # macro
CP_SET_DRAW_STATE__0_GMEM = 0x00200000 # macro
CP_SET_DRAW_STATE__0_SYSMEM = 0x00400000 # macro
CP_SET_DRAW_STATE__0_GROUP_ID__MASK = 0x1f000000 # macro
CP_SET_DRAW_STATE__0_GROUP_ID__SHIFT = 24 # macro
CP_SET_DRAW_STATE__1_ADDR_LO__MASK = 0xffffffff # macro
CP_SET_DRAW_STATE__1_ADDR_LO__SHIFT = 0 # macro
CP_SET_DRAW_STATE__2_ADDR_HI__MASK = 0xffffffff # macro
CP_SET_DRAW_STATE__2_ADDR_HI__SHIFT = 0 # macro
REG_CP_SET_BIN_0 = 0x00000000 # macro
REG_CP_SET_BIN_1 = 0x00000001 # macro
CP_SET_BIN_1_X1__MASK = 0x0000ffff # macro
CP_SET_BIN_1_X1__SHIFT = 0 # macro
CP_SET_BIN_1_Y1__MASK = 0xffff0000 # macro
CP_SET_BIN_1_Y1__SHIFT = 16 # macro
REG_CP_SET_BIN_2 = 0x00000002 # macro
CP_SET_BIN_2_X2__MASK = 0x0000ffff # macro
CP_SET_BIN_2_X2__SHIFT = 0 # macro
CP_SET_BIN_2_Y2__MASK = 0xffff0000 # macro
CP_SET_BIN_2_Y2__SHIFT = 16 # macro
REG_CP_SET_BIN_DATA_0 = 0x00000000 # macro
CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK = 0xffffffff # macro
CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT = 0 # macro
REG_CP_SET_BIN_DATA_1 = 0x00000001 # macro
CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK = 0xffffffff # macro
CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT = 0 # macro
REG_CP_SET_BIN_DATA5_0 = 0x00000000 # macro
CP_SET_BIN_DATA5_0_VSC_SIZE__MASK = 0x003f0000 # macro
CP_SET_BIN_DATA5_0_VSC_SIZE__SHIFT = 16 # macro
CP_SET_BIN_DATA5_0_VSC_N__MASK = 0x07c00000 # macro
CP_SET_BIN_DATA5_0_VSC_N__SHIFT = 22 # macro
REG_CP_SET_BIN_DATA5_1 = 0x00000001 # macro
CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__MASK = 0xffffffff # macro
CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__SHIFT = 0 # macro
REG_CP_SET_BIN_DATA5_2 = 0x00000002 # macro
CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__MASK = 0xffffffff # macro
CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__SHIFT = 0 # macro
REG_CP_SET_BIN_DATA5_3 = 0x00000003 # macro
CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__MASK = 0xffffffff # macro
CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__SHIFT = 0 # macro
REG_CP_SET_BIN_DATA5_4 = 0x00000004 # macro
CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__MASK = 0xffffffff # macro
CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__SHIFT = 0 # macro
REG_CP_SET_BIN_DATA5_5 = 0x00000005 # macro
CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO__MASK = 0xffffffff # macro
CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO__SHIFT = 0 # macro
REG_CP_SET_BIN_DATA5_6 = 0x00000006 # macro
CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI__MASK = 0xffffffff # macro
CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI__SHIFT = 0 # macro
REG_CP_SET_BIN_DATA5_7 = 0x00000007 # macro
REG_CP_SET_BIN_DATA5_9 = 0x00000009 # macro
REG_CP_SET_BIN_DATA5_OFFSET_0 = 0x00000000 # macro
CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__MASK = 0x003f0000 # macro
CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__SHIFT = 16 # macro
CP_SET_BIN_DATA5_OFFSET_0_VSC_N__MASK = 0x07c00000 # macro
CP_SET_BIN_DATA5_OFFSET_0_VSC_N__SHIFT = 22 # macro
REG_CP_SET_BIN_DATA5_OFFSET_1 = 0x00000001 # macro
CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET__MASK = 0xffffffff # macro
CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET__SHIFT = 0 # macro
REG_CP_SET_BIN_DATA5_OFFSET_2 = 0x00000002 # macro
CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET__MASK = 0xffffffff # macro
CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET__SHIFT = 0 # macro
REG_CP_SET_BIN_DATA5_OFFSET_3 = 0x00000003 # macro
CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET__MASK = 0xffffffff # macro
CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET__SHIFT = 0 # macro
REG_CP_REG_RMW_0 = 0x00000000 # macro
CP_REG_RMW_0_DST_REG__MASK = 0x0003ffff # macro
CP_REG_RMW_0_DST_REG__SHIFT = 0 # macro
CP_REG_RMW_0_ROTATE__MASK = 0x1f000000 # macro
CP_REG_RMW_0_ROTATE__SHIFT = 24 # macro
CP_REG_RMW_0_SRC1_ADD = 0x20000000 # macro
CP_REG_RMW_0_SRC1_IS_REG = 0x40000000 # macro
CP_REG_RMW_0_SRC0_IS_REG = 0x80000000 # macro
REG_CP_REG_RMW_1 = 0x00000001 # macro
CP_REG_RMW_1_SRC0__MASK = 0xffffffff # macro
CP_REG_RMW_1_SRC0__SHIFT = 0 # macro
REG_CP_REG_RMW_2 = 0x00000002 # macro
CP_REG_RMW_2_SRC1__MASK = 0xffffffff # macro
CP_REG_RMW_2_SRC1__SHIFT = 0 # macro
REG_CP_REG_TO_MEM_0 = 0x00000000 # macro
CP_REG_TO_MEM_0_REG__MASK = 0x0003ffff # macro
CP_REG_TO_MEM_0_REG__SHIFT = 0 # macro
CP_REG_TO_MEM_0_CNT__MASK = 0x3ffc0000 # macro
CP_REG_TO_MEM_0_CNT__SHIFT = 18 # macro
CP_REG_TO_MEM_0_64B = 0x40000000 # macro
CP_REG_TO_MEM_0_ACCUMULATE = 0x80000000 # macro
REG_CP_REG_TO_MEM_1 = 0x00000001 # macro
CP_REG_TO_MEM_1_DEST__MASK = 0xffffffff # macro
CP_REG_TO_MEM_1_DEST__SHIFT = 0 # macro
REG_CP_REG_TO_MEM_2 = 0x00000002 # macro
CP_REG_TO_MEM_2_DEST_HI__MASK = 0xffffffff # macro
CP_REG_TO_MEM_2_DEST_HI__SHIFT = 0 # macro
REG_CP_REG_TO_MEM_OFFSET_REG_0 = 0x00000000 # macro
CP_REG_TO_MEM_OFFSET_REG_0_REG__MASK = 0x0003ffff # macro
CP_REG_TO_MEM_OFFSET_REG_0_REG__SHIFT = 0 # macro
CP_REG_TO_MEM_OFFSET_REG_0_CNT__MASK = 0x3ffc0000 # macro
CP_REG_TO_MEM_OFFSET_REG_0_CNT__SHIFT = 18 # macro
CP_REG_TO_MEM_OFFSET_REG_0_64B = 0x40000000 # macro
CP_REG_TO_MEM_OFFSET_REG_0_ACCUMULATE = 0x80000000 # macro
REG_CP_REG_TO_MEM_OFFSET_REG_1 = 0x00000001 # macro
CP_REG_TO_MEM_OFFSET_REG_1_DEST__MASK = 0xffffffff # macro
CP_REG_TO_MEM_OFFSET_REG_1_DEST__SHIFT = 0 # macro
REG_CP_REG_TO_MEM_OFFSET_REG_2 = 0x00000002 # macro
CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__MASK = 0xffffffff # macro
CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__SHIFT = 0 # macro
REG_CP_REG_TO_MEM_OFFSET_REG_3 = 0x00000003 # macro
CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__MASK = 0x0003ffff # macro
CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__SHIFT = 0 # macro
CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0_SCRATCH = 0x00080000 # macro
REG_CP_REG_TO_MEM_OFFSET_MEM_0 = 0x00000000 # macro
CP_REG_TO_MEM_OFFSET_MEM_0_REG__MASK = 0x0003ffff # macro
CP_REG_TO_MEM_OFFSET_MEM_0_REG__SHIFT = 0 # macro
CP_REG_TO_MEM_OFFSET_MEM_0_CNT__MASK = 0x3ffc0000 # macro
CP_REG_TO_MEM_OFFSET_MEM_0_CNT__SHIFT = 18 # macro
CP_REG_TO_MEM_OFFSET_MEM_0_64B = 0x40000000 # macro
CP_REG_TO_MEM_OFFSET_MEM_0_ACCUMULATE = 0x80000000 # macro
REG_CP_REG_TO_MEM_OFFSET_MEM_1 = 0x00000001 # macro
CP_REG_TO_MEM_OFFSET_MEM_1_DEST__MASK = 0xffffffff # macro
CP_REG_TO_MEM_OFFSET_MEM_1_DEST__SHIFT = 0 # macro
REG_CP_REG_TO_MEM_OFFSET_MEM_2 = 0x00000002 # macro
CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__MASK = 0xffffffff # macro
CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__SHIFT = 0 # macro
REG_CP_REG_TO_MEM_OFFSET_MEM_3 = 0x00000003 # macro
CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO__MASK = 0xffffffff # macro
CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO__SHIFT = 0 # macro
REG_CP_REG_TO_MEM_OFFSET_MEM_4 = 0x00000004 # macro
CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI__MASK = 0xffffffff # macro
CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI__SHIFT = 0 # macro
REG_CP_MEM_TO_REG_0 = 0x00000000 # macro
CP_MEM_TO_REG_0_REG__MASK = 0x0003ffff # macro
CP_MEM_TO_REG_0_REG__SHIFT = 0 # macro
CP_MEM_TO_REG_0_CNT__MASK = 0x3ff80000 # macro
CP_MEM_TO_REG_0_CNT__SHIFT = 19 # macro
CP_MEM_TO_REG_0_SHIFT_BY_2 = 0x40000000 # macro
CP_MEM_TO_REG_0_UNK31 = 0x80000000 # macro
REG_CP_MEM_TO_REG_1 = 0x00000001 # macro
CP_MEM_TO_REG_1_SRC__MASK = 0xffffffff # macro
CP_MEM_TO_REG_1_SRC__SHIFT = 0 # macro
REG_CP_MEM_TO_REG_2 = 0x00000002 # macro
CP_MEM_TO_REG_2_SRC_HI__MASK = 0xffffffff # macro
CP_MEM_TO_REG_2_SRC_HI__SHIFT = 0 # macro
REG_CP_MEM_TO_MEM_0 = 0x00000000 # macro
CP_MEM_TO_MEM_0_NEG_A = 0x00000001 # macro
CP_MEM_TO_MEM_0_NEG_B = 0x00000002 # macro
CP_MEM_TO_MEM_0_NEG_C = 0x00000004 # macro
CP_MEM_TO_MEM_0_DOUBLE = 0x20000000 # macro
CP_MEM_TO_MEM_0_WAIT_FOR_MEM_WRITES = 0x40000000 # macro
CP_MEM_TO_MEM_0_UNK31 = 0x80000000 # macro
REG_CP_MEMCPY_0 = 0x00000000 # macro
CP_MEMCPY_0_DWORDS__MASK = 0xffffffff # macro
CP_MEMCPY_0_DWORDS__SHIFT = 0 # macro
REG_CP_MEMCPY_1 = 0x00000001 # macro
CP_MEMCPY_1_SRC_LO__MASK = 0xffffffff # macro
CP_MEMCPY_1_SRC_LO__SHIFT = 0 # macro
REG_CP_MEMCPY_2 = 0x00000002 # macro
CP_MEMCPY_2_SRC_HI__MASK = 0xffffffff # macro
CP_MEMCPY_2_SRC_HI__SHIFT = 0 # macro
REG_CP_MEMCPY_3 = 0x00000003 # macro
CP_MEMCPY_3_DST_LO__MASK = 0xffffffff # macro
CP_MEMCPY_3_DST_LO__SHIFT = 0 # macro
REG_CP_MEMCPY_4 = 0x00000004 # macro
CP_MEMCPY_4_DST_HI__MASK = 0xffffffff # macro
CP_MEMCPY_4_DST_HI__SHIFT = 0 # macro
REG_CP_REG_TO_SCRATCH_0 = 0x00000000 # macro
CP_REG_TO_SCRATCH_0_REG__MASK = 0x0003ffff # macro
CP_REG_TO_SCRATCH_0_REG__SHIFT = 0 # macro
CP_REG_TO_SCRATCH_0_SCRATCH__MASK = 0x00700000 # macro
CP_REG_TO_SCRATCH_0_SCRATCH__SHIFT = 20 # macro
CP_REG_TO_SCRATCH_0_CNT__MASK = 0x07000000 # macro
CP_REG_TO_SCRATCH_0_CNT__SHIFT = 24 # macro
REG_CP_SCRATCH_TO_REG_0 = 0x00000000 # macro
CP_SCRATCH_TO_REG_0_REG__MASK = 0x0003ffff # macro
CP_SCRATCH_TO_REG_0_REG__SHIFT = 0 # macro
CP_SCRATCH_TO_REG_0_UNK18 = 0x00040000 # macro
CP_SCRATCH_TO_REG_0_SCRATCH__MASK = 0x00700000 # macro
CP_SCRATCH_TO_REG_0_SCRATCH__SHIFT = 20 # macro
CP_SCRATCH_TO_REG_0_CNT__MASK = 0x07000000 # macro
CP_SCRATCH_TO_REG_0_CNT__SHIFT = 24 # macro
REG_CP_SCRATCH_WRITE_0 = 0x00000000 # macro
CP_SCRATCH_WRITE_0_SCRATCH__MASK = 0x00700000 # macro
CP_SCRATCH_WRITE_0_SCRATCH__SHIFT = 20 # macro
REG_CP_MEM_WRITE_0 = 0x00000000 # macro
CP_MEM_WRITE_0_ADDR_LO__MASK = 0xffffffff # macro
CP_MEM_WRITE_0_ADDR_LO__SHIFT = 0 # macro
REG_CP_MEM_WRITE_1 = 0x00000001 # macro
CP_MEM_WRITE_1_ADDR_HI__MASK = 0xffffffff # macro
CP_MEM_WRITE_1_ADDR_HI__SHIFT = 0 # macro
REG_CP_COND_WRITE_0 = 0x00000000 # macro
CP_COND_WRITE_0_FUNCTION__MASK = 0x00000007 # macro
CP_COND_WRITE_0_FUNCTION__SHIFT = 0 # macro
CP_COND_WRITE_0_POLL_MEMORY = 0x00000010 # macro
CP_COND_WRITE_0_WRITE_MEMORY = 0x00000100 # macro
REG_CP_COND_WRITE_1 = 0x00000001 # macro
CP_COND_WRITE_1_POLL_ADDR__MASK = 0xffffffff # macro
CP_COND_WRITE_1_POLL_ADDR__SHIFT = 0 # macro
REG_CP_COND_WRITE_2 = 0x00000002 # macro
CP_COND_WRITE_2_REF__MASK = 0xffffffff # macro
CP_COND_WRITE_2_REF__SHIFT = 0 # macro
REG_CP_COND_WRITE_3 = 0x00000003 # macro
CP_COND_WRITE_3_MASK__MASK = 0xffffffff # macro
CP_COND_WRITE_3_MASK__SHIFT = 0 # macro
REG_CP_COND_WRITE_4 = 0x00000004 # macro
CP_COND_WRITE_4_WRITE_ADDR__MASK = 0xffffffff # macro
CP_COND_WRITE_4_WRITE_ADDR__SHIFT = 0 # macro
REG_CP_COND_WRITE_5 = 0x00000005 # macro
CP_COND_WRITE_5_WRITE_DATA__MASK = 0xffffffff # macro
CP_COND_WRITE_5_WRITE_DATA__SHIFT = 0 # macro
REG_CP_COND_WRITE5_0 = 0x00000000 # macro
CP_COND_WRITE5_0_FUNCTION__MASK = 0x00000007 # macro
CP_COND_WRITE5_0_FUNCTION__SHIFT = 0 # macro
CP_COND_WRITE5_0_SIGNED_COMPARE = 0x00000008 # macro
CP_COND_WRITE5_0_POLL__MASK = 0x00000030 # macro
CP_COND_WRITE5_0_POLL__SHIFT = 4 # macro
CP_COND_WRITE5_0_WRITE_MEMORY = 0x00000100 # macro
REG_CP_COND_WRITE5_1 = 0x00000001 # macro
CP_COND_WRITE5_1_POLL_ADDR_LO__MASK = 0xffffffff # macro
CP_COND_WRITE5_1_POLL_ADDR_LO__SHIFT = 0 # macro
REG_CP_COND_WRITE5_2 = 0x00000002 # macro
CP_COND_WRITE5_2_POLL_ADDR_HI__MASK = 0xffffffff # macro
CP_COND_WRITE5_2_POLL_ADDR_HI__SHIFT = 0 # macro
REG_CP_COND_WRITE5_3 = 0x00000003 # macro
CP_COND_WRITE5_3_REF__MASK = 0xffffffff # macro
CP_COND_WRITE5_3_REF__SHIFT = 0 # macro
REG_CP_COND_WRITE5_4 = 0x00000004 # macro
CP_COND_WRITE5_4_MASK__MASK = 0xffffffff # macro
CP_COND_WRITE5_4_MASK__SHIFT = 0 # macro
REG_CP_COND_WRITE5_5 = 0x00000005 # macro
CP_COND_WRITE5_5_WRITE_ADDR_LO__MASK = 0xffffffff # macro
CP_COND_WRITE5_5_WRITE_ADDR_LO__SHIFT = 0 # macro
REG_CP_COND_WRITE5_6 = 0x00000006 # macro
CP_COND_WRITE5_6_WRITE_ADDR_HI__MASK = 0xffffffff # macro
CP_COND_WRITE5_6_WRITE_ADDR_HI__SHIFT = 0 # macro
REG_CP_COND_WRITE5_7 = 0x00000007 # macro
CP_COND_WRITE5_7_WRITE_DATA__MASK = 0xffffffff # macro
CP_COND_WRITE5_7_WRITE_DATA__SHIFT = 0 # macro
REG_CP_WAIT_MEM_GTE_0 = 0x00000000 # macro
CP_WAIT_MEM_GTE_0_RESERVED__MASK = 0xffffffff # macro
CP_WAIT_MEM_GTE_0_RESERVED__SHIFT = 0 # macro
REG_CP_WAIT_MEM_GTE_1 = 0x00000001 # macro
CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__MASK = 0xffffffff # macro
CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__SHIFT = 0 # macro
REG_CP_WAIT_MEM_GTE_2 = 0x00000002 # macro
CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__MASK = 0xffffffff # macro
CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__SHIFT = 0 # macro
REG_CP_WAIT_MEM_GTE_3 = 0x00000003 # macro
CP_WAIT_MEM_GTE_3_REF__MASK = 0xffffffff # macro
CP_WAIT_MEM_GTE_3_REF__SHIFT = 0 # macro
REG_CP_WAIT_REG_MEM_0 = 0x00000000 # macro
CP_WAIT_REG_MEM_0_FUNCTION__MASK = 0x00000007 # macro
CP_WAIT_REG_MEM_0_FUNCTION__SHIFT = 0 # macro
CP_WAIT_REG_MEM_0_SIGNED_COMPARE = 0x00000008 # macro
CP_WAIT_REG_MEM_0_POLL__MASK = 0x00000030 # macro
CP_WAIT_REG_MEM_0_POLL__SHIFT = 4 # macro
CP_WAIT_REG_MEM_0_WRITE_MEMORY = 0x00000100 # macro
REG_CP_WAIT_REG_MEM_1 = 0x00000001 # macro
CP_WAIT_REG_MEM_1_POLL_ADDR_LO__MASK = 0xffffffff # macro
CP_WAIT_REG_MEM_1_POLL_ADDR_LO__SHIFT = 0 # macro
REG_CP_WAIT_REG_MEM_2 = 0x00000002 # macro
CP_WAIT_REG_MEM_2_POLL_ADDR_HI__MASK = 0xffffffff # macro
CP_WAIT_REG_MEM_2_POLL_ADDR_HI__SHIFT = 0 # macro
REG_CP_WAIT_REG_MEM_3 = 0x00000003 # macro
CP_WAIT_REG_MEM_3_REF__MASK = 0xffffffff # macro
CP_WAIT_REG_MEM_3_REF__SHIFT = 0 # macro
REG_CP_WAIT_REG_MEM_4 = 0x00000004 # macro
CP_WAIT_REG_MEM_4_MASK__MASK = 0xffffffff # macro
CP_WAIT_REG_MEM_4_MASK__SHIFT = 0 # macro
REG_CP_WAIT_REG_MEM_5 = 0x00000005 # macro
CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES__MASK = 0xffffffff # macro
CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES__SHIFT = 0 # macro
REG_CP_WAIT_TWO_REGS_0 = 0x00000000 # macro
CP_WAIT_TWO_REGS_0_REG0__MASK = 0x0003ffff # macro
CP_WAIT_TWO_REGS_0_REG0__SHIFT = 0 # macro
REG_CP_WAIT_TWO_REGS_1 = 0x00000001 # macro
CP_WAIT_TWO_REGS_1_REG1__MASK = 0x0003ffff # macro
CP_WAIT_TWO_REGS_1_REG1__SHIFT = 0 # macro
REG_CP_WAIT_TWO_REGS_2 = 0x00000002 # macro
CP_WAIT_TWO_REGS_2_REF__MASK = 0xffffffff # macro
CP_WAIT_TWO_REGS_2_REF__SHIFT = 0 # macro
REG_CP_DISPATCH_COMPUTE_0 = 0x00000000 # macro
REG_CP_DISPATCH_COMPUTE_1 = 0x00000001 # macro
CP_DISPATCH_COMPUTE_1_X__MASK = 0xffffffff # macro
CP_DISPATCH_COMPUTE_1_X__SHIFT = 0 # macro
REG_CP_DISPATCH_COMPUTE_2 = 0x00000002 # macro
CP_DISPATCH_COMPUTE_2_Y__MASK = 0xffffffff # macro
CP_DISPATCH_COMPUTE_2_Y__SHIFT = 0 # macro
REG_CP_DISPATCH_COMPUTE_3 = 0x00000003 # macro
CP_DISPATCH_COMPUTE_3_Z__MASK = 0xffffffff # macro
CP_DISPATCH_COMPUTE_3_Z__SHIFT = 0 # macro
REG_CP_SET_RENDER_MODE_0 = 0x00000000 # macro
CP_SET_RENDER_MODE_0_MODE__MASK = 0x000001ff # macro
CP_SET_RENDER_MODE_0_MODE__SHIFT = 0 # macro
REG_CP_SET_RENDER_MODE_1 = 0x00000001 # macro
CP_SET_RENDER_MODE_1_ADDR_0_LO__MASK = 0xffffffff # macro
CP_SET_RENDER_MODE_1_ADDR_0_LO__SHIFT = 0 # macro
REG_CP_SET_RENDER_MODE_2 = 0x00000002 # macro
CP_SET_RENDER_MODE_2_ADDR_0_HI__MASK = 0xffffffff # macro
CP_SET_RENDER_MODE_2_ADDR_0_HI__SHIFT = 0 # macro
REG_CP_SET_RENDER_MODE_3 = 0x00000003 # macro
CP_SET_RENDER_MODE_3_VSC_ENABLE = 0x00000008 # macro
CP_SET_RENDER_MODE_3_GMEM_ENABLE = 0x00000010 # macro
REG_CP_SET_RENDER_MODE_4 = 0x00000004 # macro
REG_CP_SET_RENDER_MODE_5 = 0x00000005 # macro
CP_SET_RENDER_MODE_5_ADDR_1_LEN__MASK = 0xffffffff # macro
CP_SET_RENDER_MODE_5_ADDR_1_LEN__SHIFT = 0 # macro
REG_CP_SET_RENDER_MODE_6 = 0x00000006 # macro
CP_SET_RENDER_MODE_6_ADDR_1_LO__MASK = 0xffffffff # macro
CP_SET_RENDER_MODE_6_ADDR_1_LO__SHIFT = 0 # macro
REG_CP_SET_RENDER_MODE_7 = 0x00000007 # macro
CP_SET_RENDER_MODE_7_ADDR_1_HI__MASK = 0xffffffff # macro
CP_SET_RENDER_MODE_7_ADDR_1_HI__SHIFT = 0 # macro
REG_CP_COMPUTE_CHECKPOINT_0 = 0x00000000 # macro
CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__MASK = 0xffffffff # macro
CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__SHIFT = 0 # macro
REG_CP_COMPUTE_CHECKPOINT_1 = 0x00000001 # macro
CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__MASK = 0xffffffff # macro
CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__SHIFT = 0 # macro
REG_CP_COMPUTE_CHECKPOINT_2 = 0x00000002 # macro
REG_CP_COMPUTE_CHECKPOINT_3 = 0x00000003 # macro
REG_CP_COMPUTE_CHECKPOINT_4 = 0x00000004 # macro
CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__MASK = 0xffffffff # macro
CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__SHIFT = 0 # macro
REG_CP_COMPUTE_CHECKPOINT_5 = 0x00000005 # macro
CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__MASK = 0xffffffff # macro
CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__SHIFT = 0 # macro
REG_CP_COMPUTE_CHECKPOINT_6 = 0x00000006 # macro
CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__MASK = 0xffffffff # macro
CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__SHIFT = 0 # macro
REG_CP_COMPUTE_CHECKPOINT_7 = 0x00000007 # macro
REG_CP_PERFCOUNTER_ACTION_0 = 0x00000000 # macro
REG_CP_PERFCOUNTER_ACTION_1 = 0x00000001 # macro
CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__MASK = 0xffffffff # macro
CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__SHIFT = 0 # macro
REG_CP_PERFCOUNTER_ACTION_2 = 0x00000002 # macro
CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__MASK = 0xffffffff # macro
CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__SHIFT = 0 # macro
REG_CP_EVENT_WRITE_0 = 0x00000000 # macro
CP_EVENT_WRITE_0_EVENT__MASK = 0x000000ff # macro
CP_EVENT_WRITE_0_EVENT__SHIFT = 0 # macro
CP_EVENT_WRITE_0_TIMESTAMP = 0x40000000 # macro
CP_EVENT_WRITE_0_IRQ = 0x80000000 # macro
REG_CP_EVENT_WRITE_1 = 0x00000001 # macro
CP_EVENT_WRITE_1_ADDR_0_LO__MASK = 0xffffffff # macro
CP_EVENT_WRITE_1_ADDR_0_LO__SHIFT = 0 # macro
REG_CP_EVENT_WRITE_2 = 0x00000002 # macro
CP_EVENT_WRITE_2_ADDR_0_HI__MASK = 0xffffffff # macro
CP_EVENT_WRITE_2_ADDR_0_HI__SHIFT = 0 # macro
REG_CP_EVENT_WRITE_3 = 0x00000003 # macro
REG_CP_EVENT_WRITE7_0 = 0x00000000 # macro
CP_EVENT_WRITE7_0_EVENT__MASK = 0x000000ff # macro
CP_EVENT_WRITE7_0_EVENT__SHIFT = 0 # macro
CP_EVENT_WRITE7_0_WRITE_SAMPLE_COUNT = 0x00001000 # macro
CP_EVENT_WRITE7_0_SAMPLE_COUNT_END_OFFSET = 0x00002000 # macro
CP_EVENT_WRITE7_0_WRITE_ACCUM_SAMPLE_COUNT_DIFF = 0x00004000 # macro
CP_EVENT_WRITE7_0_INC_BV_COUNT = 0x00010000 # macro
CP_EVENT_WRITE7_0_INC_BR_COUNT = 0x00020000 # macro
CP_EVENT_WRITE7_0_CLEAR_RENDER_RESOURCE = 0x00040000 # macro
CP_EVENT_WRITE7_0_CLEAR_LRZ_RESOURCE = 0x00080000 # macro
CP_EVENT_WRITE7_0_WRITE_SRC__MASK = 0x00700000 # macro
CP_EVENT_WRITE7_0_WRITE_SRC__SHIFT = 20 # macro
CP_EVENT_WRITE7_0_WRITE_DST__MASK = 0x01000000 # macro
CP_EVENT_WRITE7_0_WRITE_DST__SHIFT = 24 # macro
CP_EVENT_WRITE7_0_WRITE_ENABLED = 0x08000000 # macro
REG_EV_DST_RAM_CP_EVENT_WRITE7_1 = 0x00000001 # macro
EV_DST_RAM_CP_EVENT_WRITE7_1_ADDR_0_LO__MASK = 0xffffffff # macro
EV_DST_RAM_CP_EVENT_WRITE7_1_ADDR_0_LO__SHIFT = 0 # macro
REG_EV_DST_RAM_CP_EVENT_WRITE7_2 = 0x00000002 # macro
EV_DST_RAM_CP_EVENT_WRITE7_2_ADDR_0_HI__MASK = 0xffffffff # macro
EV_DST_RAM_CP_EVENT_WRITE7_2_ADDR_0_HI__SHIFT = 0 # macro
REG_EV_DST_RAM_CP_EVENT_WRITE7_3 = 0x00000003 # macro
EV_DST_RAM_CP_EVENT_WRITE7_3_PAYLOAD_0__MASK = 0xffffffff # macro
EV_DST_RAM_CP_EVENT_WRITE7_3_PAYLOAD_0__SHIFT = 0 # macro
REG_EV_DST_RAM_CP_EVENT_WRITE7_4 = 0x00000004 # macro
EV_DST_RAM_CP_EVENT_WRITE7_4_PAYLOAD_1__MASK = 0xffffffff # macro
EV_DST_RAM_CP_EVENT_WRITE7_4_PAYLOAD_1__SHIFT = 0 # macro
REG_EV_DST_ONCHIP_CP_EVENT_WRITE7_1 = 0x00000001 # macro
EV_DST_ONCHIP_CP_EVENT_WRITE7_1_ONCHIP_ADDR_0__MASK = 0xffffffff # macro
EV_DST_ONCHIP_CP_EVENT_WRITE7_1_ONCHIP_ADDR_0__SHIFT = 0 # macro
REG_EV_DST_ONCHIP_CP_EVENT_WRITE7_3 = 0x00000003 # macro
EV_DST_ONCHIP_CP_EVENT_WRITE7_3_PAYLOAD_0__MASK = 0xffffffff # macro
EV_DST_ONCHIP_CP_EVENT_WRITE7_3_PAYLOAD_0__SHIFT = 0 # macro
REG_EV_DST_ONCHIP_CP_EVENT_WRITE7_4 = 0x00000004 # macro
EV_DST_ONCHIP_CP_EVENT_WRITE7_4_PAYLOAD_1__MASK = 0xffffffff # macro
EV_DST_ONCHIP_CP_EVENT_WRITE7_4_PAYLOAD_1__SHIFT = 0 # macro
REG_CP_BLIT_0 = 0x00000000 # macro
CP_BLIT_0_OP__MASK = 0x0000000f # macro
CP_BLIT_0_OP__SHIFT = 0 # macro
REG_CP_BLIT_1 = 0x00000001 # macro
CP_BLIT_1_SRC_X1__MASK = 0x00003fff # macro
CP_BLIT_1_SRC_X1__SHIFT = 0 # macro
CP_BLIT_1_SRC_Y1__MASK = 0x3fff0000 # macro
CP_BLIT_1_SRC_Y1__SHIFT = 16 # macro
REG_CP_BLIT_2 = 0x00000002 # macro
CP_BLIT_2_SRC_X2__MASK = 0x00003fff # macro
CP_BLIT_2_SRC_X2__SHIFT = 0 # macro
CP_BLIT_2_SRC_Y2__MASK = 0x3fff0000 # macro
CP_BLIT_2_SRC_Y2__SHIFT = 16 # macro
REG_CP_BLIT_3 = 0x00000003 # macro
CP_BLIT_3_DST_X1__MASK = 0x00003fff # macro
CP_BLIT_3_DST_X1__SHIFT = 0 # macro
CP_BLIT_3_DST_Y1__MASK = 0x3fff0000 # macro
CP_BLIT_3_DST_Y1__SHIFT = 16 # macro
REG_CP_BLIT_4 = 0x00000004 # macro
CP_BLIT_4_DST_X2__MASK = 0x00003fff # macro
CP_BLIT_4_DST_X2__SHIFT = 0 # macro
CP_BLIT_4_DST_Y2__MASK = 0x3fff0000 # macro
CP_BLIT_4_DST_Y2__SHIFT = 16 # macro
REG_CP_EXEC_CS_0 = 0x00000000 # macro
REG_CP_EXEC_CS_1 = 0x00000001 # macro
CP_EXEC_CS_1_NGROUPS_X__MASK = 0xffffffff # macro
CP_EXEC_CS_1_NGROUPS_X__SHIFT = 0 # macro
REG_CP_EXEC_CS_2 = 0x00000002 # macro
CP_EXEC_CS_2_NGROUPS_Y__MASK = 0xffffffff # macro
CP_EXEC_CS_2_NGROUPS_Y__SHIFT = 0 # macro
REG_CP_EXEC_CS_3 = 0x00000003 # macro
CP_EXEC_CS_3_NGROUPS_Z__MASK = 0xffffffff # macro
CP_EXEC_CS_3_NGROUPS_Z__SHIFT = 0 # macro
REG_A4XX_CP_EXEC_CS_INDIRECT_0 = 0x00000000 # macro
REG_A4XX_CP_EXEC_CS_INDIRECT_1 = 0x00000001 # macro
A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__MASK = 0xffffffff # macro
A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__SHIFT = 0 # macro
REG_A4XX_CP_EXEC_CS_INDIRECT_2 = 0x00000002 # macro
A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__MASK = 0x00000ffc # macro
A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__SHIFT = 2 # macro
A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__MASK = 0x003ff000 # macro
A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__SHIFT = 12 # macro
A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__MASK = 0xffc00000 # macro
A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__SHIFT = 22 # macro
REG_A5XX_CP_EXEC_CS_INDIRECT_1 = 0x00000001 # macro
A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__MASK = 0xffffffff # macro
A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__SHIFT = 0 # macro
REG_A5XX_CP_EXEC_CS_INDIRECT_2 = 0x00000002 # macro
A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__MASK = 0xffffffff # macro
A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__SHIFT = 0 # macro
REG_A5XX_CP_EXEC_CS_INDIRECT_3 = 0x00000003 # macro
A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__MASK = 0x00000ffc # macro
A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__SHIFT = 2 # macro
A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__MASK = 0x003ff000 # macro
A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__SHIFT = 12 # macro
A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__MASK = 0xffc00000 # macro
A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__SHIFT = 22 # macro
REG_A6XX_CP_SET_MARKER_0 = 0x00000000 # macro
A6XX_CP_SET_MARKER_0_MODE__MASK = 0x000001ff # macro
A6XX_CP_SET_MARKER_0_MODE__SHIFT = 0 # macro
A6XX_CP_SET_MARKER_0_MARKER__MASK = 0x0000000f # macro
A6XX_CP_SET_MARKER_0_MARKER__SHIFT = 0 # macro
# def REG_A6XX_CP_SET_PSEUDO_REG_(i0): # macro
# return (0x00000000+0x3*i0)
A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__MASK = 0x000007ff # macro
A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__SHIFT = 0 # macro
A6XX_CP_SET_PSEUDO_REG__1_LO__MASK = 0xffffffff # macro
A6XX_CP_SET_PSEUDO_REG__1_LO__SHIFT = 0 # macro
A6XX_CP_SET_PSEUDO_REG__2_HI__MASK = 0xffffffff # macro
A6XX_CP_SET_PSEUDO_REG__2_HI__SHIFT = 0 # macro
REG_A6XX_CP_REG_TEST_0 = 0x00000000 # macro
A6XX_CP_REG_TEST_0_REG__MASK = 0x0003ffff # macro
A6XX_CP_REG_TEST_0_REG__SHIFT = 0 # macro
A6XX_CP_REG_TEST_0_SCRATCH_MEM_OFFSET__MASK = 0x0003ffff # macro
A6XX_CP_REG_TEST_0_SCRATCH_MEM_OFFSET__SHIFT = 0 # macro
A6XX_CP_REG_TEST_0_SOURCE__MASK = 0x00040000 # macro
A6XX_CP_REG_TEST_0_SOURCE__SHIFT = 18 # macro
A6XX_CP_REG_TEST_0_BIT__MASK = 0x01f00000 # macro
A6XX_CP_REG_TEST_0_BIT__SHIFT = 20 # macro
A6XX_CP_REG_TEST_0_SKIP_WAIT_FOR_ME = 0x02000000 # macro
A6XX_CP_REG_TEST_0_PRED_BIT__MASK = 0x7c000000 # macro
A6XX_CP_REG_TEST_0_PRED_BIT__SHIFT = 26 # macro
A6XX_CP_REG_TEST_0_PRED_UPDATE = 0x80000000 # macro
REG_A6XX_CP_REG_TEST_PRED_MASK = 0x00000001 # macro
REG_A6XX_CP_REG_TEST_PRED_VAL = 0x00000002 # macro
REG_CP_COND_REG_EXEC_0 = 0x00000000 # macro
CP_COND_REG_EXEC_0_REG0__MASK = 0x0003ffff # macro
CP_COND_REG_EXEC_0_REG0__SHIFT = 0 # macro
CP_COND_REG_EXEC_0_PRED_BIT__MASK = 0x007c0000 # macro
CP_COND_REG_EXEC_0_PRED_BIT__SHIFT = 18 # macro
CP_COND_REG_EXEC_0_SKIP_WAIT_FOR_ME = 0x00800000 # macro
CP_COND_REG_EXEC_0_ONCHIP_MEM = 0x01000000 # macro
CP_COND_REG_EXEC_0_BINNING = 0x02000000 # macro
CP_COND_REG_EXEC_0_GMEM = 0x04000000 # macro
CP_COND_REG_EXEC_0_SYSMEM = 0x08000000 # macro
CP_COND_REG_EXEC_0_BV = 0x02000000 # macro
CP_COND_REG_EXEC_0_BR = 0x04000000 # macro
CP_COND_REG_EXEC_0_LPAC = 0x08000000 # macro
CP_COND_REG_EXEC_0_MODE__MASK = 0xf0000000 # macro
CP_COND_REG_EXEC_0_MODE__SHIFT = 28 # macro
REG_PRED_TEST_CP_COND_REG_EXEC_1 = 0x00000001 # macro
PRED_TEST_CP_COND_REG_EXEC_1_DWORDS__MASK = 0x00ffffff # macro
PRED_TEST_CP_COND_REG_EXEC_1_DWORDS__SHIFT = 0 # macro
REG_REG_COMPARE_CP_COND_REG_EXEC_1 = 0x00000001 # macro
REG_COMPARE_CP_COND_REG_EXEC_1_REG1__MASK = 0x0003ffff # macro
REG_COMPARE_CP_COND_REG_EXEC_1_REG1__SHIFT = 0 # macro
REG_COMPARE_CP_COND_REG_EXEC_1_ONCHIP_MEM = 0x01000000 # macro
REG_RENDER_MODE_CP_COND_REG_EXEC_1 = 0x00000001 # macro
RENDER_MODE_CP_COND_REG_EXEC_1_DWORDS__MASK = 0x00ffffff # macro
RENDER_MODE_CP_COND_REG_EXEC_1_DWORDS__SHIFT = 0 # macro
REG_REG_COMPARE_IMM_CP_COND_REG_EXEC_1 = 0x00000001 # macro
REG_COMPARE_IMM_CP_COND_REG_EXEC_1_IMM__MASK = 0xffffffff # macro
REG_COMPARE_IMM_CP_COND_REG_EXEC_1_IMM__SHIFT = 0 # macro
REG_THREAD_MODE_CP_COND_REG_EXEC_1 = 0x00000001 # macro
THREAD_MODE_CP_COND_REG_EXEC_1_DWORDS__MASK = 0x00ffffff # macro
THREAD_MODE_CP_COND_REG_EXEC_1_DWORDS__SHIFT = 0 # macro
REG_CP_COND_REG_EXEC_2 = 0x00000002 # macro
CP_COND_REG_EXEC_2_DWORDS__MASK = 0x00ffffff # macro
CP_COND_REG_EXEC_2_DWORDS__SHIFT = 0 # macro
REG_CP_COND_EXEC_0 = 0x00000000 # macro
CP_COND_EXEC_0_ADDR0_LO__MASK = 0xffffffff # macro
CP_COND_EXEC_0_ADDR0_LO__SHIFT = 0 # macro
REG_CP_COND_EXEC_1 = 0x00000001 # macro
CP_COND_EXEC_1_ADDR0_HI__MASK = 0xffffffff # macro
CP_COND_EXEC_1_ADDR0_HI__SHIFT = 0 # macro
REG_CP_COND_EXEC_2 = 0x00000002 # macro
CP_COND_EXEC_2_ADDR1_LO__MASK = 0xffffffff # macro
CP_COND_EXEC_2_ADDR1_LO__SHIFT = 0 # macro
REG_CP_COND_EXEC_3 = 0x00000003 # macro
CP_COND_EXEC_3_ADDR1_HI__MASK = 0xffffffff # macro
CP_COND_EXEC_3_ADDR1_HI__SHIFT = 0 # macro
REG_CP_COND_EXEC_4 = 0x00000004 # macro
CP_COND_EXEC_4_REF__MASK = 0xffffffff # macro
CP_COND_EXEC_4_REF__SHIFT = 0 # macro
REG_CP_COND_EXEC_5 = 0x00000005 # macro
CP_COND_EXEC_5_DWORDS__MASK = 0xffffffff # macro
CP_COND_EXEC_5_DWORDS__SHIFT = 0 # macro
REG_CP_SET_CTXSWITCH_IB_0 = 0x00000000 # macro
CP_SET_CTXSWITCH_IB_0_ADDR_LO__MASK = 0xffffffff # macro
CP_SET_CTXSWITCH_IB_0_ADDR_LO__SHIFT = 0 # macro
REG_CP_SET_CTXSWITCH_IB_1 = 0x00000001 # macro
CP_SET_CTXSWITCH_IB_1_ADDR_HI__MASK = 0xffffffff # macro
CP_SET_CTXSWITCH_IB_1_ADDR_HI__SHIFT = 0 # macro
REG_CP_SET_CTXSWITCH_IB_2 = 0x00000002 # macro
CP_SET_CTXSWITCH_IB_2_DWORDS__MASK = 0x000fffff # macro
CP_SET_CTXSWITCH_IB_2_DWORDS__SHIFT = 0 # macro
CP_SET_CTXSWITCH_IB_2_TYPE__MASK = 0x00300000 # macro
CP_SET_CTXSWITCH_IB_2_TYPE__SHIFT = 20 # macro
REG_CP_REG_WRITE_0 = 0x00000000 # macro
CP_REG_WRITE_0_TRACKER__MASK = 0x0000000f # macro
CP_REG_WRITE_0_TRACKER__SHIFT = 0 # macro
REG_CP_REG_WRITE_1 = 0x00000001 # macro
REG_CP_REG_WRITE_2 = 0x00000002 # macro
REG_CP_SMMU_TABLE_UPDATE_0 = 0x00000000 # macro
CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__MASK = 0xffffffff # macro
CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__SHIFT = 0 # macro
REG_CP_SMMU_TABLE_UPDATE_1 = 0x00000001 # macro
CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__MASK = 0x0000ffff # macro
CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__SHIFT = 0 # macro
CP_SMMU_TABLE_UPDATE_1_ASID__MASK = 0xffff0000 # macro
CP_SMMU_TABLE_UPDATE_1_ASID__SHIFT = 16 # macro
REG_CP_SMMU_TABLE_UPDATE_2 = 0x00000002 # macro
CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__MASK = 0xffffffff # macro
CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__SHIFT = 0 # macro
REG_CP_SMMU_TABLE_UPDATE_3 = 0x00000003 # macro
CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__MASK = 0xffffffff # macro
CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__SHIFT = 0 # macro
REG_CP_START_BIN_BIN_COUNT = 0x00000000 # macro
REG_CP_START_BIN_PREFIX_ADDR = 0x00000001 # macro
REG_CP_START_BIN_PREFIX_DWORDS = 0x00000003 # macro
REG_CP_START_BIN_BODY_DWORDS = 0x00000004 # macro
REG_CP_WAIT_TIMESTAMP_0 = 0x00000000 # macro
CP_WAIT_TIMESTAMP_0_WAIT_VALUE_SRC__MASK = 0x00000003 # macro
CP_WAIT_TIMESTAMP_0_WAIT_VALUE_SRC__SHIFT = 0 # macro
CP_WAIT_TIMESTAMP_0_WAIT_DST__MASK = 0x00000010 # macro
CP_WAIT_TIMESTAMP_0_WAIT_DST__SHIFT = 4 # macro
REG_TS_WAIT_RAM_CP_WAIT_TIMESTAMP_ADDR = 0x00000001 # macro
REG_TS_WAIT_ONCHIP_CP_WAIT_TIMESTAMP_ONCHIP_ADDR_0 = 0x00000001 # macro
REG_CP_WAIT_TIMESTAMP_SRC_0 = 0x00000003 # macro
REG_CP_WAIT_TIMESTAMP_SRC_1 = 0x00000004 # macro
REG_CP_BV_BR_COUNT_OPS_0 = 0x00000000 # macro
CP_BV_BR_COUNT_OPS_0_OP__MASK = 0x0000000f # macro
CP_BV_BR_COUNT_OPS_0_OP__SHIFT = 0 # macro
REG_CP_BV_BR_COUNT_OPS_1 = 0x00000001 # macro
CP_BV_BR_COUNT_OPS_1_BR_OFFSET__MASK = 0x0000ffff # macro
CP_BV_BR_COUNT_OPS_1_BR_OFFSET__SHIFT = 0 # macro
REG_CP_MODIFY_TIMESTAMP_0 = 0x00000000 # macro
CP_MODIFY_TIMESTAMP_0_ADD__MASK = 0x000000ff # macro
CP_MODIFY_TIMESTAMP_0_ADD__SHIFT = 0 # macro
CP_MODIFY_TIMESTAMP_0_OP__MASK = 0xf0000000 # macro
CP_MODIFY_TIMESTAMP_0_OP__SHIFT = 28 # macro
REG_CP_MEM_TO_SCRATCH_MEM_0 = 0x00000000 # macro
CP_MEM_TO_SCRATCH_MEM_0_CNT__MASK = 0x0000003f # macro
CP_MEM_TO_SCRATCH_MEM_0_CNT__SHIFT = 0 # macro
REG_CP_MEM_TO_SCRATCH_MEM_1 = 0x00000001 # macro
CP_MEM_TO_SCRATCH_MEM_1_OFFSET__MASK = 0x0000003f # macro
CP_MEM_TO_SCRATCH_MEM_1_OFFSET__SHIFT = 0 # macro
REG_CP_MEM_TO_SCRATCH_MEM_2 = 0x00000002 # macro
CP_MEM_TO_SCRATCH_MEM_2_SRC__MASK = 0xffffffff # macro
CP_MEM_TO_SCRATCH_MEM_2_SRC__SHIFT = 0 # macro
REG_CP_MEM_TO_SCRATCH_MEM_3 = 0x00000003 # macro
CP_MEM_TO_SCRATCH_MEM_3_SRC_HI__MASK = 0xffffffff # macro
CP_MEM_TO_SCRATCH_MEM_3_SRC_HI__SHIFT = 0 # macro
REG_CP_THREAD_CONTROL_0 = 0x00000000 # macro
CP_THREAD_CONTROL_0_THREAD__MASK = 0x00000003 # macro
CP_THREAD_CONTROL_0_THREAD__SHIFT = 0 # macro
CP_THREAD_CONTROL_0_CONCURRENT_BIN_DISABLE = 0x08000000 # macro
CP_THREAD_CONTROL_0_SYNC_THREADS = 0x80000000 # macro
REG_CP_FIXED_STRIDE_DRAW_TABLE_IB_BASE = 0x00000000 # macro
REG_CP_FIXED_STRIDE_DRAW_TABLE_2 = 0x00000002 # macro
CP_FIXED_STRIDE_DRAW_TABLE_2_IB_SIZE__MASK = 0x00000fff # macro
CP_FIXED_STRIDE_DRAW_TABLE_2_IB_SIZE__SHIFT = 0 # macro
CP_FIXED_STRIDE_DRAW_TABLE_2_STRIDE__MASK = 0xfff00000 # macro
CP_FIXED_STRIDE_DRAW_TABLE_2_STRIDE__SHIFT = 20 # macro
REG_CP_FIXED_STRIDE_DRAW_TABLE_3 = 0x00000003 # macro
CP_FIXED_STRIDE_DRAW_TABLE_3_COUNT__MASK = 0xffffffff # macro
CP_FIXED_STRIDE_DRAW_TABLE_3_COUNT__SHIFT = 0 # macro
REG_CP_RESET_CONTEXT_STATE_0 = 0x00000000 # macro
CP_RESET_CONTEXT_STATE_0_CLEAR_ON_CHIP_TS = 0x00000001 # macro
CP_RESET_CONTEXT_STATE_0_CLEAR_RESOURCE_TABLE = 0x00000002 # macro
CP_RESET_CONTEXT_STATE_0_CLEAR_GLOBAL_LOCAL_TS = 0x00000004 # macro
REG_AXXX_CP_RB_BASE = 0x000001c0 # macro
REG_AXXX_CP_RB_CNTL = 0x000001c1 # macro
AXXX_CP_RB_CNTL_BUFSZ__MASK = 0x0000003f # macro
AXXX_CP_RB_CNTL_BUFSZ__SHIFT = 0 # macro
AXXX_CP_RB_CNTL_BLKSZ__MASK = 0x00003f00 # macro
AXXX_CP_RB_CNTL_BLKSZ__SHIFT = 8 # macro
AXXX_CP_RB_CNTL_BUF_SWAP__MASK = 0x00030000 # macro
AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT = 16 # macro
AXXX_CP_RB_CNTL_POLL_EN = 0x00100000 # macro
AXXX_CP_RB_CNTL_NO_UPDATE = 0x08000000 # macro
AXXX_CP_RB_CNTL_RPTR_WR_EN = 0x80000000 # macro
REG_AXXX_CP_RB_RPTR_ADDR = 0x000001c3 # macro
AXXX_CP_RB_RPTR_ADDR_SWAP__MASK = 0x00000003 # macro
AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT = 0 # macro
AXXX_CP_RB_RPTR_ADDR_ADDR__MASK = 0xfffffffc # macro
AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT = 2 # macro
REG_AXXX_CP_RB_RPTR = 0x000001c4 # macro
REG_AXXX_CP_RB_WPTR = 0x000001c5 # macro
REG_AXXX_CP_RB_WPTR_DELAY = 0x000001c6 # macro
REG_AXXX_CP_RB_RPTR_WR = 0x000001c7 # macro
REG_AXXX_CP_RB_WPTR_BASE = 0x000001c8 # macro
REG_AXXX_CP_QUEUE_THRESHOLDS = 0x000001d5 # macro
AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__MASK = 0x0000000f # macro
AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__SHIFT = 0 # macro
AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__MASK = 0x00000f00 # macro
AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__SHIFT = 8 # macro
AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__MASK = 0x000f0000 # macro
AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__SHIFT = 16 # macro
REG_AXXX_CP_MEQ_THRESHOLDS = 0x000001d6 # macro
AXXX_CP_MEQ_THRESHOLDS_MEQ_END__MASK = 0x001f0000 # macro
AXXX_CP_MEQ_THRESHOLDS_MEQ_END__SHIFT = 16 # macro
AXXX_CP_MEQ_THRESHOLDS_ROQ_END__MASK = 0x1f000000 # macro
AXXX_CP_MEQ_THRESHOLDS_ROQ_END__SHIFT = 24 # macro
REG_AXXX_CP_CSQ_AVAIL = 0x000001d7 # macro
AXXX_CP_CSQ_AVAIL_RING__MASK = 0x0000007f # macro
AXXX_CP_CSQ_AVAIL_RING__SHIFT = 0 # macro
AXXX_CP_CSQ_AVAIL_IB1__MASK = 0x00007f00 # macro
AXXX_CP_CSQ_AVAIL_IB1__SHIFT = 8 # macro
AXXX_CP_CSQ_AVAIL_IB2__MASK = 0x007f0000 # macro
AXXX_CP_CSQ_AVAIL_IB2__SHIFT = 16 # macro
REG_AXXX_CP_STQ_AVAIL = 0x000001d8 # macro
AXXX_CP_STQ_AVAIL_ST__MASK = 0x0000007f # macro
AXXX_CP_STQ_AVAIL_ST__SHIFT = 0 # macro
REG_AXXX_CP_MEQ_AVAIL = 0x000001d9 # macro
AXXX_CP_MEQ_AVAIL_MEQ__MASK = 0x0000001f # macro
AXXX_CP_MEQ_AVAIL_MEQ__SHIFT = 0 # macro
REG_AXXX_SCRATCH_UMSK = 0x000001dc # macro
AXXX_SCRATCH_UMSK_UMSK__MASK = 0x000000ff # macro
AXXX_SCRATCH_UMSK_UMSK__SHIFT = 0 # macro
AXXX_SCRATCH_UMSK_SWAP__MASK = 0x00030000 # macro
AXXX_SCRATCH_UMSK_SWAP__SHIFT = 16 # macro
REG_AXXX_SCRATCH_ADDR = 0x000001dd # macro
REG_AXXX_CP_ME_RDADDR = 0x000001ea # macro
REG_AXXX_CP_STATE_DEBUG_INDEX = 0x000001ec # macro
REG_AXXX_CP_STATE_DEBUG_DATA = 0x000001ed # macro
REG_AXXX_CP_INT_CNTL = 0x000001f2 # macro
AXXX_CP_INT_CNTL_SW_INT_MASK = 0x00080000 # macro
AXXX_CP_INT_CNTL_T0_PACKET_IN_IB_MASK = 0x00800000 # macro
AXXX_CP_INT_CNTL_OPCODE_ERROR_MASK = 0x01000000 # macro
AXXX_CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK = 0x02000000 # macro
AXXX_CP_INT_CNTL_RESERVED_BIT_ERROR_MASK = 0x04000000 # macro
AXXX_CP_INT_CNTL_IB_ERROR_MASK = 0x08000000 # macro
AXXX_CP_INT_CNTL_IB2_INT_MASK = 0x20000000 # macro
AXXX_CP_INT_CNTL_IB1_INT_MASK = 0x40000000 # macro
AXXX_CP_INT_CNTL_RB_INT_MASK = 0x80000000 # macro
REG_AXXX_CP_INT_STATUS = 0x000001f3 # macro
REG_AXXX_CP_INT_ACK = 0x000001f4 # macro
REG_AXXX_CP_ME_CNTL = 0x000001f6 # macro
AXXX_CP_ME_CNTL_BUSY = 0x20000000 # macro
AXXX_CP_ME_CNTL_HALT = 0x10000000 # macro
REG_AXXX_CP_ME_STATUS = 0x000001f7 # macro
REG_AXXX_CP_ME_RAM_WADDR = 0x000001f8 # macro
REG_AXXX_CP_ME_RAM_RADDR = 0x000001f9 # macro
REG_AXXX_CP_ME_RAM_DATA = 0x000001fa # macro
REG_AXXX_CP_DEBUG = 0x000001fc # macro
AXXX_CP_DEBUG_PREDICATE_DISABLE = 0x00800000 # macro
AXXX_CP_DEBUG_PROG_END_PTR_ENABLE = 0x01000000 # macro
AXXX_CP_DEBUG_MIU_128BIT_WRITE_ENABLE = 0x02000000 # macro
AXXX_CP_DEBUG_PREFETCH_PASS_NOPS = 0x04000000 # macro
AXXX_CP_DEBUG_DYNAMIC_CLK_DISABLE = 0x08000000 # macro
AXXX_CP_DEBUG_PREFETCH_MATCH_DISABLE = 0x10000000 # macro
AXXX_CP_DEBUG_SIMPLE_ME_FLOW_CONTROL = 0x40000000 # macro
AXXX_CP_DEBUG_MIU_WRITE_PACK_DISABLE = 0x80000000 # macro
REG_AXXX_CP_CSQ_RB_STAT = 0x000001fd # macro
AXXX_CP_CSQ_RB_STAT_RPTR__MASK = 0x0000007f # macro
AXXX_CP_CSQ_RB_STAT_RPTR__SHIFT = 0 # macro
AXXX_CP_CSQ_RB_STAT_WPTR__MASK = 0x007f0000 # macro
AXXX_CP_CSQ_RB_STAT_WPTR__SHIFT = 16 # macro
REG_AXXX_CP_CSQ_IB1_STAT = 0x000001fe # macro
AXXX_CP_CSQ_IB1_STAT_RPTR__MASK = 0x0000007f # macro
AXXX_CP_CSQ_IB1_STAT_RPTR__SHIFT = 0 # macro
AXXX_CP_CSQ_IB1_STAT_WPTR__MASK = 0x007f0000 # macro
AXXX_CP_CSQ_IB1_STAT_WPTR__SHIFT = 16 # macro
REG_AXXX_CP_CSQ_IB2_STAT = 0x000001ff # macro
AXXX_CP_CSQ_IB2_STAT_RPTR__MASK = 0x0000007f # macro
AXXX_CP_CSQ_IB2_STAT_RPTR__SHIFT = 0 # macro
AXXX_CP_CSQ_IB2_STAT_WPTR__MASK = 0x007f0000 # macro
AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT = 16 # macro
REG_AXXX_CP_NON_PREFETCH_CNTRS = 0x00000440 # macro
REG_AXXX_CP_STQ_ST_STAT = 0x00000443 # macro
REG_AXXX_CP_ST_BASE = 0x0000044d # macro
REG_AXXX_CP_ST_BUFSZ = 0x0000044e # macro
REG_AXXX_CP_MEQ_STAT = 0x0000044f # macro
REG_AXXX_CP_MIU_TAG_STAT = 0x00000452 # macro
REG_AXXX_CP_BIN_MASK_LO = 0x00000454 # macro
REG_AXXX_CP_BIN_MASK_HI = 0x00000455 # macro
REG_AXXX_CP_BIN_SELECT_LO = 0x00000456 # macro
REG_AXXX_CP_BIN_SELECT_HI = 0x00000457 # macro
REG_AXXX_CP_IB1_BASE = 0x00000458 # macro
REG_AXXX_CP_IB1_BUFSZ = 0x00000459 # macro
REG_AXXX_CP_IB2_BASE = 0x0000045a # macro
REG_AXXX_CP_IB2_BUFSZ = 0x0000045b # macro
REG_AXXX_CP_STAT = 0x0000047f # macro
AXXX_CP_STAT_CP_BUSY = 0x80000000 # macro
AXXX_CP_STAT_VS_EVENT_FIFO_BUSY = 0x40000000 # macro
AXXX_CP_STAT_PS_EVENT_FIFO_BUSY = 0x20000000 # macro
AXXX_CP_STAT_CF_EVENT_FIFO_BUSY = 0x10000000 # macro
AXXX_CP_STAT_RB_EVENT_FIFO_BUSY = 0x08000000 # macro
AXXX_CP_STAT_ME_BUSY = 0x04000000 # macro
AXXX_CP_STAT_MIU_WR_C_BUSY = 0x02000000 # macro
AXXX_CP_STAT_CP_3D_BUSY = 0x00800000 # macro
AXXX_CP_STAT_CP_NRT_BUSY = 0x00400000 # macro
AXXX_CP_STAT_RBIU_SCRATCH_BUSY = 0x00200000 # macro
AXXX_CP_STAT_RCIU_ME_BUSY = 0x00100000 # macro
AXXX_CP_STAT_RCIU_PFP_BUSY = 0x00080000 # macro
AXXX_CP_STAT_MEQ_RING_BUSY = 0x00040000 # macro
AXXX_CP_STAT_PFP_BUSY = 0x00020000 # macro
AXXX_CP_STAT_ST_QUEUE_BUSY = 0x00010000 # macro
AXXX_CP_STAT_INDIRECT2_QUEUE_BUSY = 0x00002000 # macro
AXXX_CP_STAT_INDIRECTS_QUEUE_BUSY = 0x00001000 # macro
AXXX_CP_STAT_RING_QUEUE_BUSY = 0x00000800 # macro
AXXX_CP_STAT_CSF_BUSY = 0x00000400 # macro
AXXX_CP_STAT_CSF_ST_BUSY = 0x00000200 # macro
AXXX_CP_STAT_EVENT_BUSY = 0x00000100 # macro
AXXX_CP_STAT_CSF_INDIRECT2_BUSY = 0x00000080 # macro
AXXX_CP_STAT_CSF_INDIRECTS_BUSY = 0x00000040 # macro
AXXX_CP_STAT_CSF_RING_BUSY = 0x00000020 # macro
AXXX_CP_STAT_RCIU_BUSY = 0x00000010 # macro
AXXX_CP_STAT_RBIU_BUSY = 0x00000008 # macro
AXXX_CP_STAT_MIU_RD_RETURN_BUSY = 0x00000004 # macro
AXXX_CP_STAT_MIU_RD_REQ_BUSY = 0x00000002 # macro
AXXX_CP_STAT_MIU_WR_BUSY = 0x00000001 # macro
REG_AXXX_CP_SCRATCH_REG0 = 0x00000578 # macro
REG_AXXX_CP_SCRATCH_REG1 = 0x00000579 # macro
REG_AXXX_CP_SCRATCH_REG2 = 0x0000057a # macro
REG_AXXX_CP_SCRATCH_REG3 = 0x0000057b # macro
REG_AXXX_CP_SCRATCH_REG4 = 0x0000057c # macro
REG_AXXX_CP_SCRATCH_REG5 = 0x0000057d # macro
REG_AXXX_CP_SCRATCH_REG6 = 0x0000057e # macro
REG_AXXX_CP_SCRATCH_REG7 = 0x0000057f # macro
REG_AXXX_CP_ME_VS_EVENT_SRC = 0x00000600 # macro
REG_AXXX_CP_ME_VS_EVENT_ADDR = 0x00000601 # macro
REG_AXXX_CP_ME_VS_EVENT_DATA = 0x00000602 # macro
REG_AXXX_CP_ME_VS_EVENT_ADDR_SWM = 0x00000603 # macro
REG_AXXX_CP_ME_VS_EVENT_DATA_SWM = 0x00000604 # macro
REG_AXXX_CP_ME_PS_EVENT_SRC = 0x00000605 # macro
REG_AXXX_CP_ME_PS_EVENT_ADDR = 0x00000606 # macro
REG_AXXX_CP_ME_PS_EVENT_DATA = 0x00000607 # macro
REG_AXXX_CP_ME_PS_EVENT_ADDR_SWM = 0x00000608 # macro
REG_AXXX_CP_ME_PS_EVENT_DATA_SWM = 0x00000609 # macro
REG_AXXX_CP_ME_CF_EVENT_SRC = 0x0000060a # macro
REG_AXXX_CP_ME_CF_EVENT_ADDR = 0x0000060b # macro
REG_AXXX_CP_ME_CF_EVENT_DATA = 0x0000060c # macro
REG_AXXX_CP_ME_NRT_ADDR = 0x0000060d # macro
REG_AXXX_CP_ME_NRT_DATA = 0x0000060e # macro
REG_AXXX_CP_ME_VS_FETCH_DONE_SRC = 0x00000612 # macro
REG_AXXX_CP_ME_VS_FETCH_DONE_ADDR = 0x00000613 # macro
REG_AXXX_CP_ME_VS_FETCH_DONE_DATA = 0x00000614 # macro
A6XX_RBBM_INT_0_MASK_RBBM_GPU_IDLE = 0x00000001 # macro
A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR = 0x00000002 # macro
A6XX_RBBM_INT_0_MASK_CP_IPC_INTR_0 = 0x00000010 # macro
A6XX_RBBM_INT_0_MASK_CP_IPC_INTR_1 = 0x00000020 # macro
A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW = 0x00000040 # macro
A6XX_RBBM_INT_0_MASK_RBBM_GPC_ERROR = 0x00000080 # macro
A6XX_RBBM_INT_0_MASK_CP_SW = 0x00000100 # macro
A6XX_RBBM_INT_0_MASK_CP_HW_ERROR = 0x00000200 # macro
A6XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_DEPTH_TS = 0x00000400 # macro
A6XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_COLOR_TS = 0x00000800 # macro
A6XX_RBBM_INT_0_MASK_CP_CCU_RESOLVE_TS = 0x00001000 # macro
A6XX_RBBM_INT_0_MASK_CP_IB2 = 0x00002000 # macro
A6XX_RBBM_INT_0_MASK_CP_IB1 = 0x00004000 # macro
A6XX_RBBM_INT_0_MASK_CP_RB = 0x00008000 # macro
A6XX_RBBM_INT_0_MASK_PM4CPINTERRUPT = 0x00008000 # macro
A6XX_RBBM_INT_0_MASK_PM4CPINTERRUPTLPAC = 0x00010000 # macro
A6XX_RBBM_INT_0_MASK_CP_RB_DONE_TS = 0x00020000 # macro
A6XX_RBBM_INT_0_MASK_CP_WT_DONE_TS = 0x00040000 # macro
A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS = 0x00100000 # macro
A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS_LPAC = 0x00200000 # macro
A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW = 0x00400000 # macro
A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT = 0x00800000 # macro
A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS = 0x01000000 # macro
A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR = 0x02000000 # macro
A6XX_RBBM_INT_0_MASK_DEBBUS_INTR_0 = 0x04000000 # macro
A6XX_RBBM_INT_0_MASK_DEBBUS_INTR_1 = 0x08000000 # macro
A6XX_RBBM_INT_0_MASK_TSBWRITEERROR = 0x10000000 # macro
A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION = 0x20000000 # macro
A6XX_RBBM_INT_0_MASK_ISDB_CPU_IRQ = 0x40000000 # macro
A6XX_RBBM_INT_0_MASK_ISDB_UNDER_DEBUG = 0x80000000 # macro
A6XX_CP_INT_CP_OPCODE_ERROR = 0x00000001 # macro
A6XX_CP_INT_CP_UCODE_ERROR = 0x00000002 # macro
A6XX_CP_INT_CP_HW_FAULT_ERROR = 0x00000004 # macro
A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR = 0x00000010 # macro
A6XX_CP_INT_CP_AHB_ERROR = 0x00000020 # macro
A6XX_CP_INT_CP_VSD_PARITY_ERROR = 0x00000040 # macro
A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR = 0x00000080 # macro
A6XX_CP_INT_CP_OPCODE_ERROR_LPAC = 0x00000100 # macro
A6XX_CP_INT_CP_UCODE_ERROR_LPAC = 0x00000200 # macro
A6XX_CP_INT_CP_HW_FAULT_ERROR_LPAC = 0x00000400 # macro
A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR_LPAC = 0x00000800 # macro
A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR_LPAC = 0x00001000 # macro
A6XX_CP_INT_CP_OPCODE_ERROR_BV = 0x00002000 # macro
A6XX_CP_INT_CP_UCODE_ERROR_BV = 0x00004000 # macro
A6XX_CP_INT_CP_HW_FAULT_ERROR_BV = 0x00008000 # macro
A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR_BV = 0x00010000 # macro
A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR_BV = 0x00020000 # macro
REG_A6XX_CP_RB_BASE = 0x00000800 # macro
REG_A6XX_CP_RB_CNTL = 0x00000802 # macro
REG_A6XX_CP_RB_RPTR_ADDR = 0x00000804 # macro
REG_A6XX_CP_RB_RPTR = 0x00000806 # macro
REG_A6XX_CP_RB_WPTR = 0x00000807 # macro
REG_A6XX_CP_SQE_CNTL = 0x00000808 # macro
REG_A6XX_CP_CP2GMU_STATUS = 0x00000812 # macro
A6XX_CP_CP2GMU_STATUS_IFPC = 0x00000001 # macro
REG_A6XX_CP_HW_FAULT = 0x00000821 # macro
REG_A6XX_CP_INTERRUPT_STATUS = 0x00000823 # macro
REG_A6XX_CP_PROTECT_STATUS = 0x00000824 # macro
REG_A6XX_CP_STATUS_1 = 0x00000825 # macro
REG_A6XX_CP_SQE_INSTR_BASE = 0x00000830 # macro
REG_A6XX_CP_MISC_CNTL = 0x00000840 # macro
REG_A6XX_CP_APRIV_CNTL = 0x00000844 # macro
A6XX_CP_APRIV_CNTL_CDWRITE = 0x00000040 # macro
A6XX_CP_APRIV_CNTL_CDREAD = 0x00000020 # macro
A6XX_CP_APRIV_CNTL_RBRPWB = 0x00000008 # macro
A6XX_CP_APRIV_CNTL_RBPRIVLEVEL = 0x00000004 # macro
A6XX_CP_APRIV_CNTL_RBFETCH = 0x00000002 # macro
A6XX_CP_APRIV_CNTL_ICACHE = 0x00000001 # macro
REG_A6XX_CP_PREEMPT_THRESHOLD = 0x000008c0 # macro
REG_A6XX_CP_ROQ_THRESHOLDS_1 = 0x000008c1 # macro
A6XX_CP_ROQ_THRESHOLDS_1_MRB_START__MASK = 0x000000ff # macro
A6XX_CP_ROQ_THRESHOLDS_1_MRB_START__SHIFT = 0 # macro
A6XX_CP_ROQ_THRESHOLDS_1_VSD_START__MASK = 0x0000ff00 # macro
A6XX_CP_ROQ_THRESHOLDS_1_VSD_START__SHIFT = 8 # macro
A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__MASK = 0x00ff0000 # macro
A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__SHIFT = 16 # macro
A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__MASK = 0xff000000 # macro
A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__SHIFT = 24 # macro
REG_A6XX_CP_ROQ_THRESHOLDS_2 = 0x000008c2 # macro
A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__MASK = 0x000001ff # macro
A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__SHIFT = 0 # macro
A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__MASK = 0xffff0000 # macro
A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__SHIFT = 16 # macro
REG_A6XX_CP_MEM_POOL_SIZE = 0x000008c3 # macro
REG_A6XX_CP_CHICKEN_DBG = 0x00000841 # macro
REG_A6XX_CP_ADDR_MODE_CNTL = 0x00000842 # macro
REG_A6XX_CP_DBG_ECO_CNTL = 0x00000843 # macro
REG_A6XX_CP_PROTECT_CNTL = 0x0000084f # macro
A6XX_CP_PROTECT_CNTL_LAST_SPAN_INF_RANGE = 0x00000008 # macro
A6XX_CP_PROTECT_CNTL_ACCESS_FAULT_ON_VIOL_EN = 0x00000002 # macro
A6XX_CP_PROTECT_CNTL_ACCESS_PROT_EN = 0x00000001 # macro
# def REG_A6XX_CP_SCRATCH(i0): # macro
# return (0x00000883+0x1*i0)
# def REG_A6XX_CP_PROTECT(i0): # macro
# return (0x00000850+0x1*i0)
A6XX_CP_PROTECT_REG_BASE_ADDR__MASK = 0x0003ffff # macro
A6XX_CP_PROTECT_REG_BASE_ADDR__SHIFT = 0 # macro
A6XX_CP_PROTECT_REG_MASK_LEN__MASK = 0x7ffc0000 # macro
A6XX_CP_PROTECT_REG_MASK_LEN__SHIFT = 18 # macro
A6XX_CP_PROTECT_REG_READ = 0x80000000 # macro
REG_A6XX_CP_CONTEXT_SWITCH_CNTL = 0x000008a0 # macro
REG_A6XX_CP_CONTEXT_SWITCH_SMMU_INFO = 0x000008a1 # macro
REG_A6XX_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR = 0x000008a3 # macro
REG_A6XX_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR = 0x000008a5 # macro
REG_A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR = 0x000008a7 # macro
REG_A7XX_CP_CONTEXT_SWITCH_LEVEL_STATUS = 0x000008ab # macro
# def REG_A6XX_CP_PERFCTR_CP_SEL(i0): # macro
# return (0x000008d0+0x1*i0)
# def REG_A7XX_CP_BV_PERFCTR_CP_SEL(i0): # macro
# return (0x000008e0+0x1*i0)
REG_A6XX_CP_CRASH_SCRIPT_BASE = 0x00000900 # macro
REG_A6XX_CP_CRASH_DUMP_CNTL = 0x00000902 # macro
REG_A6XX_CP_CRASH_DUMP_STATUS = 0x00000903 # macro
REG_A6XX_CP_SQE_STAT_ADDR = 0x00000908 # macro
REG_A6XX_CP_SQE_STAT_DATA = 0x00000909 # macro
REG_A6XX_CP_DRAW_STATE_ADDR = 0x0000090a # macro
REG_A6XX_CP_DRAW_STATE_DATA = 0x0000090b # macro
REG_A6XX_CP_ROQ_DBG_ADDR = 0x0000090c # macro
REG_A6XX_CP_ROQ_DBG_DATA = 0x0000090d # macro
REG_A6XX_CP_MEM_POOL_DBG_ADDR = 0x0000090e # macro
REG_A6XX_CP_MEM_POOL_DBG_DATA = 0x0000090f # macro
REG_A6XX_CP_SQE_UCODE_DBG_ADDR = 0x00000910 # macro
REG_A6XX_CP_SQE_UCODE_DBG_DATA = 0x00000911 # macro
REG_A6XX_CP_IB1_BASE = 0x00000928 # macro
REG_A6XX_CP_IB1_REM_SIZE = 0x0000092a # macro
REG_A6XX_CP_IB2_BASE = 0x0000092b # macro
REG_A6XX_CP_IB2_REM_SIZE = 0x0000092d # macro
REG_A6XX_CP_SDS_BASE = 0x0000092e # macro
REG_A6XX_CP_SDS_REM_SIZE = 0x00000930 # macro
REG_A6XX_CP_MRB_BASE = 0x00000931 # macro
REG_A6XX_CP_MRB_REM_SIZE = 0x00000933 # macro
REG_A6XX_CP_VSD_BASE = 0x00000934 # macro
REG_A6XX_CP_ROQ_RB_STAT = 0x00000939 # macro
A6XX_CP_ROQ_RB_STAT_RPTR__MASK = 0x000003ff # macro
A6XX_CP_ROQ_RB_STAT_RPTR__SHIFT = 0 # macro
A6XX_CP_ROQ_RB_STAT_WPTR__MASK = 0x03ff0000 # macro
A6XX_CP_ROQ_RB_STAT_WPTR__SHIFT = 16 # macro
REG_A6XX_CP_ROQ_IB1_STAT = 0x0000093a # macro
A6XX_CP_ROQ_IB1_STAT_RPTR__MASK = 0x000003ff # macro
A6XX_CP_ROQ_IB1_STAT_RPTR__SHIFT = 0 # macro
A6XX_CP_ROQ_IB1_STAT_WPTR__MASK = 0x03ff0000 # macro
A6XX_CP_ROQ_IB1_STAT_WPTR__SHIFT = 16 # macro
REG_A6XX_CP_ROQ_IB2_STAT = 0x0000093b # macro
A6XX_CP_ROQ_IB2_STAT_RPTR__MASK = 0x000003ff # macro
A6XX_CP_ROQ_IB2_STAT_RPTR__SHIFT = 0 # macro
A6XX_CP_ROQ_IB2_STAT_WPTR__MASK = 0x03ff0000 # macro
A6XX_CP_ROQ_IB2_STAT_WPTR__SHIFT = 16 # macro
REG_A6XX_CP_ROQ_SDS_STAT = 0x0000093c # macro
A6XX_CP_ROQ_SDS_STAT_RPTR__MASK = 0x000003ff # macro
A6XX_CP_ROQ_SDS_STAT_RPTR__SHIFT = 0 # macro
A6XX_CP_ROQ_SDS_STAT_WPTR__MASK = 0x03ff0000 # macro
A6XX_CP_ROQ_SDS_STAT_WPTR__SHIFT = 16 # macro
REG_A6XX_CP_ROQ_MRB_STAT = 0x0000093d # macro
A6XX_CP_ROQ_MRB_STAT_RPTR__MASK = 0x000003ff # macro
A6XX_CP_ROQ_MRB_STAT_RPTR__SHIFT = 0 # macro
A6XX_CP_ROQ_MRB_STAT_WPTR__MASK = 0x03ff0000 # macro
A6XX_CP_ROQ_MRB_STAT_WPTR__SHIFT = 16 # macro
REG_A6XX_CP_ROQ_VSD_STAT = 0x0000093e # macro
A6XX_CP_ROQ_VSD_STAT_RPTR__MASK = 0x000003ff # macro
A6XX_CP_ROQ_VSD_STAT_RPTR__SHIFT = 0 # macro
A6XX_CP_ROQ_VSD_STAT_WPTR__MASK = 0x03ff0000 # macro
A6XX_CP_ROQ_VSD_STAT_WPTR__SHIFT = 16 # macro
REG_A6XX_CP_IB1_DWORDS = 0x00000943 # macro
REG_A6XX_CP_IB2_DWORDS = 0x00000944 # macro
REG_A6XX_CP_SDS_DWORDS = 0x00000945 # macro
REG_A6XX_CP_MRB_DWORDS = 0x00000946 # macro
REG_A6XX_CP_VSD_DWORDS = 0x00000947 # macro
REG_A6XX_CP_ROQ_AVAIL_RB = 0x00000948 # macro
A6XX_CP_ROQ_AVAIL_RB_REM__MASK = 0xffff0000 # macro
A6XX_CP_ROQ_AVAIL_RB_REM__SHIFT = 16 # macro
REG_A6XX_CP_ROQ_AVAIL_IB1 = 0x00000949 # macro
A6XX_CP_ROQ_AVAIL_IB1_REM__MASK = 0xffff0000 # macro
A6XX_CP_ROQ_AVAIL_IB1_REM__SHIFT = 16 # macro
REG_A6XX_CP_ROQ_AVAIL_IB2 = 0x0000094a # macro
A6XX_CP_ROQ_AVAIL_IB2_REM__MASK = 0xffff0000 # macro
A6XX_CP_ROQ_AVAIL_IB2_REM__SHIFT = 16 # macro
REG_A6XX_CP_ROQ_AVAIL_SDS = 0x0000094b # macro
A6XX_CP_ROQ_AVAIL_SDS_REM__MASK = 0xffff0000 # macro
A6XX_CP_ROQ_AVAIL_SDS_REM__SHIFT = 16 # macro
REG_A6XX_CP_ROQ_AVAIL_MRB = 0x0000094c # macro
A6XX_CP_ROQ_AVAIL_MRB_REM__MASK = 0xffff0000 # macro
A6XX_CP_ROQ_AVAIL_MRB_REM__SHIFT = 16 # macro
REG_A6XX_CP_ROQ_AVAIL_VSD = 0x0000094d # macro
A6XX_CP_ROQ_AVAIL_VSD_REM__MASK = 0xffff0000 # macro
A6XX_CP_ROQ_AVAIL_VSD_REM__SHIFT = 16 # macro
REG_A6XX_CP_ALWAYS_ON_COUNTER = 0x00000980 # macro
REG_A6XX_CP_AHB_CNTL = 0x0000098d # macro
REG_A6XX_CP_APERTURE_CNTL_HOST = 0x00000a00 # macro
REG_A7XX_CP_APERTURE_CNTL_HOST = 0x00000a00 # macro
A7XX_CP_APERTURE_CNTL_HOST_PIPE__MASK = 0x00003000 # macro
A7XX_CP_APERTURE_CNTL_HOST_PIPE__SHIFT = 12 # macro
A7XX_CP_APERTURE_CNTL_HOST_CLUSTER__MASK = 0x00000700 # macro
A7XX_CP_APERTURE_CNTL_HOST_CLUSTER__SHIFT = 8 # macro
A7XX_CP_APERTURE_CNTL_HOST_CONTEXT__MASK = 0x00000030 # macro
A7XX_CP_APERTURE_CNTL_HOST_CONTEXT__SHIFT = 4 # macro
REG_A6XX_CP_APERTURE_CNTL_CD = 0x00000a03 # macro
REG_A7XX_CP_APERTURE_CNTL_CD = 0x00000a03 # macro
A7XX_CP_APERTURE_CNTL_CD_PIPE__MASK = 0x00003000 # macro
A7XX_CP_APERTURE_CNTL_CD_PIPE__SHIFT = 12 # macro
A7XX_CP_APERTURE_CNTL_CD_CLUSTER__MASK = 0x00000700 # macro
A7XX_CP_APERTURE_CNTL_CD_CLUSTER__SHIFT = 8 # macro
A7XX_CP_APERTURE_CNTL_CD_CONTEXT__MASK = 0x00000030 # macro
A7XX_CP_APERTURE_CNTL_CD_CONTEXT__SHIFT = 4 # macro
REG_A7XX_CP_BV_PROTECT_STATUS = 0x00000a61 # macro
REG_A7XX_CP_BV_HW_FAULT = 0x00000a64 # macro
REG_A7XX_CP_BV_DRAW_STATE_ADDR = 0x00000a81 # macro
REG_A7XX_CP_BV_DRAW_STATE_DATA = 0x00000a82 # macro
REG_A7XX_CP_BV_ROQ_DBG_ADDR = 0x00000a83 # macro
REG_A7XX_CP_BV_ROQ_DBG_DATA = 0x00000a84 # macro
REG_A7XX_CP_BV_SQE_UCODE_DBG_ADDR = 0x00000a85 # macro
REG_A7XX_CP_BV_SQE_UCODE_DBG_DATA = 0x00000a86 # macro
REG_A7XX_CP_BV_SQE_STAT_ADDR = 0x00000a87 # macro
REG_A7XX_CP_BV_SQE_STAT_DATA = 0x00000a88 # macro
REG_A7XX_CP_BV_MEM_POOL_DBG_ADDR = 0x00000a96 # macro
REG_A7XX_CP_BV_MEM_POOL_DBG_DATA = 0x00000a97 # macro
REG_A7XX_CP_BV_RB_RPTR_ADDR = 0x00000a98 # macro
REG_A7XX_CP_RESOURCE_TBL_DBG_ADDR = 0x00000a9a # macro
REG_A7XX_CP_RESOURCE_TBL_DBG_DATA = 0x00000a9b # macro
REG_A7XX_CP_BV_APRIV_CNTL = 0x00000ad0 # macro
REG_A7XX_CP_BV_CHICKEN_DBG = 0x00000ada # macro
REG_A7XX_CP_LPAC_DRAW_STATE_ADDR = 0x00000b0a # macro
REG_A7XX_CP_LPAC_DRAW_STATE_DATA = 0x00000b0b # macro
REG_A7XX_CP_LPAC_ROQ_DBG_ADDR = 0x00000b0c # macro
REG_A7XX_CP_SQE_AC_UCODE_DBG_ADDR = 0x00000b27 # macro
REG_A7XX_CP_SQE_AC_UCODE_DBG_DATA = 0x00000b28 # macro
REG_A7XX_CP_SQE_AC_STAT_ADDR = 0x00000b29 # macro
REG_A7XX_CP_SQE_AC_STAT_DATA = 0x00000b2a # macro
REG_A7XX_CP_LPAC_APRIV_CNTL = 0x00000b31 # macro
REG_A6XX_CP_LPAC_PROG_FIFO_SIZE = 0x00000b34 # macro
REG_A7XX_CP_LPAC_ROQ_DBG_DATA = 0x00000b35 # macro
REG_A7XX_CP_LPAC_FIFO_DBG_DATA = 0x00000b36 # macro
REG_A7XX_CP_LPAC_FIFO_DBG_ADDR = 0x00000b40 # macro
REG_A6XX_CP_LPAC_SQE_CNTL = 0x00000b81 # macro
REG_A6XX_CP_LPAC_SQE_INSTR_BASE = 0x00000b82 # macro
REG_A7XX_CP_AQE_INSTR_BASE_0 = 0x00000b70 # macro
REG_A7XX_CP_AQE_INSTR_BASE_1 = 0x00000b72 # macro
REG_A7XX_CP_AQE_APRIV_CNTL = 0x00000b78 # macro
REG_A7XX_CP_AQE_ROQ_DBG_ADDR_0 = 0x00000ba8 # macro
REG_A7XX_CP_AQE_ROQ_DBG_ADDR_1 = 0x00000ba9 # macro
REG_A7XX_CP_AQE_ROQ_DBG_DATA_0 = 0x00000bac # macro
REG_A7XX_CP_AQE_ROQ_DBG_DATA_1 = 0x00000bad # macro
REG_A7XX_CP_AQE_UCODE_DBG_ADDR_0 = 0x00000bb0 # macro
REG_A7XX_CP_AQE_UCODE_DBG_ADDR_1 = 0x00000bb1 # macro
REG_A7XX_CP_AQE_UCODE_DBG_DATA_0 = 0x00000bb4 # macro
REG_A7XX_CP_AQE_UCODE_DBG_DATA_1 = 0x00000bb5 # macro
REG_A7XX_CP_AQE_STAT_ADDR_0 = 0x00000bb8 # macro
REG_A7XX_CP_AQE_STAT_ADDR_1 = 0x00000bb9 # macro
REG_A7XX_CP_AQE_STAT_DATA_0 = 0x00000bbc # macro
REG_A7XX_CP_AQE_STAT_DATA_1 = 0x00000bbd # macro
REG_A6XX_VSC_ADDR_MODE_CNTL = 0x00000c01 # macro
REG_A6XX_RBBM_GPR0_CNTL = 0x00000018 # macro
REG_A6XX_RBBM_INT_0_STATUS = 0x00000201 # macro
REG_A6XX_RBBM_STATUS = 0x00000210 # macro
A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB = 0x00800000 # macro
A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP = 0x00400000 # macro
A6XX_RBBM_STATUS_HLSQ_BUSY = 0x00200000 # macro
A6XX_RBBM_STATUS_VSC_BUSY = 0x00100000 # macro
A6XX_RBBM_STATUS_TPL1_BUSY = 0x00080000 # macro
A6XX_RBBM_STATUS_SP_BUSY = 0x00040000 # macro
A6XX_RBBM_STATUS_UCHE_BUSY = 0x00020000 # macro
A6XX_RBBM_STATUS_VPC_BUSY = 0x00010000 # macro
A6XX_RBBM_STATUS_VFD_BUSY = 0x00008000 # macro
A6XX_RBBM_STATUS_TESS_BUSY = 0x00004000 # macro
A6XX_RBBM_STATUS_PC_VSD_BUSY = 0x00002000 # macro
A6XX_RBBM_STATUS_PC_DCALL_BUSY = 0x00001000 # macro
A6XX_RBBM_STATUS_COM_DCOM_BUSY = 0x00000800 # macro
A6XX_RBBM_STATUS_LRZ_BUSY = 0x00000400 # macro
A6XX_RBBM_STATUS_A2D_BUSY = 0x00000200 # macro
A6XX_RBBM_STATUS_CCU_BUSY = 0x00000100 # macro
A6XX_RBBM_STATUS_RB_BUSY = 0x00000080 # macro
A6XX_RBBM_STATUS_RAS_BUSY = 0x00000040 # macro
A6XX_RBBM_STATUS_TSE_BUSY = 0x00000020 # macro
A6XX_RBBM_STATUS_VBIF_BUSY = 0x00000010 # macro
A6XX_RBBM_STATUS_GFX_DBGC_BUSY = 0x00000008 # macro
A6XX_RBBM_STATUS_CP_BUSY = 0x00000004 # macro
A6XX_RBBM_STATUS_CP_AHB_BUSY_CP_MASTER = 0x00000002 # macro
A6XX_RBBM_STATUS_CP_AHB_BUSY_CX_MASTER = 0x00000001 # macro
REG_A6XX_RBBM_STATUS1 = 0x00000211 # macro
REG_A6XX_RBBM_STATUS2 = 0x00000212 # macro
REG_A6XX_RBBM_STATUS3 = 0x00000213 # macro
A6XX_RBBM_STATUS3_SMMU_STALLED_ON_FAULT = 0x01000000 # macro
REG_A6XX_RBBM_VBIF_GX_RESET_STATUS = 0x00000215 # macro
REG_A7XX_RBBM_CLOCK_MODE_CP = 0x00000260 # macro
REG_A7XX_RBBM_CLOCK_MODE_BV_LRZ = 0x00000284 # macro
REG_A7XX_RBBM_CLOCK_MODE_BV_GRAS = 0x00000285 # macro
REG_A7XX_RBBM_CLOCK_MODE2_GRAS = 0x00000286 # macro
REG_A7XX_RBBM_CLOCK_MODE_BV_VFD = 0x00000287 # macro
REG_A7XX_RBBM_CLOCK_MODE_BV_GPC = 0x00000288 # macro
REG_A7XX_RBBM_SW_FUSE_INT_STATUS = 0x000002c0 # macro
REG_A7XX_RBBM_SW_FUSE_INT_MASK = 0x000002c1 # macro
# def REG_A6XX_RBBM_PERFCTR_CP(i0): # macro
# return (0x00000400+0x2*i0)
# def REG_A6XX_RBBM_PERFCTR_RBBM(i0): # macro
# return (0x0000041c+0x2*i0)
# def REG_A6XX_RBBM_PERFCTR_PC(i0): # macro
# return (0x00000424+0x2*i0)
# def REG_A6XX_RBBM_PERFCTR_VFD(i0): # macro
# return (0x00000434+0x2*i0)
# def REG_A6XX_RBBM_PERFCTR_HLSQ(i0): # macro
# return (0x00000444+0x2*i0)
# def REG_A6XX_RBBM_PERFCTR_VPC(i0): # macro
# return (0x00000450+0x2*i0)
# def REG_A6XX_RBBM_PERFCTR_CCU(i0): # macro
# return (0x0000045c+0x2*i0)
# def REG_A6XX_RBBM_PERFCTR_TSE(i0): # macro
# return (0x00000466+0x2*i0)
# def REG_A6XX_RBBM_PERFCTR_RAS(i0): # macro
# return (0x0000046e+0x2*i0)
# def REG_A6XX_RBBM_PERFCTR_UCHE(i0): # macro
# return (0x00000476+0x2*i0)
# def REG_A6XX_RBBM_PERFCTR_TP(i0): # macro
# return (0x0000048e+0x2*i0)
# def REG_A6XX_RBBM_PERFCTR_SP(i0): # macro
# return (0x000004a6+0x2*i0)
# def REG_A6XX_RBBM_PERFCTR_RB(i0): # macro
# return (0x000004d6+0x2*i0)
# def REG_A6XX_RBBM_PERFCTR_VSC(i0): # macro
# return (0x000004e6+0x2*i0)
# def REG_A6XX_RBBM_PERFCTR_LRZ(i0): # macro
# return (0x000004ea+0x2*i0)
# def REG_A6XX_RBBM_PERFCTR_CMP(i0): # macro
# return (0x000004f2+0x2*i0)
# def REG_A7XX_RBBM_PERFCTR_CP(i0): # macro
# return (0x00000300+0x2*i0)
# def REG_A7XX_RBBM_PERFCTR_RBBM(i0): # macro
# return (0x0000031c+0x2*i0)
# def REG_A7XX_RBBM_PERFCTR_PC(i0): # macro
# return (0x00000324+0x2*i0)
# def REG_A7XX_RBBM_PERFCTR_VFD(i0): # macro
# return (0x00000334+0x2*i0)
# def REG_A7XX_RBBM_PERFCTR_HLSQ(i0): # macro
# return (0x00000344+0x2*i0)
# def REG_A7XX_RBBM_PERFCTR_VPC(i0): # macro
# return (0x00000350+0x2*i0)
# def REG_A7XX_RBBM_PERFCTR_CCU(i0): # macro
# return (0x0000035c+0x2*i0)
# def REG_A7XX_RBBM_PERFCTR_TSE(i0): # macro
# return (0x00000366+0x2*i0)
# def REG_A7XX_RBBM_PERFCTR_RAS(i0): # macro
# return (0x0000036e+0x2*i0)
# def REG_A7XX_RBBM_PERFCTR_UCHE(i0): # macro
# return (0x00000376+0x2*i0)
# def REG_A7XX_RBBM_PERFCTR_TP(i0): # macro
# return (0x0000038e+0x2*i0)
# def REG_A7XX_RBBM_PERFCTR_SP(i0): # macro
# return (0x000003a6+0x2*i0)
# def REG_A7XX_RBBM_PERFCTR_RB(i0): # macro
# return (0x000003d6+0x2*i0)
# def REG_A7XX_RBBM_PERFCTR_VSC(i0): # macro
# return (0x000003e6+0x2*i0)
# def REG_A7XX_RBBM_PERFCTR_LRZ(i0): # macro
# return (0x000003ea+0x2*i0)
# def REG_A7XX_RBBM_PERFCTR_CMP(i0): # macro
# return (0x000003f2+0x2*i0)
# def REG_A7XX_RBBM_PERFCTR_UFC(i0): # macro
# return (0x000003fa+0x2*i0)
# def REG_A7XX_RBBM_PERFCTR2_HLSQ(i0): # macro
# return (0x00000410+0x2*i0)
# def REG_A7XX_RBBM_PERFCTR2_CP(i0): # macro
# return (0x0000041c+0x2*i0)
# def REG_A7XX_RBBM_PERFCTR2_SP(i0): # macro
# return (0x0000042a+0x2*i0)
# def REG_A7XX_RBBM_PERFCTR2_TP(i0): # macro
# return (0x00000442+0x2*i0)
# def REG_A7XX_RBBM_PERFCTR2_UFC(i0): # macro
# return (0x0000044e+0x2*i0)
# def REG_A7XX_RBBM_PERFCTR_BV_PC(i0): # macro
# return (0x00000460+0x2*i0)
# def REG_A7XX_RBBM_PERFCTR_BV_VFD(i0): # macro
# return (0x00000470+0x2*i0)
# def REG_A7XX_RBBM_PERFCTR_BV_VPC(i0): # macro
# return (0x00000480+0x2*i0)
# def REG_A7XX_RBBM_PERFCTR_BV_TSE(i0): # macro
# return (0x0000048c+0x2*i0)
# def REG_A7XX_RBBM_PERFCTR_BV_RAS(i0): # macro
# return (0x00000494+0x2*i0)
# def REG_A7XX_RBBM_PERFCTR_BV_LRZ(i0): # macro
# return (0x0000049c+0x2*i0)
REG_A6XX_RBBM_PERFCTR_CNTL = 0x00000500 # macro
REG_A6XX_RBBM_PERFCTR_LOAD_CMD0 = 0x00000501 # macro
REG_A6XX_RBBM_PERFCTR_LOAD_CMD1 = 0x00000502 # macro
REG_A6XX_RBBM_PERFCTR_LOAD_CMD2 = 0x00000503 # macro
REG_A6XX_RBBM_PERFCTR_LOAD_CMD3 = 0x00000504 # macro
REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_LO = 0x00000505 # macro
REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_HI = 0x00000506 # macro
# def REG_A6XX_RBBM_PERFCTR_RBBM_SEL(i0): # macro
# return (0x00000507+0x1*i0)
REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED = 0x0000050b # macro
REG_A6XX_RBBM_PERFCTR_SRAM_INIT_CMD = 0x0000050e # macro
REG_A6XX_RBBM_PERFCTR_SRAM_INIT_STATUS = 0x0000050f # macro
REG_A6XX_RBBM_ISDB_CNT = 0x00000533 # macro
REG_A7XX_RBBM_NC_MODE_CNTL = 0x00000534 # macro
REG_A7XX_RBBM_SNAPSHOT_STATUS = 0x00000535 # macro
REG_A6XX_RBBM_PRIMCTR_0_LO = 0x00000540 # macro
REG_A6XX_RBBM_PRIMCTR_0_HI = 0x00000541 # macro
REG_A6XX_RBBM_PRIMCTR_1_LO = 0x00000542 # macro
REG_A6XX_RBBM_PRIMCTR_1_HI = 0x00000543 # macro
REG_A6XX_RBBM_PRIMCTR_2_LO = 0x00000544 # macro
REG_A6XX_RBBM_PRIMCTR_2_HI = 0x00000545 # macro
REG_A6XX_RBBM_PRIMCTR_3_LO = 0x00000546 # macro
REG_A6XX_RBBM_PRIMCTR_3_HI = 0x00000547 # macro
REG_A6XX_RBBM_PRIMCTR_4_LO = 0x00000548 # macro
REG_A6XX_RBBM_PRIMCTR_4_HI = 0x00000549 # macro
REG_A6XX_RBBM_PRIMCTR_5_LO = 0x0000054a # macro
REG_A6XX_RBBM_PRIMCTR_5_HI = 0x0000054b # macro
REG_A6XX_RBBM_PRIMCTR_6_LO = 0x0000054c # macro
REG_A6XX_RBBM_PRIMCTR_6_HI = 0x0000054d # macro
REG_A6XX_RBBM_PRIMCTR_7_LO = 0x0000054e # macro
REG_A6XX_RBBM_PRIMCTR_7_HI = 0x0000054f # macro
REG_A6XX_RBBM_PRIMCTR_8_LO = 0x00000550 # macro
REG_A6XX_RBBM_PRIMCTR_8_HI = 0x00000551 # macro
REG_A6XX_RBBM_PRIMCTR_9_LO = 0x00000552 # macro
REG_A6XX_RBBM_PRIMCTR_9_HI = 0x00000553 # macro
REG_A6XX_RBBM_PRIMCTR_10_LO = 0x00000554 # macro
REG_A6XX_RBBM_PRIMCTR_10_HI = 0x00000555 # macro
REG_A6XX_RBBM_SECVID_TRUST_CNTL = 0x0000f400 # macro
REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE = 0x0000f800 # macro
REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE = 0x0000f802 # macro
REG_A6XX_RBBM_SECVID_TSB_CNTL = 0x0000f803 # macro
REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL = 0x0000f810 # macro
REG_A7XX_RBBM_SECVID_TSB_STATUS = 0x0000fc00 # macro
REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL = 0x00000010 # macro
REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL = 0x00000011 # macro
REG_A6XX_RBBM_GBIF_HALT = 0x00000016 # macro
REG_A6XX_RBBM_GBIF_HALT_ACK = 0x00000017 # macro
REG_A6XX_RBBM_WAIT_FOR_GPU_IDLE_CMD = 0x0000001c # macro
A6XX_RBBM_WAIT_FOR_GPU_IDLE_CMD_WAIT_GPU_IDLE = 0x00000001 # macro
REG_A7XX_RBBM_GBIF_HALT = 0x00000016 # macro
REG_A7XX_RBBM_GBIF_HALT_ACK = 0x00000017 # macro
REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL = 0x0000001f # macro
REG_A6XX_RBBM_INT_CLEAR_CMD = 0x00000037 # macro
REG_A6XX_RBBM_INT_0_MASK = 0x00000038 # macro
REG_A7XX_RBBM_INT_2_MASK = 0x0000003a # macro
REG_A6XX_RBBM_SP_HYST_CNT = 0x00000042 # macro
REG_A6XX_RBBM_SW_RESET_CMD = 0x00000043 # macro
REG_A6XX_RBBM_RAC_THRESHOLD_CNT = 0x00000044 # macro
REG_A6XX_RBBM_BLOCK_SW_RESET_CMD = 0x00000045 # macro
REG_A6XX_RBBM_BLOCK_SW_RESET_CMD2 = 0x00000046 # macro
REG_A7XX_RBBM_CLOCK_CNTL_GLOBAL = 0x000000ad # macro
REG_A6XX_RBBM_CLOCK_CNTL = 0x000000ae # macro
REG_A6XX_RBBM_CLOCK_CNTL_SP0 = 0x000000b0 # macro
REG_A6XX_RBBM_CLOCK_CNTL_SP1 = 0x000000b1 # macro
REG_A6XX_RBBM_CLOCK_CNTL_SP2 = 0x000000b2 # macro
REG_A6XX_RBBM_CLOCK_CNTL_SP3 = 0x000000b3 # macro
REG_A6XX_RBBM_CLOCK_CNTL2_SP0 = 0x000000b4 # macro
REG_A6XX_RBBM_CLOCK_CNTL2_SP1 = 0x000000b5 # macro
REG_A6XX_RBBM_CLOCK_CNTL2_SP2 = 0x000000b6 # macro
REG_A6XX_RBBM_CLOCK_CNTL2_SP3 = 0x000000b7 # macro
REG_A6XX_RBBM_CLOCK_DELAY_SP0 = 0x000000b8 # macro
REG_A6XX_RBBM_CLOCK_DELAY_SP1 = 0x000000b9 # macro
REG_A6XX_RBBM_CLOCK_DELAY_SP2 = 0x000000ba # macro
REG_A6XX_RBBM_CLOCK_DELAY_SP3 = 0x000000bb # macro
REG_A6XX_RBBM_CLOCK_HYST_SP0 = 0x000000bc # macro
REG_A6XX_RBBM_CLOCK_HYST_SP1 = 0x000000bd # macro
REG_A6XX_RBBM_CLOCK_HYST_SP2 = 0x000000be # macro
REG_A6XX_RBBM_CLOCK_HYST_SP3 = 0x000000bf # macro
REG_A6XX_RBBM_CLOCK_CNTL_TP0 = 0x000000c0 # macro
REG_A6XX_RBBM_CLOCK_CNTL_TP1 = 0x000000c1 # macro
REG_A6XX_RBBM_CLOCK_CNTL_TP2 = 0x000000c2 # macro
REG_A6XX_RBBM_CLOCK_CNTL_TP3 = 0x000000c3 # macro
REG_A6XX_RBBM_CLOCK_CNTL2_TP0 = 0x000000c4 # macro
REG_A6XX_RBBM_CLOCK_CNTL2_TP1 = 0x000000c5 # macro
REG_A6XX_RBBM_CLOCK_CNTL2_TP2 = 0x000000c6 # macro
REG_A6XX_RBBM_CLOCK_CNTL2_TP3 = 0x000000c7 # macro
REG_A6XX_RBBM_CLOCK_CNTL3_TP0 = 0x000000c8 # macro
REG_A6XX_RBBM_CLOCK_CNTL3_TP1 = 0x000000c9 # macro
REG_A6XX_RBBM_CLOCK_CNTL3_TP2 = 0x000000ca # macro
REG_A6XX_RBBM_CLOCK_CNTL3_TP3 = 0x000000cb # macro
REG_A6XX_RBBM_CLOCK_CNTL4_TP0 = 0x000000cc # macro
REG_A6XX_RBBM_CLOCK_CNTL4_TP1 = 0x000000cd # macro
REG_A6XX_RBBM_CLOCK_CNTL4_TP2 = 0x000000ce # macro
REG_A6XX_RBBM_CLOCK_CNTL4_TP3 = 0x000000cf # macro
REG_A6XX_RBBM_CLOCK_DELAY_TP0 = 0x000000d0 # macro
REG_A6XX_RBBM_CLOCK_DELAY_TP1 = 0x000000d1 # macro
REG_A6XX_RBBM_CLOCK_DELAY_TP2 = 0x000000d2 # macro
REG_A6XX_RBBM_CLOCK_DELAY_TP3 = 0x000000d3 # macro
REG_A6XX_RBBM_CLOCK_DELAY2_TP0 = 0x000000d4 # macro
REG_A6XX_RBBM_CLOCK_DELAY2_TP1 = 0x000000d5 # macro
REG_A6XX_RBBM_CLOCK_DELAY2_TP2 = 0x000000d6 # macro
REG_A6XX_RBBM_CLOCK_DELAY2_TP3 = 0x000000d7 # macro
REG_A6XX_RBBM_CLOCK_DELAY3_TP0 = 0x000000d8 # macro
REG_A6XX_RBBM_CLOCK_DELAY3_TP1 = 0x000000d9 # macro
REG_A6XX_RBBM_CLOCK_DELAY3_TP2 = 0x000000da # macro
REG_A6XX_RBBM_CLOCK_DELAY3_TP3 = 0x000000db # macro
REG_A6XX_RBBM_CLOCK_DELAY4_TP0 = 0x000000dc # macro
REG_A6XX_RBBM_CLOCK_DELAY4_TP1 = 0x000000dd # macro
REG_A6XX_RBBM_CLOCK_DELAY4_TP2 = 0x000000de # macro
REG_A6XX_RBBM_CLOCK_DELAY4_TP3 = 0x000000df # macro
REG_A6XX_RBBM_CLOCK_HYST_TP0 = 0x000000e0 # macro
REG_A6XX_RBBM_CLOCK_HYST_TP1 = 0x000000e1 # macro
REG_A6XX_RBBM_CLOCK_HYST_TP2 = 0x000000e2 # macro
REG_A6XX_RBBM_CLOCK_HYST_TP3 = 0x000000e3 # macro
REG_A6XX_RBBM_CLOCK_HYST2_TP0 = 0x000000e4 # macro
REG_A6XX_RBBM_CLOCK_HYST2_TP1 = 0x000000e5 # macro
REG_A6XX_RBBM_CLOCK_HYST2_TP2 = 0x000000e6 # macro
REG_A6XX_RBBM_CLOCK_HYST2_TP3 = 0x000000e7 # macro
REG_A6XX_RBBM_CLOCK_HYST3_TP0 = 0x000000e8 # macro
REG_A6XX_RBBM_CLOCK_HYST3_TP1 = 0x000000e9 # macro
REG_A6XX_RBBM_CLOCK_HYST3_TP2 = 0x000000ea # macro
REG_A6XX_RBBM_CLOCK_HYST3_TP3 = 0x000000eb # macro
REG_A6XX_RBBM_CLOCK_HYST4_TP0 = 0x000000ec # macro
REG_A6XX_RBBM_CLOCK_HYST4_TP1 = 0x000000ed # macro
REG_A6XX_RBBM_CLOCK_HYST4_TP2 = 0x000000ee # macro
REG_A6XX_RBBM_CLOCK_HYST4_TP3 = 0x000000ef # macro
REG_A6XX_RBBM_CLOCK_CNTL_RB0 = 0x000000f0 # macro
REG_A6XX_RBBM_CLOCK_CNTL_RB1 = 0x000000f1 # macro
REG_A6XX_RBBM_CLOCK_CNTL_RB2 = 0x000000f2 # macro
REG_A6XX_RBBM_CLOCK_CNTL_RB3 = 0x000000f3 # macro
REG_A6XX_RBBM_CLOCK_CNTL2_RB0 = 0x000000f4 # macro
REG_A6XX_RBBM_CLOCK_CNTL2_RB1 = 0x000000f5 # macro
REG_A6XX_RBBM_CLOCK_CNTL2_RB2 = 0x000000f6 # macro
REG_A6XX_RBBM_CLOCK_CNTL2_RB3 = 0x000000f7 # macro
REG_A6XX_RBBM_CLOCK_CNTL_CCU0 = 0x000000f8 # macro
REG_A6XX_RBBM_CLOCK_CNTL_CCU1 = 0x000000f9 # macro
REG_A6XX_RBBM_CLOCK_CNTL_CCU2 = 0x000000fa # macro
REG_A6XX_RBBM_CLOCK_CNTL_CCU3 = 0x000000fb # macro
REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0 = 0x00000100 # macro
REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1 = 0x00000101 # macro
REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2 = 0x00000102 # macro
REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3 = 0x00000103 # macro
REG_A6XX_RBBM_CLOCK_CNTL_RAC = 0x00000104 # macro
REG_A6XX_RBBM_CLOCK_CNTL2_RAC = 0x00000105 # macro
REG_A6XX_RBBM_CLOCK_DELAY_RAC = 0x00000106 # macro
REG_A6XX_RBBM_CLOCK_HYST_RAC = 0x00000107 # macro
REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM = 0x00000108 # macro
REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM = 0x00000109 # macro
REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM = 0x0000010a # macro
REG_A6XX_RBBM_CLOCK_CNTL_UCHE = 0x0000010b # macro
REG_A6XX_RBBM_CLOCK_CNTL2_UCHE = 0x0000010c # macro
REG_A6XX_RBBM_CLOCK_CNTL3_UCHE = 0x0000010d # macro
REG_A6XX_RBBM_CLOCK_CNTL4_UCHE = 0x0000010e # macro
REG_A6XX_RBBM_CLOCK_DELAY_UCHE = 0x0000010f # macro
REG_A6XX_RBBM_CLOCK_HYST_UCHE = 0x00000110 # macro
REG_A6XX_RBBM_CLOCK_MODE_VFD = 0x00000111 # macro
REG_A6XX_RBBM_CLOCK_DELAY_VFD = 0x00000112 # macro
REG_A6XX_RBBM_CLOCK_HYST_VFD = 0x00000113 # macro
REG_A6XX_RBBM_CLOCK_MODE_GPC = 0x00000114 # macro
REG_A6XX_RBBM_CLOCK_DELAY_GPC = 0x00000115 # macro
REG_A6XX_RBBM_CLOCK_HYST_GPC = 0x00000116 # macro
REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2 = 0x00000117 # macro
REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX = 0x00000118 # macro
REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX = 0x00000119 # macro
REG_A6XX_RBBM_CLOCK_HYST_GMU_GX = 0x0000011a # macro
REG_A6XX_RBBM_CLOCK_MODE_HLSQ = 0x0000011b # macro
REG_A6XX_RBBM_CLOCK_DELAY_HLSQ = 0x0000011c # macro
REG_A6XX_RBBM_CLOCK_HYST_HLSQ = 0x0000011d # macro
REG_A7XX_RBBM_CGC_GLOBAL_LOAD_CMD = 0x0000011e # macro
REG_A7XX_RBBM_CGC_P2S_TRIG_CMD = 0x0000011f # macro
REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE = 0x00000120 # macro
REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE = 0x00000121 # macro
REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE = 0x00000122 # macro
REG_A7XX_RBBM_CGC_P2S_STATUS = 0x00000122 # macro
A7XX_RBBM_CGC_P2S_STATUS_TXDONE = 0x00000001 # macro
REG_A6XX_RBBM_CLOCK_CNTL_FCHE = 0x00000123 # macro
REG_A6XX_RBBM_CLOCK_DELAY_FCHE = 0x00000124 # macro
REG_A6XX_RBBM_CLOCK_HYST_FCHE = 0x00000125 # macro
REG_A6XX_RBBM_CLOCK_CNTL_MHUB = 0x00000126 # macro
REG_A6XX_RBBM_CLOCK_DELAY_MHUB = 0x00000127 # macro
REG_A6XX_RBBM_CLOCK_HYST_MHUB = 0x00000128 # macro
REG_A6XX_RBBM_CLOCK_DELAY_GLC = 0x00000129 # macro
REG_A6XX_RBBM_CLOCK_HYST_GLC = 0x0000012a # macro
REG_A6XX_RBBM_CLOCK_CNTL_GLC = 0x0000012b # macro
REG_A7XX_RBBM_CLOCK_HYST2_VFD = 0x0000012f # macro
REG_A6XX_RBBM_LPAC_GBIF_CLIENT_QOS_CNTL = 0x000005ff # macro
REG_A6XX_DBGC_CFG_DBGBUS_SEL_A = 0x00000600 # macro
REG_A6XX_DBGC_CFG_DBGBUS_SEL_B = 0x00000601 # macro
REG_A6XX_DBGC_CFG_DBGBUS_SEL_C = 0x00000602 # macro
REG_A6XX_DBGC_CFG_DBGBUS_SEL_D = 0x00000603 # macro
A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__MASK = 0x000000ff # macro
A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__SHIFT = 0 # macro
A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__MASK = 0x0000ff00 # macro
A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__SHIFT = 8 # macro
REG_A6XX_DBGC_CFG_DBGBUS_CNTLT = 0x00000604 # macro
A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK = 0x0000003f # macro
A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT = 0 # macro
A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK = 0x00007000 # macro
A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT = 12 # macro
A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK = 0xf0000000 # macro
A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT = 28 # macro
REG_A6XX_DBGC_CFG_DBGBUS_CNTLM = 0x00000605 # macro
A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK = 0x0f000000 # macro
A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT = 24 # macro
REG_A6XX_DBGC_CFG_DBGBUS_IVTL_0 = 0x00000608 # macro
REG_A6XX_DBGC_CFG_DBGBUS_IVTL_1 = 0x00000609 # macro
REG_A6XX_DBGC_CFG_DBGBUS_IVTL_2 = 0x0000060a # macro
REG_A6XX_DBGC_CFG_DBGBUS_IVTL_3 = 0x0000060b # macro
REG_A6XX_DBGC_CFG_DBGBUS_MASKL_0 = 0x0000060c # macro
REG_A6XX_DBGC_CFG_DBGBUS_MASKL_1 = 0x0000060d # macro
REG_A6XX_DBGC_CFG_DBGBUS_MASKL_2 = 0x0000060e # macro
REG_A6XX_DBGC_CFG_DBGBUS_MASKL_3 = 0x0000060f # macro
REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_0 = 0x00000610 # macro
A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK = 0x0000000f # macro
A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT = 0 # macro
A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK = 0x000000f0 # macro
A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT = 4 # macro
A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK = 0x00000f00 # macro
A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT = 8 # macro
A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK = 0x0000f000 # macro
A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT = 12 # macro
A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK = 0x000f0000 # macro
A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT = 16 # macro
A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK = 0x00f00000 # macro
A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT = 20 # macro
A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK = 0x0f000000 # macro
A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT = 24 # macro
A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK = 0xf0000000 # macro
A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT = 28 # macro
REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_1 = 0x00000611 # macro
A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK = 0x0000000f # macro
A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT = 0 # macro
A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK = 0x000000f0 # macro
A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT = 4 # macro
A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK = 0x00000f00 # macro
A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT = 8 # macro
A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK = 0x0000f000 # macro
A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT = 12 # macro
A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK = 0x000f0000 # macro
A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT = 16 # macro
A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK = 0x00f00000 # macro
A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT = 20 # macro
A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK = 0x0f000000 # macro
A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT = 24 # macro
A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK = 0xf0000000 # macro
A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT = 28 # macro
REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF1 = 0x0000062f # macro
REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF2 = 0x00000630 # macro
# def REG_A6XX_VSC_PERFCTR_VSC_SEL(i0): # macro
# return (0x00000cd8+0x1*i0)
REG_A7XX_VSC_UNKNOWN_0CD8 = 0x00000cd8 # macro
A7XX_VSC_UNKNOWN_0CD8_BINNING = 0x00000001 # macro
REG_A6XX_HLSQ_DBG_AHB_READ_APERTURE = 0x0000c800 # macro
REG_A6XX_HLSQ_DBG_READ_SEL = 0x0000d000 # macro
REG_A6XX_UCHE_ADDR_MODE_CNTL = 0x00000e00 # macro
REG_A6XX_UCHE_MODE_CNTL = 0x00000e01 # macro
REG_A6XX_UCHE_WRITE_RANGE_MAX = 0x00000e05 # macro
REG_A6XX_UCHE_WRITE_THRU_BASE = 0x00000e07 # macro
REG_A6XX_UCHE_TRAP_BASE = 0x00000e09 # macro
REG_A6XX_UCHE_GMEM_RANGE_MIN = 0x00000e0b # macro
REG_A6XX_UCHE_GMEM_RANGE_MAX = 0x00000e0d # macro
REG_A6XX_UCHE_CACHE_WAYS = 0x00000e17 # macro
REG_A6XX_UCHE_FILTER_CNTL = 0x00000e18 # macro
REG_A6XX_UCHE_CLIENT_PF = 0x00000e19 # macro
A6XX_UCHE_CLIENT_PF_PERFSEL__MASK = 0x000000ff # macro
A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT = 0 # macro
# def REG_A6XX_UCHE_PERFCTR_UCHE_SEL(i0): # macro
# return (0x00000e1c+0x1*i0)
REG_A6XX_UCHE_GBIF_GX_CONFIG = 0x00000e3a # macro
REG_A6XX_UCHE_CMDQ_CONFIG = 0x00000e3c # macro
REG_A6XX_VBIF_VERSION = 0x00003000 # macro
REG_A6XX_VBIF_CLKON = 0x00003001 # macro
A6XX_VBIF_CLKON_FORCE_ON_TESTBUS = 0x00000002 # macro
REG_A6XX_VBIF_GATE_OFF_WRREQ_EN = 0x0000302a # macro
REG_A6XX_VBIF_XIN_HALT_CTRL0 = 0x00003080 # macro
REG_A6XX_VBIF_XIN_HALT_CTRL1 = 0x00003081 # macro
REG_A6XX_VBIF_TEST_BUS_OUT_CTRL = 0x00003084 # macro
REG_A6XX_VBIF_TEST_BUS1_CTRL0 = 0x00003085 # macro
REG_A6XX_VBIF_TEST_BUS1_CTRL1 = 0x00003086 # macro
A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__MASK = 0x0000000f # macro
A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__SHIFT = 0 # macro
REG_A6XX_VBIF_TEST_BUS2_CTRL0 = 0x00003087 # macro
REG_A6XX_VBIF_TEST_BUS2_CTRL1 = 0x00003088 # macro
A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__MASK = 0x000001ff # macro
A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__SHIFT = 0 # macro
REG_A6XX_VBIF_TEST_BUS_OUT = 0x0000308c # macro
REG_A6XX_VBIF_PERF_CNT_SEL0 = 0x000030d0 # macro
REG_A6XX_VBIF_PERF_CNT_SEL1 = 0x000030d1 # macro
REG_A6XX_VBIF_PERF_CNT_SEL2 = 0x000030d2 # macro
REG_A6XX_VBIF_PERF_CNT_SEL3 = 0x000030d3 # macro
REG_A6XX_VBIF_PERF_CNT_LOW0 = 0x000030d8 # macro
REG_A6XX_VBIF_PERF_CNT_LOW1 = 0x000030d9 # macro
REG_A6XX_VBIF_PERF_CNT_LOW2 = 0x000030da # macro
REG_A6XX_VBIF_PERF_CNT_LOW3 = 0x000030db # macro
REG_A6XX_VBIF_PERF_CNT_HIGH0 = 0x000030e0 # macro
REG_A6XX_VBIF_PERF_CNT_HIGH1 = 0x000030e1 # macro
REG_A6XX_VBIF_PERF_CNT_HIGH2 = 0x000030e2 # macro
REG_A6XX_VBIF_PERF_CNT_HIGH3 = 0x000030e3 # macro
REG_A6XX_VBIF_PERF_PWR_CNT_EN0 = 0x00003100 # macro
REG_A6XX_VBIF_PERF_PWR_CNT_EN1 = 0x00003101 # macro
REG_A6XX_VBIF_PERF_PWR_CNT_EN2 = 0x00003102 # macro
REG_A6XX_VBIF_PERF_PWR_CNT_LOW0 = 0x00003110 # macro
REG_A6XX_VBIF_PERF_PWR_CNT_LOW1 = 0x00003111 # macro
REG_A6XX_VBIF_PERF_PWR_CNT_LOW2 = 0x00003112 # macro
REG_A6XX_VBIF_PERF_PWR_CNT_HIGH0 = 0x00003118 # macro
REG_A6XX_VBIF_PERF_PWR_CNT_HIGH1 = 0x00003119 # macro
REG_A6XX_VBIF_PERF_PWR_CNT_HIGH2 = 0x0000311a # macro
REG_A6XX_GBIF_SCACHE_CNTL0 = 0x00003c01 # macro
REG_A6XX_GBIF_SCACHE_CNTL1 = 0x00003c02 # macro
REG_A6XX_GBIF_QSB_SIDE0 = 0x00003c03 # macro
REG_A6XX_GBIF_QSB_SIDE1 = 0x00003c04 # macro
REG_A6XX_GBIF_QSB_SIDE2 = 0x00003c05 # macro
REG_A6XX_GBIF_QSB_SIDE3 = 0x00003c06 # macro
REG_A6XX_GBIF_HALT = 0x00003c45 # macro
REG_A6XX_GBIF_HALT_ACK = 0x00003c46 # macro
REG_A6XX_GBIF_PERF_PWR_CNT_EN = 0x00003cc0 # macro
REG_A6XX_GBIF_PERF_PWR_CNT_CLR = 0x00003cc1 # macro
REG_A6XX_GBIF_PERF_CNT_SEL = 0x00003cc2 # macro
REG_A6XX_GBIF_PERF_PWR_CNT_SEL = 0x00003cc3 # macro
REG_A6XX_GBIF_PERF_CNT_LOW0 = 0x00003cc4 # macro
REG_A6XX_GBIF_PERF_CNT_LOW1 = 0x00003cc5 # macro
REG_A6XX_GBIF_PERF_CNT_LOW2 = 0x00003cc6 # macro
REG_A6XX_GBIF_PERF_CNT_LOW3 = 0x00003cc7 # macro
REG_A6XX_GBIF_PERF_CNT_HIGH0 = 0x00003cc8 # macro
REG_A6XX_GBIF_PERF_CNT_HIGH1 = 0x00003cc9 # macro
REG_A6XX_GBIF_PERF_CNT_HIGH2 = 0x00003cca # macro
REG_A6XX_GBIF_PERF_CNT_HIGH3 = 0x00003ccb # macro
REG_A6XX_GBIF_PWR_CNT_LOW0 = 0x00003ccc # macro
REG_A6XX_GBIF_PWR_CNT_LOW1 = 0x00003ccd # macro
REG_A6XX_GBIF_PWR_CNT_LOW2 = 0x00003cce # macro
REG_A6XX_GBIF_PWR_CNT_HIGH0 = 0x00003ccf # macro
REG_A6XX_GBIF_PWR_CNT_HIGH1 = 0x00003cd0 # macro
REG_A6XX_GBIF_PWR_CNT_HIGH2 = 0x00003cd1 # macro
REG_A6XX_VSC_DBG_ECO_CNTL = 0x00000c00 # macro
REG_A6XX_VSC_BIN_SIZE = 0x00000c02 # macro
A6XX_VSC_BIN_SIZE_WIDTH__MASK = 0x000000ff # macro
A6XX_VSC_BIN_SIZE_WIDTH__SHIFT = 0 # macro
A6XX_VSC_BIN_SIZE_HEIGHT__MASK = 0x0001ff00 # macro
A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT = 8 # macro
REG_A6XX_VSC_DRAW_STRM_SIZE_ADDRESS = 0x00000c03 # macro
REG_A6XX_VSC_BIN_COUNT = 0x00000c06 # macro
A6XX_VSC_BIN_COUNT_NX__MASK = 0x000007fe # macro
A6XX_VSC_BIN_COUNT_NX__SHIFT = 1 # macro
A6XX_VSC_BIN_COUNT_NY__MASK = 0x001ff800 # macro
A6XX_VSC_BIN_COUNT_NY__SHIFT = 11 # macro
# def REG_A6XX_VSC_PIPE_CONFIG(i0): # macro
# return (0x00000c10+0x1*i0)
A6XX_VSC_PIPE_CONFIG_REG_X__MASK = 0x000003ff # macro
A6XX_VSC_PIPE_CONFIG_REG_X__SHIFT = 0 # macro
A6XX_VSC_PIPE_CONFIG_REG_Y__MASK = 0x000ffc00 # macro
A6XX_VSC_PIPE_CONFIG_REG_Y__SHIFT = 10 # macro
A6XX_VSC_PIPE_CONFIG_REG_W__MASK = 0x03f00000 # macro
A6XX_VSC_PIPE_CONFIG_REG_W__SHIFT = 20 # macro
A6XX_VSC_PIPE_CONFIG_REG_H__MASK = 0xfc000000 # macro
A6XX_VSC_PIPE_CONFIG_REG_H__SHIFT = 26 # macro
REG_A6XX_VSC_PRIM_STRM_ADDRESS = 0x00000c30 # macro
REG_A6XX_VSC_PRIM_STRM_PITCH = 0x00000c32 # macro
REG_A6XX_VSC_PRIM_STRM_LIMIT = 0x00000c33 # macro
REG_A6XX_VSC_DRAW_STRM_ADDRESS = 0x00000c34 # macro
REG_A6XX_VSC_DRAW_STRM_PITCH = 0x00000c36 # macro
REG_A6XX_VSC_DRAW_STRM_LIMIT = 0x00000c37 # macro
# def REG_A6XX_VSC_STATE(i0): # macro
# return (0x00000c38+0x1*i0)
# def REG_A6XX_VSC_PRIM_STRM_SIZE(i0): # macro
# return (0x00000c58+0x1*i0)
# def REG_A6XX_VSC_DRAW_STRM_SIZE(i0): # macro
# return (0x00000c78+0x1*i0)
REG_A7XX_VSC_UNKNOWN_0D08 = 0x00000d08 # macro
REG_A7XX_UCHE_UNKNOWN_0E10 = 0x00000e10 # macro
REG_A7XX_UCHE_UNKNOWN_0E11 = 0x00000e11 # macro
REG_A6XX_UCHE_UNKNOWN_0E12 = 0x00000e12 # macro
REG_A6XX_GRAS_CL_CNTL = 0x00008000 # macro
A6XX_GRAS_CL_CNTL_CLIP_DISABLE = 0x00000001 # macro
A6XX_GRAS_CL_CNTL_ZNEAR_CLIP_DISABLE = 0x00000002 # macro
A6XX_GRAS_CL_CNTL_ZFAR_CLIP_DISABLE = 0x00000004 # macro
A6XX_GRAS_CL_CNTL_Z_CLAMP_ENABLE = 0x00000020 # macro
A6XX_GRAS_CL_CNTL_ZERO_GB_SCALE_Z = 0x00000040 # macro
A6XX_GRAS_CL_CNTL_VP_CLIP_CODE_IGNORE = 0x00000080 # macro
A6XX_GRAS_CL_CNTL_VP_XFORM_DISABLE = 0x00000100 # macro
A6XX_GRAS_CL_CNTL_PERSP_DIVISION_DISABLE = 0x00000200 # macro
REG_A6XX_GRAS_VS_CL_CNTL = 0x00008001 # macro
A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__MASK = 0x000000ff # macro
A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__SHIFT = 0 # macro
A6XX_GRAS_VS_CL_CNTL_CULL_MASK__MASK = 0x0000ff00 # macro
A6XX_GRAS_VS_CL_CNTL_CULL_MASK__SHIFT = 8 # macro
REG_A6XX_GRAS_DS_CL_CNTL = 0x00008002 # macro
A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__MASK = 0x000000ff # macro
A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__SHIFT = 0 # macro
A6XX_GRAS_DS_CL_CNTL_CULL_MASK__MASK = 0x0000ff00 # macro
A6XX_GRAS_DS_CL_CNTL_CULL_MASK__SHIFT = 8 # macro
REG_A6XX_GRAS_GS_CL_CNTL = 0x00008003 # macro
A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__MASK = 0x000000ff # macro
A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__SHIFT = 0 # macro
A6XX_GRAS_GS_CL_CNTL_CULL_MASK__MASK = 0x0000ff00 # macro
A6XX_GRAS_GS_CL_CNTL_CULL_MASK__SHIFT = 8 # macro
REG_A6XX_GRAS_MAX_LAYER_INDEX = 0x00008004 # macro
REG_A6XX_GRAS_CNTL = 0x00008005 # macro
A6XX_GRAS_CNTL_IJ_PERSP_PIXEL = 0x00000001 # macro
A6XX_GRAS_CNTL_IJ_PERSP_CENTROID = 0x00000002 # macro
A6XX_GRAS_CNTL_IJ_PERSP_SAMPLE = 0x00000004 # macro
A6XX_GRAS_CNTL_IJ_LINEAR_PIXEL = 0x00000008 # macro
A6XX_GRAS_CNTL_IJ_LINEAR_CENTROID = 0x00000010 # macro
A6XX_GRAS_CNTL_IJ_LINEAR_SAMPLE = 0x00000020 # macro
A6XX_GRAS_CNTL_COORD_MASK__MASK = 0x000003c0 # macro
A6XX_GRAS_CNTL_COORD_MASK__SHIFT = 6 # macro
A6XX_GRAS_CNTL_UNK10 = 0x00000400 # macro
A6XX_GRAS_CNTL_UNK11 = 0x00000800 # macro
REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ = 0x00008006 # macro
A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK = 0x000001ff # macro
A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT = 0 # macro
A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK = 0x0007fc00 # macro
A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT = 10 # macro
REG_A7XX_GRAS_UNKNOWN_8007 = 0x00008007 # macro
REG_A7XX_GRAS_UNKNOWN_8008 = 0x00008008 # macro
REG_A7XX_GRAS_UNKNOWN_8009 = 0x00008009 # macro
REG_A7XX_GRAS_UNKNOWN_800A = 0x0000800a # macro
REG_A7XX_GRAS_UNKNOWN_800B = 0x0000800b # macro
REG_A7XX_GRAS_UNKNOWN_800C = 0x0000800c # macro
# def REG_A6XX_GRAS_CL_VPORT(i0): # macro
# return (0x00008010+0x6*i0)
A6XX_GRAS_CL_VPORT_XOFFSET__MASK = 0xffffffff # macro
A6XX_GRAS_CL_VPORT_XOFFSET__SHIFT = 0 # macro
A6XX_GRAS_CL_VPORT_XSCALE__MASK = 0xffffffff # macro
A6XX_GRAS_CL_VPORT_XSCALE__SHIFT = 0 # macro
A6XX_GRAS_CL_VPORT_YOFFSET__MASK = 0xffffffff # macro
A6XX_GRAS_CL_VPORT_YOFFSET__SHIFT = 0 # macro
A6XX_GRAS_CL_VPORT_YSCALE__MASK = 0xffffffff # macro
A6XX_GRAS_CL_VPORT_YSCALE__SHIFT = 0 # macro
A6XX_GRAS_CL_VPORT_ZOFFSET__MASK = 0xffffffff # macro
A6XX_GRAS_CL_VPORT_ZOFFSET__SHIFT = 0 # macro
A6XX_GRAS_CL_VPORT_ZSCALE__MASK = 0xffffffff # macro
A6XX_GRAS_CL_VPORT_ZSCALE__SHIFT = 0 # macro
# def REG_A6XX_GRAS_CL_Z_CLAMP(i0): # macro
# return (0x00008070+0x2*i0)
A6XX_GRAS_CL_Z_CLAMP_MIN__MASK = 0xffffffff # macro
A6XX_GRAS_CL_Z_CLAMP_MIN__SHIFT = 0 # macro
A6XX_GRAS_CL_Z_CLAMP_MAX__MASK = 0xffffffff # macro
A6XX_GRAS_CL_Z_CLAMP_MAX__SHIFT = 0 # macro
REG_A6XX_GRAS_SU_CNTL = 0x00008090 # macro
A6XX_GRAS_SU_CNTL_CULL_FRONT = 0x00000001 # macro
A6XX_GRAS_SU_CNTL_CULL_BACK = 0x00000002 # macro
A6XX_GRAS_SU_CNTL_FRONT_CW = 0x00000004 # macro
A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK = 0x000007f8 # macro
A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT = 3 # macro
A6XX_GRAS_SU_CNTL_POLY_OFFSET = 0x00000800 # macro
A6XX_GRAS_SU_CNTL_UNK12 = 0x00001000 # macro
A6XX_GRAS_SU_CNTL_LINE_MODE__MASK = 0x00002000 # macro
A6XX_GRAS_SU_CNTL_LINE_MODE__SHIFT = 13 # macro
A6XX_GRAS_SU_CNTL_UNK15__MASK = 0x00018000 # macro
A6XX_GRAS_SU_CNTL_UNK15__SHIFT = 15 # macro
A6XX_GRAS_SU_CNTL_MULTIVIEW_ENABLE = 0x00020000 # macro
A6XX_GRAS_SU_CNTL_RENDERTARGETINDEXINCR = 0x00040000 # macro
A6XX_GRAS_SU_CNTL_VIEWPORTINDEXINCR = 0x00080000 # macro
A6XX_GRAS_SU_CNTL_UNK20__MASK = 0x00700000 # macro
A6XX_GRAS_SU_CNTL_UNK20__SHIFT = 20 # macro
REG_A6XX_GRAS_SU_POINT_MINMAX = 0x00008091 # macro
A6XX_GRAS_SU_POINT_MINMAX_MIN__MASK = 0x0000ffff # macro
A6XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT = 0 # macro
A6XX_GRAS_SU_POINT_MINMAX_MAX__MASK = 0xffff0000 # macro
A6XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT = 16 # macro
REG_A6XX_GRAS_SU_POINT_SIZE = 0x00008092 # macro
A6XX_GRAS_SU_POINT_SIZE__MASK = 0x0000ffff # macro
A6XX_GRAS_SU_POINT_SIZE__SHIFT = 0 # macro
REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL = 0x00008094 # macro
A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__MASK = 0x00000003 # macro
A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__SHIFT = 0 # macro
REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE = 0x00008095 # macro
A6XX_GRAS_SU_POLY_OFFSET_SCALE__MASK = 0xffffffff # macro
A6XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT = 0 # macro
REG_A6XX_GRAS_SU_POLY_OFFSET_OFFSET = 0x00008096 # macro
A6XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK = 0xffffffff # macro
A6XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT = 0 # macro
REG_A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP = 0x00008097 # macro
A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK = 0xffffffff # macro
A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT = 0 # macro
REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO = 0x00008098 # macro
A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK = 0x00000007 # macro
A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT = 0 # macro
A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3 = 0x00000008 # macro
REG_A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL = 0x00008099 # macro
A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_CONSERVATIVERASEN = 0x00000001 # macro
A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT__MASK = 0x00000006 # macro
A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT__SHIFT = 1 # macro
A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_INNERCONSERVATIVERASEN = 0x00000008 # macro
A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4__MASK = 0x00000030 # macro
A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4__SHIFT = 4 # macro
REG_A6XX_GRAS_SU_PATH_RENDERING_CNTL = 0x0000809a # macro
A6XX_GRAS_SU_PATH_RENDERING_CNTL_UNK0 = 0x00000001 # macro
A6XX_GRAS_SU_PATH_RENDERING_CNTL_LINELENGTHEN = 0x00000002 # macro
REG_A6XX_GRAS_VS_LAYER_CNTL = 0x0000809b # macro
A6XX_GRAS_VS_LAYER_CNTL_WRITES_LAYER = 0x00000001 # macro
A6XX_GRAS_VS_LAYER_CNTL_WRITES_VIEW = 0x00000002 # macro
REG_A6XX_GRAS_GS_LAYER_CNTL = 0x0000809c # macro
A6XX_GRAS_GS_LAYER_CNTL_WRITES_LAYER = 0x00000001 # macro
A6XX_GRAS_GS_LAYER_CNTL_WRITES_VIEW = 0x00000002 # macro
REG_A6XX_GRAS_DS_LAYER_CNTL = 0x0000809d # macro
A6XX_GRAS_DS_LAYER_CNTL_WRITES_LAYER = 0x00000001 # macro
A6XX_GRAS_DS_LAYER_CNTL_WRITES_VIEW = 0x00000002 # macro
REG_A6XX_GRAS_SC_CNTL = 0x000080a0 # macro
A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE__MASK = 0x00000007 # macro
A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE__SHIFT = 0 # macro
A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE__MASK = 0x00000018 # macro
A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE__SHIFT = 3 # macro
A6XX_GRAS_SC_CNTL_RASTER_MODE__MASK = 0x00000020 # macro
A6XX_GRAS_SC_CNTL_RASTER_MODE__SHIFT = 5 # macro
A6XX_GRAS_SC_CNTL_RASTER_DIRECTION__MASK = 0x000000c0 # macro
A6XX_GRAS_SC_CNTL_RASTER_DIRECTION__SHIFT = 6 # macro
A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION__MASK = 0x00000100 # macro
A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION__SHIFT = 8 # macro
A6XX_GRAS_SC_CNTL_UNK9 = 0x00000200 # macro
A6XX_GRAS_SC_CNTL_ROTATION__MASK = 0x00000c00 # macro
A6XX_GRAS_SC_CNTL_ROTATION__SHIFT = 10 # macro
A6XX_GRAS_SC_CNTL_EARLYVIZOUTEN = 0x00001000 # macro
REG_A6XX_GRAS_BIN_CONTROL = 0x000080a1 # macro
A6XX_GRAS_BIN_CONTROL_BINW__MASK = 0x0000003f # macro
A6XX_GRAS_BIN_CONTROL_BINW__SHIFT = 0 # macro
A6XX_GRAS_BIN_CONTROL_BINH__MASK = 0x00007f00 # macro
A6XX_GRAS_BIN_CONTROL_BINH__SHIFT = 8 # macro
A6XX_GRAS_BIN_CONTROL_RENDER_MODE__MASK = 0x001c0000 # macro
A6XX_GRAS_BIN_CONTROL_RENDER_MODE__SHIFT = 18 # macro
A6XX_GRAS_BIN_CONTROL_FORCE_LRZ_WRITE_DIS = 0x00200000 # macro
A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION__MASK = 0x00c00000 # macro
A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION__SHIFT = 22 # macro
A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK = 0x07000000 # macro
A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT = 24 # macro
A6XX_GRAS_BIN_CONTROL_UNK27 = 0x08000000 # macro
REG_A6XX_GRAS_RAS_MSAA_CNTL = 0x000080a2 # macro
A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__MASK = 0x00000003 # macro
A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__SHIFT = 0 # macro
A6XX_GRAS_RAS_MSAA_CNTL_UNK2 = 0x00000004 # macro
A6XX_GRAS_RAS_MSAA_CNTL_UNK3 = 0x00000008 # macro
REG_A6XX_GRAS_DEST_MSAA_CNTL = 0x000080a3 # macro
A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__MASK = 0x00000003 # macro
A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__SHIFT = 0 # macro
A6XX_GRAS_DEST_MSAA_CNTL_MSAA_DISABLE = 0x00000004 # macro
REG_A6XX_GRAS_SAMPLE_CONFIG = 0x000080a4 # macro
A6XX_GRAS_SAMPLE_CONFIG_UNK0 = 0x00000001 # macro
A6XX_GRAS_SAMPLE_CONFIG_LOCATION_ENABLE = 0x00000002 # macro
REG_A6XX_GRAS_SAMPLE_LOCATION_0 = 0x000080a5 # macro
A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK = 0x0000000f # macro
A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT = 0 # macro
A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK = 0x000000f0 # macro
A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT = 4 # macro
A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK = 0x00000f00 # macro
A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT = 8 # macro
A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK = 0x0000f000 # macro
A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT = 12 # macro
A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK = 0x000f0000 # macro
A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT = 16 # macro
A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK = 0x00f00000 # macro
A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT = 20 # macro
A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK = 0x0f000000 # macro
A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT = 24 # macro
A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK = 0xf0000000 # macro
A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT = 28 # macro
REG_A6XX_GRAS_SAMPLE_LOCATION_1 = 0x000080a6 # macro
A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK = 0x0000000f # macro
A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT = 0 # macro
A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK = 0x000000f0 # macro
A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT = 4 # macro
A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK = 0x00000f00 # macro
A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT = 8 # macro
A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK = 0x0000f000 # macro
A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT = 12 # macro
A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK = 0x000f0000 # macro
A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT = 16 # macro
A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK = 0x00f00000 # macro
A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT = 20 # macro
A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK = 0x0f000000 # macro
A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT = 24 # macro
A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK = 0xf0000000 # macro
A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT = 28 # macro
REG_A7XX_GRAS_UNKNOWN_80A7 = 0x000080a7 # macro
REG_A6XX_GRAS_UNKNOWN_80AF = 0x000080af # macro
# def REG_A6XX_GRAS_SC_SCREEN_SCISSOR(i0): # macro
# return (0x000080b0+0x2*i0)
A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK = 0x0000ffff # macro
A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT = 0 # macro
A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK = 0xffff0000 # macro
A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT = 16 # macro
A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK = 0x0000ffff # macro
A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT = 0 # macro
A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK = 0xffff0000 # macro
A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT = 16 # macro
# def REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR(i0): # macro
# return (0x000080d0+0x2*i0)
A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__MASK = 0x0000ffff # macro
A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__SHIFT = 0 # macro
A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__MASK = 0xffff0000 # macro
A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__SHIFT = 16 # macro
A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__MASK = 0x0000ffff # macro
A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__SHIFT = 0 # macro
A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__MASK = 0xffff0000 # macro
A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__SHIFT = 16 # macro
REG_A6XX_GRAS_SC_WINDOW_SCISSOR_TL = 0x000080f0 # macro
A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK = 0x00003fff # macro
A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT = 0 # macro
A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK = 0x3fff0000 # macro
A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT = 16 # macro
REG_A6XX_GRAS_SC_WINDOW_SCISSOR_BR = 0x000080f1 # macro
A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK = 0x00003fff # macro
A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT = 0 # macro
A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK = 0x3fff0000 # macro
A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT = 16 # macro
REG_A7XX_GRAS_UNKNOWN_80F4 = 0x000080f4 # macro
REG_A7XX_GRAS_UNKNOWN_80F5 = 0x000080f5 # macro
REG_A7XX_GRAS_UNKNOWN_80F6 = 0x000080f6 # macro
REG_A7XX_GRAS_UNKNOWN_80F8 = 0x000080f8 # macro
REG_A7XX_GRAS_UNKNOWN_80F9 = 0x000080f9 # macro
REG_A7XX_GRAS_UNKNOWN_80FA = 0x000080fa # macro
REG_A6XX_GRAS_LRZ_CNTL = 0x00008100 # macro
A6XX_GRAS_LRZ_CNTL_ENABLE = 0x00000001 # macro
A6XX_GRAS_LRZ_CNTL_LRZ_WRITE = 0x00000002 # macro
A6XX_GRAS_LRZ_CNTL_GREATER = 0x00000004 # macro
A6XX_GRAS_LRZ_CNTL_FC_ENABLE = 0x00000008 # macro
A6XX_GRAS_LRZ_CNTL_Z_TEST_ENABLE = 0x00000010 # macro
A6XX_GRAS_LRZ_CNTL_Z_BOUNDS_ENABLE = 0x00000020 # macro
A6XX_GRAS_LRZ_CNTL_DIR__MASK = 0x000000c0 # macro
A6XX_GRAS_LRZ_CNTL_DIR__SHIFT = 6 # macro
A6XX_GRAS_LRZ_CNTL_DIR_WRITE = 0x00000100 # macro
A6XX_GRAS_LRZ_CNTL_DISABLE_ON_WRONG_DIR = 0x00000200 # macro
A6XX_GRAS_LRZ_CNTL_Z_FUNC__MASK = 0x00003800 # macro
A6XX_GRAS_LRZ_CNTL_Z_FUNC__SHIFT = 11 # macro
REG_A6XX_GRAS_LRZ_PS_INPUT_CNTL = 0x00008101 # macro
A6XX_GRAS_LRZ_PS_INPUT_CNTL_SAMPLEID = 0x00000001 # macro
A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE__MASK = 0x00000006 # macro
A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE__SHIFT = 1 # macro
REG_A6XX_GRAS_LRZ_MRT_BUF_INFO_0 = 0x00008102 # macro
A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT__MASK = 0x000000ff # macro
A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT__SHIFT = 0 # macro
REG_A6XX_GRAS_LRZ_BUFFER_BASE = 0x00008103 # macro
REG_A6XX_GRAS_LRZ_BUFFER_PITCH = 0x00008105 # macro
A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__MASK = 0x000000ff # macro
A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__SHIFT = 0 # macro
A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK = 0x1ffffc00 # macro
A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT = 10 # macro
REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE = 0x00008106 # macro
REG_A6XX_GRAS_SAMPLE_CNTL = 0x00008109 # macro
A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE = 0x00000001 # macro
REG_A6XX_GRAS_LRZ_DEPTH_VIEW = 0x0000810a # macro
A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_LAYER__MASK = 0x000007ff # macro
A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_LAYER__SHIFT = 0 # macro
A6XX_GRAS_LRZ_DEPTH_VIEW_LAYER_COUNT__MASK = 0x07ff0000 # macro
A6XX_GRAS_LRZ_DEPTH_VIEW_LAYER_COUNT__SHIFT = 16 # macro
A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_MIP_LEVEL__MASK = 0xf0000000 # macro
A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_MIP_LEVEL__SHIFT = 28 # macro
REG_A7XX_GRAS_LRZ_CNTL2 = 0x0000810b # macro
A7XX_GRAS_LRZ_CNTL2_DISABLE_ON_WRONG_DIR = 0x00000001 # macro
A7XX_GRAS_LRZ_CNTL2_FC_ENABLE = 0x00000002 # macro
REG_A6XX_GRAS_UNKNOWN_8110 = 0x00008110 # macro
REG_A7XX_GRAS_LRZ_CLEAR_DEPTH_F32 = 0x00008111 # macro
A7XX_GRAS_LRZ_CLEAR_DEPTH_F32__MASK = 0xffffffff # macro
A7XX_GRAS_LRZ_CLEAR_DEPTH_F32__SHIFT = 0 # macro
REG_A7XX_GRAS_LRZ_DEPTH_BUFFER_INFO = 0x00008113 # macro
A7XX_GRAS_LRZ_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK = 0x00000007 # macro
A7XX_GRAS_LRZ_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT = 0 # macro
A7XX_GRAS_LRZ_DEPTH_BUFFER_INFO_UNK3 = 0x00000008 # macro
REG_A7XX_GRAS_UNKNOWN_8120 = 0x00008120 # macro
REG_A7XX_GRAS_UNKNOWN_8121 = 0x00008121 # macro
REG_A6XX_GRAS_2D_BLIT_CNTL = 0x00008400 # macro
A6XX_GRAS_2D_BLIT_CNTL_ROTATE__MASK = 0x00000007 # macro
A6XX_GRAS_2D_BLIT_CNTL_ROTATE__SHIFT = 0 # macro
A6XX_GRAS_2D_BLIT_CNTL_OVERWRITEEN = 0x00000008 # macro
A6XX_GRAS_2D_BLIT_CNTL_UNK4__MASK = 0x00000070 # macro
A6XX_GRAS_2D_BLIT_CNTL_UNK4__SHIFT = 4 # macro
A6XX_GRAS_2D_BLIT_CNTL_SOLID_COLOR = 0x00000080 # macro
A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__MASK = 0x0000ff00 # macro
A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT = 8 # macro
A6XX_GRAS_2D_BLIT_CNTL_SCISSOR = 0x00010000 # macro
A6XX_GRAS_2D_BLIT_CNTL_UNK17__MASK = 0x00060000 # macro
A6XX_GRAS_2D_BLIT_CNTL_UNK17__SHIFT = 17 # macro
A6XX_GRAS_2D_BLIT_CNTL_D24S8 = 0x00080000 # macro
A6XX_GRAS_2D_BLIT_CNTL_MASK__MASK = 0x00f00000 # macro
A6XX_GRAS_2D_BLIT_CNTL_MASK__SHIFT = 20 # macro
A6XX_GRAS_2D_BLIT_CNTL_IFMT__MASK = 0x1f000000 # macro
A6XX_GRAS_2D_BLIT_CNTL_IFMT__SHIFT = 24 # macro
A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE__MASK = 0x20000000 # macro
A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE__SHIFT = 29 # macro
A6XX_GRAS_2D_BLIT_CNTL_UNK30 = 0x40000000 # macro
REG_A6XX_GRAS_2D_SRC_TL_X = 0x00008401 # macro
A6XX_GRAS_2D_SRC_TL_X__MASK = 0x01ffff00 # macro
A6XX_GRAS_2D_SRC_TL_X__SHIFT = 8 # macro
REG_A6XX_GRAS_2D_SRC_BR_X = 0x00008402 # macro
A6XX_GRAS_2D_SRC_BR_X__MASK = 0x01ffff00 # macro
A6XX_GRAS_2D_SRC_BR_X__SHIFT = 8 # macro
REG_A6XX_GRAS_2D_SRC_TL_Y = 0x00008403 # macro
A6XX_GRAS_2D_SRC_TL_Y__MASK = 0x01ffff00 # macro
A6XX_GRAS_2D_SRC_TL_Y__SHIFT = 8 # macro
REG_A6XX_GRAS_2D_SRC_BR_Y = 0x00008404 # macro
A6XX_GRAS_2D_SRC_BR_Y__MASK = 0x01ffff00 # macro
A6XX_GRAS_2D_SRC_BR_Y__SHIFT = 8 # macro
REG_A6XX_GRAS_2D_DST_TL = 0x00008405 # macro
A6XX_GRAS_2D_DST_TL_X__MASK = 0x00003fff # macro
A6XX_GRAS_2D_DST_TL_X__SHIFT = 0 # macro
A6XX_GRAS_2D_DST_TL_Y__MASK = 0x3fff0000 # macro
A6XX_GRAS_2D_DST_TL_Y__SHIFT = 16 # macro
REG_A6XX_GRAS_2D_DST_BR = 0x00008406 # macro
A6XX_GRAS_2D_DST_BR_X__MASK = 0x00003fff # macro
A6XX_GRAS_2D_DST_BR_X__SHIFT = 0 # macro
A6XX_GRAS_2D_DST_BR_Y__MASK = 0x3fff0000 # macro
A6XX_GRAS_2D_DST_BR_Y__SHIFT = 16 # macro
REG_A6XX_GRAS_2D_UNKNOWN_8407 = 0x00008407 # macro
REG_A6XX_GRAS_2D_UNKNOWN_8408 = 0x00008408 # macro
REG_A6XX_GRAS_2D_UNKNOWN_8409 = 0x00008409 # macro
REG_A6XX_GRAS_2D_RESOLVE_CNTL_1 = 0x0000840a # macro
A6XX_GRAS_2D_RESOLVE_CNTL_1_X__MASK = 0x00003fff # macro
A6XX_GRAS_2D_RESOLVE_CNTL_1_X__SHIFT = 0 # macro
A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__MASK = 0x3fff0000 # macro
A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__SHIFT = 16 # macro
REG_A6XX_GRAS_2D_RESOLVE_CNTL_2 = 0x0000840b # macro
A6XX_GRAS_2D_RESOLVE_CNTL_2_X__MASK = 0x00003fff # macro
A6XX_GRAS_2D_RESOLVE_CNTL_2_X__SHIFT = 0 # macro
A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__MASK = 0x3fff0000 # macro
A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__SHIFT = 16 # macro
REG_A6XX_GRAS_DBG_ECO_CNTL = 0x00008600 # macro
A6XX_GRAS_DBG_ECO_CNTL_UNK7 = 0x00000080 # macro
A6XX_GRAS_DBG_ECO_CNTL_LRZCACHELOCKDIS = 0x00000800 # macro
REG_A6XX_GRAS_ADDR_MODE_CNTL = 0x00008601 # macro
REG_A7XX_GRAS_NC_MODE_CNTL = 0x00008602 # macro
# def REG_A6XX_GRAS_PERFCTR_TSE_SEL(i0): # macro
# return (0x00008610+0x1*i0)
# def REG_A6XX_GRAS_PERFCTR_RAS_SEL(i0): # macro
# return (0x00008614+0x1*i0)
# def REG_A6XX_GRAS_PERFCTR_LRZ_SEL(i0): # macro
# return (0x00008618+0x1*i0)
REG_A6XX_RB_BIN_CONTROL = 0x00008800 # macro
A6XX_RB_BIN_CONTROL_BINW__MASK = 0x0000003f # macro
A6XX_RB_BIN_CONTROL_BINW__SHIFT = 0 # macro
A6XX_RB_BIN_CONTROL_BINH__MASK = 0x00007f00 # macro
A6XX_RB_BIN_CONTROL_BINH__SHIFT = 8 # macro
A6XX_RB_BIN_CONTROL_RENDER_MODE__MASK = 0x001c0000 # macro
A6XX_RB_BIN_CONTROL_RENDER_MODE__SHIFT = 18 # macro
A6XX_RB_BIN_CONTROL_FORCE_LRZ_WRITE_DIS = 0x00200000 # macro
A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION__MASK = 0x00c00000 # macro
A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION__SHIFT = 22 # macro
A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK = 0x07000000 # macro
A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT = 24 # macro
REG_A7XX_RB_BIN_CONTROL = 0x00008800 # macro
A7XX_RB_BIN_CONTROL_BINW__MASK = 0x0000003f # macro
A7XX_RB_BIN_CONTROL_BINW__SHIFT = 0 # macro
A7XX_RB_BIN_CONTROL_BINH__MASK = 0x00007f00 # macro
A7XX_RB_BIN_CONTROL_BINH__SHIFT = 8 # macro
A7XX_RB_BIN_CONTROL_RENDER_MODE__MASK = 0x001c0000 # macro
A7XX_RB_BIN_CONTROL_RENDER_MODE__SHIFT = 18 # macro
A7XX_RB_BIN_CONTROL_FORCE_LRZ_WRITE_DIS = 0x00200000 # macro
A7XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK = 0x07000000 # macro
A7XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT = 24 # macro
REG_A6XX_RB_RENDER_CNTL = 0x00008801 # macro
A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE__MASK = 0x00000038 # macro
A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE__SHIFT = 3 # macro
A6XX_RB_RENDER_CNTL_EARLYVIZOUTEN = 0x00000040 # macro
A6XX_RB_RENDER_CNTL_BINNING = 0x00000080 # macro
A6XX_RB_RENDER_CNTL_UNK8__MASK = 0x00000700 # macro
A6XX_RB_RENDER_CNTL_UNK8__SHIFT = 8 # macro
A6XX_RB_RENDER_CNTL_RASTER_MODE__MASK = 0x00000100 # macro
A6XX_RB_RENDER_CNTL_RASTER_MODE__SHIFT = 8 # macro
A6XX_RB_RENDER_CNTL_RASTER_DIRECTION__MASK = 0x00000600 # macro
A6XX_RB_RENDER_CNTL_RASTER_DIRECTION__SHIFT = 9 # macro
A6XX_RB_RENDER_CNTL_CONSERVATIVERASEN = 0x00000800 # macro
A6XX_RB_RENDER_CNTL_INNERCONSERVATIVERASEN = 0x00001000 # macro
A6XX_RB_RENDER_CNTL_FLAG_DEPTH = 0x00004000 # macro
A6XX_RB_RENDER_CNTL_FLAG_MRTS__MASK = 0x00ff0000 # macro
A6XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT = 16 # macro
REG_A7XX_RB_RENDER_CNTL = 0x00008801 # macro
A7XX_RB_RENDER_CNTL_EARLYVIZOUTEN = 0x00000040 # macro
A7XX_RB_RENDER_CNTL_BINNING = 0x00000080 # macro
A7XX_RB_RENDER_CNTL_RASTER_MODE__MASK = 0x00000100 # macro
A7XX_RB_RENDER_CNTL_RASTER_MODE__SHIFT = 8 # macro
A7XX_RB_RENDER_CNTL_RASTER_DIRECTION__MASK = 0x00000600 # macro
A7XX_RB_RENDER_CNTL_RASTER_DIRECTION__SHIFT = 9 # macro
A7XX_RB_RENDER_CNTL_CONSERVATIVERASEN = 0x00000800 # macro
A7XX_RB_RENDER_CNTL_INNERCONSERVATIVERASEN = 0x00001000 # macro
REG_A7XX_GRAS_SU_RENDER_CNTL = 0x00008116 # macro
A7XX_GRAS_SU_RENDER_CNTL_BINNING = 0x00000080 # macro
REG_A6XX_RB_RAS_MSAA_CNTL = 0x00008802 # macro
A6XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK = 0x00000003 # macro
A6XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT = 0 # macro
A6XX_RB_RAS_MSAA_CNTL_UNK2 = 0x00000004 # macro
A6XX_RB_RAS_MSAA_CNTL_UNK3 = 0x00000008 # macro
REG_A6XX_RB_DEST_MSAA_CNTL = 0x00008803 # macro
A6XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK = 0x00000003 # macro
A6XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT = 0 # macro
A6XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE = 0x00000004 # macro
REG_A6XX_RB_SAMPLE_CONFIG = 0x00008804 # macro
A6XX_RB_SAMPLE_CONFIG_UNK0 = 0x00000001 # macro
A6XX_RB_SAMPLE_CONFIG_LOCATION_ENABLE = 0x00000002 # macro
REG_A6XX_RB_SAMPLE_LOCATION_0 = 0x00008805 # macro
A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK = 0x0000000f # macro
A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT = 0 # macro
A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK = 0x000000f0 # macro
A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT = 4 # macro
A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK = 0x00000f00 # macro
A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT = 8 # macro
A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK = 0x0000f000 # macro
A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT = 12 # macro
A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK = 0x000f0000 # macro
A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT = 16 # macro
A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK = 0x00f00000 # macro
A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT = 20 # macro
A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK = 0x0f000000 # macro
A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT = 24 # macro
A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK = 0xf0000000 # macro
A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT = 28 # macro
REG_A6XX_RB_SAMPLE_LOCATION_1 = 0x00008806 # macro
A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK = 0x0000000f # macro
A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT = 0 # macro
A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK = 0x000000f0 # macro
A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT = 4 # macro
A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK = 0x00000f00 # macro
A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT = 8 # macro
A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK = 0x0000f000 # macro
A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT = 12 # macro
A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK = 0x000f0000 # macro
A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT = 16 # macro
A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK = 0x00f00000 # macro
A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT = 20 # macro
A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK = 0x0f000000 # macro
A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT = 24 # macro
A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK = 0xf0000000 # macro
A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT = 28 # macro
REG_A6XX_RB_RENDER_CONTROL0 = 0x00008809 # macro
A6XX_RB_RENDER_CONTROL0_IJ_PERSP_PIXEL = 0x00000001 # macro
A6XX_RB_RENDER_CONTROL0_IJ_PERSP_CENTROID = 0x00000002 # macro
A6XX_RB_RENDER_CONTROL0_IJ_PERSP_SAMPLE = 0x00000004 # macro
A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_PIXEL = 0x00000008 # macro
A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_CENTROID = 0x00000010 # macro
A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_SAMPLE = 0x00000020 # macro
A6XX_RB_RENDER_CONTROL0_COORD_MASK__MASK = 0x000003c0 # macro
A6XX_RB_RENDER_CONTROL0_COORD_MASK__SHIFT = 6 # macro
A6XX_RB_RENDER_CONTROL0_UNK10 = 0x00000400 # macro
REG_A6XX_RB_RENDER_CONTROL1 = 0x0000880a # macro
A6XX_RB_RENDER_CONTROL1_SAMPLEMASK = 0x00000001 # macro
A6XX_RB_RENDER_CONTROL1_POSTDEPTHCOVERAGE = 0x00000002 # macro
A6XX_RB_RENDER_CONTROL1_FACENESS = 0x00000004 # macro
A6XX_RB_RENDER_CONTROL1_SAMPLEID = 0x00000008 # macro
A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE__MASK = 0x00000030 # macro
A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE__SHIFT = 4 # macro
A6XX_RB_RENDER_CONTROL1_CENTERRHW = 0x00000040 # macro
A6XX_RB_RENDER_CONTROL1_LINELENGTHEN = 0x00000080 # macro
A6XX_RB_RENDER_CONTROL1_FOVEATION = 0x00000100 # macro
REG_A6XX_RB_FS_OUTPUT_CNTL0 = 0x0000880b # macro
A6XX_RB_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE = 0x00000001 # macro
A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z = 0x00000002 # macro
A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK = 0x00000004 # macro
A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_STENCILREF = 0x00000008 # macro
REG_A6XX_RB_FS_OUTPUT_CNTL1 = 0x0000880c # macro
A6XX_RB_FS_OUTPUT_CNTL1_MRT__MASK = 0x0000000f # macro
A6XX_RB_FS_OUTPUT_CNTL1_MRT__SHIFT = 0 # macro
REG_A6XX_RB_RENDER_COMPONENTS = 0x0000880d # macro
A6XX_RB_RENDER_COMPONENTS_RT0__MASK = 0x0000000f # macro
A6XX_RB_RENDER_COMPONENTS_RT0__SHIFT = 0 # macro
A6XX_RB_RENDER_COMPONENTS_RT1__MASK = 0x000000f0 # macro
A6XX_RB_RENDER_COMPONENTS_RT1__SHIFT = 4 # macro
A6XX_RB_RENDER_COMPONENTS_RT2__MASK = 0x00000f00 # macro
A6XX_RB_RENDER_COMPONENTS_RT2__SHIFT = 8 # macro
A6XX_RB_RENDER_COMPONENTS_RT3__MASK = 0x0000f000 # macro
A6XX_RB_RENDER_COMPONENTS_RT3__SHIFT = 12 # macro
A6XX_RB_RENDER_COMPONENTS_RT4__MASK = 0x000f0000 # macro
A6XX_RB_RENDER_COMPONENTS_RT4__SHIFT = 16 # macro
A6XX_RB_RENDER_COMPONENTS_RT5__MASK = 0x00f00000 # macro
A6XX_RB_RENDER_COMPONENTS_RT5__SHIFT = 20 # macro
A6XX_RB_RENDER_COMPONENTS_RT6__MASK = 0x0f000000 # macro
A6XX_RB_RENDER_COMPONENTS_RT6__SHIFT = 24 # macro
A6XX_RB_RENDER_COMPONENTS_RT7__MASK = 0xf0000000 # macro
A6XX_RB_RENDER_COMPONENTS_RT7__SHIFT = 28 # macro
REG_A6XX_RB_DITHER_CNTL = 0x0000880e # macro
A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__MASK = 0x00000003 # macro
A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__SHIFT = 0 # macro
A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__MASK = 0x0000000c # macro
A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__SHIFT = 2 # macro
A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__MASK = 0x00000030 # macro
A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__SHIFT = 4 # macro
A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__MASK = 0x000000c0 # macro
A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__SHIFT = 6 # macro
A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__MASK = 0x00000300 # macro
A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__SHIFT = 8 # macro
A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__MASK = 0x00000c00 # macro
A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__SHIFT = 10 # macro
A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__MASK = 0x00003000 # macro
A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__SHIFT = 12 # macro
A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__MASK = 0x0000c000 # macro
A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__SHIFT = 14 # macro
REG_A6XX_RB_SRGB_CNTL = 0x0000880f # macro
A6XX_RB_SRGB_CNTL_SRGB_MRT0 = 0x00000001 # macro
A6XX_RB_SRGB_CNTL_SRGB_MRT1 = 0x00000002 # macro
A6XX_RB_SRGB_CNTL_SRGB_MRT2 = 0x00000004 # macro
A6XX_RB_SRGB_CNTL_SRGB_MRT3 = 0x00000008 # macro
A6XX_RB_SRGB_CNTL_SRGB_MRT4 = 0x00000010 # macro
A6XX_RB_SRGB_CNTL_SRGB_MRT5 = 0x00000020 # macro
A6XX_RB_SRGB_CNTL_SRGB_MRT6 = 0x00000040 # macro
A6XX_RB_SRGB_CNTL_SRGB_MRT7 = 0x00000080 # macro
REG_A6XX_RB_SAMPLE_CNTL = 0x00008810 # macro
A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE = 0x00000001 # macro
REG_A6XX_RB_UNKNOWN_8811 = 0x00008811 # macro
REG_A7XX_RB_UNKNOWN_8812 = 0x00008812 # macro
REG_A6XX_RB_UNKNOWN_8818 = 0x00008818 # macro
REG_A6XX_RB_UNKNOWN_8819 = 0x00008819 # macro
REG_A6XX_RB_UNKNOWN_881A = 0x0000881a # macro
REG_A6XX_RB_UNKNOWN_881B = 0x0000881b # macro
REG_A6XX_RB_UNKNOWN_881C = 0x0000881c # macro
REG_A6XX_RB_UNKNOWN_881D = 0x0000881d # macro
REG_A6XX_RB_UNKNOWN_881E = 0x0000881e # macro
# def REG_A6XX_RB_MRT(i0): # macro
# return (0x00008820+0x8*i0)
A6XX_RB_MRT_CONTROL_BLEND = 0x00000001 # macro
A6XX_RB_MRT_CONTROL_BLEND2 = 0x00000002 # macro
A6XX_RB_MRT_CONTROL_ROP_ENABLE = 0x00000004 # macro
A6XX_RB_MRT_CONTROL_ROP_CODE__MASK = 0x00000078 # macro
A6XX_RB_MRT_CONTROL_ROP_CODE__SHIFT = 3 # macro
A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK = 0x00000780 # macro
A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT = 7 # macro
A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK = 0x0000001f # macro
A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT = 0 # macro
A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK = 0x000000e0 # macro
A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT = 5 # macro
A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK = 0x00001f00 # macro
A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT = 8 # macro
A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK = 0x001f0000 # macro
A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT = 16 # macro
A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK = 0x00e00000 # macro
A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT = 21 # macro
A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK = 0x1f000000 # macro
A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT = 24 # macro
A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK = 0x000000ff # macro
A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT = 0 # macro
A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK = 0x00000300 # macro
A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT = 8 # macro
A6XX_RB_MRT_BUF_INFO_UNK10 = 0x00000400 # macro
A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK = 0x00006000 # macro
A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT = 13 # macro
A7XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK = 0x000000ff # macro
A7XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT = 0 # macro
A7XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK = 0x00000300 # macro
A7XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT = 8 # macro
A7XX_RB_MRT_BUF_INFO_UNK10 = 0x00000400 # macro
A7XX_RB_MRT_BUF_INFO_LOSSLESSCOMPEN = 0x00000800 # macro
A7XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK = 0x00006000 # macro
A7XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT = 13 # macro
A6XX_RB_MRT_PITCH__MASK = 0xffffffff # macro
A6XX_RB_MRT_PITCH__SHIFT = 0 # macro
A6XX_RB_MRT_ARRAY_PITCH__MASK = 0xffffffff # macro
A6XX_RB_MRT_ARRAY_PITCH__SHIFT = 0 # macro
REG_A6XX_RB_BLEND_RED_F32 = 0x00008860 # macro
A6XX_RB_BLEND_RED_F32__MASK = 0xffffffff # macro
A6XX_RB_BLEND_RED_F32__SHIFT = 0 # macro
REG_A6XX_RB_BLEND_GREEN_F32 = 0x00008861 # macro
A6XX_RB_BLEND_GREEN_F32__MASK = 0xffffffff # macro
A6XX_RB_BLEND_GREEN_F32__SHIFT = 0 # macro
REG_A6XX_RB_BLEND_BLUE_F32 = 0x00008862 # macro
A6XX_RB_BLEND_BLUE_F32__MASK = 0xffffffff # macro
A6XX_RB_BLEND_BLUE_F32__SHIFT = 0 # macro
REG_A6XX_RB_BLEND_ALPHA_F32 = 0x00008863 # macro
A6XX_RB_BLEND_ALPHA_F32__MASK = 0xffffffff # macro
A6XX_RB_BLEND_ALPHA_F32__SHIFT = 0 # macro
REG_A6XX_RB_ALPHA_CONTROL = 0x00008864 # macro
A6XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK = 0x000000ff # macro
A6XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT = 0 # macro
A6XX_RB_ALPHA_CONTROL_ALPHA_TEST = 0x00000100 # macro
A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK = 0x00000e00 # macro
A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT = 9 # macro
REG_A6XX_RB_BLEND_CNTL = 0x00008865 # macro
A6XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK = 0x000000ff # macro
A6XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT = 0 # macro
A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND = 0x00000100 # macro
A6XX_RB_BLEND_CNTL_DUAL_COLOR_IN_ENABLE = 0x00000200 # macro
A6XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE = 0x00000400 # macro
A6XX_RB_BLEND_CNTL_ALPHA_TO_ONE = 0x00000800 # macro
A6XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK = 0xffff0000 # macro
A6XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT = 16 # macro
REG_A6XX_RB_DEPTH_PLANE_CNTL = 0x00008870 # macro
A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__MASK = 0x00000003 # macro
A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__SHIFT = 0 # macro
REG_A6XX_RB_DEPTH_CNTL = 0x00008871 # macro
A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE = 0x00000001 # macro
A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE = 0x00000002 # macro
A6XX_RB_DEPTH_CNTL_ZFUNC__MASK = 0x0000001c # macro
A6XX_RB_DEPTH_CNTL_ZFUNC__SHIFT = 2 # macro
A6XX_RB_DEPTH_CNTL_Z_CLAMP_ENABLE = 0x00000020 # macro
A6XX_RB_DEPTH_CNTL_Z_READ_ENABLE = 0x00000040 # macro
A6XX_RB_DEPTH_CNTL_Z_BOUNDS_ENABLE = 0x00000080 # macro
REG_A6XX_GRAS_SU_DEPTH_CNTL = 0x00008114 # macro
A6XX_GRAS_SU_DEPTH_CNTL_Z_TEST_ENABLE = 0x00000001 # macro
REG_A6XX_RB_DEPTH_BUFFER_INFO = 0x00008872 # macro
A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK = 0x00000007 # macro
A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT = 0 # macro
A6XX_RB_DEPTH_BUFFER_INFO_UNK3__MASK = 0x00000018 # macro
A6XX_RB_DEPTH_BUFFER_INFO_UNK3__SHIFT = 3 # macro
REG_A7XX_RB_DEPTH_BUFFER_INFO = 0x00008872 # macro
A7XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK = 0x00000007 # macro
A7XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT = 0 # macro
A7XX_RB_DEPTH_BUFFER_INFO_UNK3__MASK = 0x00000018 # macro
A7XX_RB_DEPTH_BUFFER_INFO_UNK3__SHIFT = 3 # macro
A7XX_RB_DEPTH_BUFFER_INFO_TILEMODE__MASK = 0x00000060 # macro
A7XX_RB_DEPTH_BUFFER_INFO_TILEMODE__SHIFT = 5 # macro
A7XX_RB_DEPTH_BUFFER_INFO_LOSSLESSCOMPEN = 0x00000080 # macro
REG_A6XX_RB_DEPTH_BUFFER_PITCH = 0x00008873 # macro
A6XX_RB_DEPTH_BUFFER_PITCH__MASK = 0x00003fff # macro
A6XX_RB_DEPTH_BUFFER_PITCH__SHIFT = 0 # macro
REG_A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH = 0x00008874 # macro
A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK = 0x0fffffff # macro
A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT = 0 # macro
REG_A6XX_RB_DEPTH_BUFFER_BASE = 0x00008875 # macro
REG_A6XX_RB_DEPTH_BUFFER_BASE_GMEM = 0x00008877 # macro
REG_A6XX_RB_Z_BOUNDS_MIN = 0x00008878 # macro
A6XX_RB_Z_BOUNDS_MIN__MASK = 0xffffffff # macro
A6XX_RB_Z_BOUNDS_MIN__SHIFT = 0 # macro
REG_A6XX_RB_Z_BOUNDS_MAX = 0x00008879 # macro
A6XX_RB_Z_BOUNDS_MAX__MASK = 0xffffffff # macro
A6XX_RB_Z_BOUNDS_MAX__SHIFT = 0 # macro
REG_A6XX_RB_STENCIL_CONTROL = 0x00008880 # macro
A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE = 0x00000001 # macro
A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF = 0x00000002 # macro
A6XX_RB_STENCIL_CONTROL_STENCIL_READ = 0x00000004 # macro
A6XX_RB_STENCIL_CONTROL_FUNC__MASK = 0x00000700 # macro
A6XX_RB_STENCIL_CONTROL_FUNC__SHIFT = 8 # macro
A6XX_RB_STENCIL_CONTROL_FAIL__MASK = 0x00003800 # macro
A6XX_RB_STENCIL_CONTROL_FAIL__SHIFT = 11 # macro
A6XX_RB_STENCIL_CONTROL_ZPASS__MASK = 0x0001c000 # macro
A6XX_RB_STENCIL_CONTROL_ZPASS__SHIFT = 14 # macro
A6XX_RB_STENCIL_CONTROL_ZFAIL__MASK = 0x000e0000 # macro
A6XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT = 17 # macro
A6XX_RB_STENCIL_CONTROL_FUNC_BF__MASK = 0x00700000 # macro
A6XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT = 20 # macro
A6XX_RB_STENCIL_CONTROL_FAIL_BF__MASK = 0x03800000 # macro
A6XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT = 23 # macro
A6XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK = 0x1c000000 # macro
A6XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT = 26 # macro
A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK = 0xe0000000 # macro
A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT = 29 # macro
REG_A6XX_GRAS_SU_STENCIL_CNTL = 0x00008115 # macro
A6XX_GRAS_SU_STENCIL_CNTL_STENCIL_ENABLE = 0x00000001 # macro
REG_A6XX_RB_STENCIL_INFO = 0x00008881 # macro
A6XX_RB_STENCIL_INFO_SEPARATE_STENCIL = 0x00000001 # macro
A6XX_RB_STENCIL_INFO_UNK1 = 0x00000002 # macro
REG_A7XX_RB_STENCIL_INFO = 0x00008881 # macro
A7XX_RB_STENCIL_INFO_SEPARATE_STENCIL = 0x00000001 # macro
A7XX_RB_STENCIL_INFO_UNK1 = 0x00000002 # macro
A7XX_RB_STENCIL_INFO_TILEMODE__MASK = 0x0000000c # macro
A7XX_RB_STENCIL_INFO_TILEMODE__SHIFT = 2 # macro
REG_A6XX_RB_STENCIL_BUFFER_PITCH = 0x00008882 # macro
A6XX_RB_STENCIL_BUFFER_PITCH__MASK = 0x00000fff # macro
A6XX_RB_STENCIL_BUFFER_PITCH__SHIFT = 0 # macro
REG_A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH = 0x00008883 # macro
A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK = 0x00ffffff # macro
A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT = 0 # macro
REG_A6XX_RB_STENCIL_BUFFER_BASE = 0x00008884 # macro
REG_A6XX_RB_STENCIL_BUFFER_BASE_GMEM = 0x00008886 # macro
REG_A6XX_RB_STENCILREF = 0x00008887 # macro
A6XX_RB_STENCILREF_REF__MASK = 0x000000ff # macro
A6XX_RB_STENCILREF_REF__SHIFT = 0 # macro
A6XX_RB_STENCILREF_BFREF__MASK = 0x0000ff00 # macro
A6XX_RB_STENCILREF_BFREF__SHIFT = 8 # macro
REG_A6XX_RB_STENCILMASK = 0x00008888 # macro
A6XX_RB_STENCILMASK_MASK__MASK = 0x000000ff # macro
A6XX_RB_STENCILMASK_MASK__SHIFT = 0 # macro
A6XX_RB_STENCILMASK_BFMASK__MASK = 0x0000ff00 # macro
A6XX_RB_STENCILMASK_BFMASK__SHIFT = 8 # macro
REG_A6XX_RB_STENCILWRMASK = 0x00008889 # macro
A6XX_RB_STENCILWRMASK_WRMASK__MASK = 0x000000ff # macro
A6XX_RB_STENCILWRMASK_WRMASK__SHIFT = 0 # macro
A6XX_RB_STENCILWRMASK_BFWRMASK__MASK = 0x0000ff00 # macro
A6XX_RB_STENCILWRMASK_BFWRMASK__SHIFT = 8 # macro
REG_A6XX_RB_WINDOW_OFFSET = 0x00008890 # macro
A6XX_RB_WINDOW_OFFSET_X__MASK = 0x00003fff # macro
A6XX_RB_WINDOW_OFFSET_X__SHIFT = 0 # macro
A6XX_RB_WINDOW_OFFSET_Y__MASK = 0x3fff0000 # macro
A6XX_RB_WINDOW_OFFSET_Y__SHIFT = 16 # macro
REG_A6XX_RB_SAMPLE_COUNT_CONTROL = 0x00008891 # macro
A6XX_RB_SAMPLE_COUNT_CONTROL_DISABLE = 0x00000001 # macro
A6XX_RB_SAMPLE_COUNT_CONTROL_COPY = 0x00000002 # macro
REG_A6XX_RB_LRZ_CNTL = 0x00008898 # macro
A6XX_RB_LRZ_CNTL_ENABLE = 0x00000001 # macro
REG_A7XX_RB_UNKNOWN_8899 = 0x00008899 # macro
REG_A6XX_RB_Z_CLAMP_MIN = 0x000088c0 # macro
A6XX_RB_Z_CLAMP_MIN__MASK = 0xffffffff # macro
A6XX_RB_Z_CLAMP_MIN__SHIFT = 0 # macro
REG_A6XX_RB_Z_CLAMP_MAX = 0x000088c1 # macro
A6XX_RB_Z_CLAMP_MAX__MASK = 0xffffffff # macro
A6XX_RB_Z_CLAMP_MAX__SHIFT = 0 # macro
REG_A6XX_RB_UNKNOWN_88D0 = 0x000088d0 # macro
A6XX_RB_UNKNOWN_88D0_UNK0__MASK = 0x00001fff # macro
A6XX_RB_UNKNOWN_88D0_UNK0__SHIFT = 0 # macro
A6XX_RB_UNKNOWN_88D0_UNK16__MASK = 0x07ff0000 # macro
A6XX_RB_UNKNOWN_88D0_UNK16__SHIFT = 16 # macro
REG_A6XX_RB_BLIT_SCISSOR_TL = 0x000088d1 # macro
A6XX_RB_BLIT_SCISSOR_TL_X__MASK = 0x00003fff # macro
A6XX_RB_BLIT_SCISSOR_TL_X__SHIFT = 0 # macro
A6XX_RB_BLIT_SCISSOR_TL_Y__MASK = 0x3fff0000 # macro
A6XX_RB_BLIT_SCISSOR_TL_Y__SHIFT = 16 # macro
REG_A6XX_RB_BLIT_SCISSOR_BR = 0x000088d2 # macro
A6XX_RB_BLIT_SCISSOR_BR_X__MASK = 0x00003fff # macro
A6XX_RB_BLIT_SCISSOR_BR_X__SHIFT = 0 # macro
A6XX_RB_BLIT_SCISSOR_BR_Y__MASK = 0x3fff0000 # macro
A6XX_RB_BLIT_SCISSOR_BR_Y__SHIFT = 16 # macro
REG_A6XX_RB_BIN_CONTROL2 = 0x000088d3 # macro
A6XX_RB_BIN_CONTROL2_BINW__MASK = 0x0000003f # macro
A6XX_RB_BIN_CONTROL2_BINW__SHIFT = 0 # macro
A6XX_RB_BIN_CONTROL2_BINH__MASK = 0x00007f00 # macro
A6XX_RB_BIN_CONTROL2_BINH__SHIFT = 8 # macro
REG_A6XX_RB_WINDOW_OFFSET2 = 0x000088d4 # macro
A6XX_RB_WINDOW_OFFSET2_X__MASK = 0x00003fff # macro
A6XX_RB_WINDOW_OFFSET2_X__SHIFT = 0 # macro
A6XX_RB_WINDOW_OFFSET2_Y__MASK = 0x3fff0000 # macro
A6XX_RB_WINDOW_OFFSET2_Y__SHIFT = 16 # macro
REG_A6XX_RB_BLIT_GMEM_MSAA_CNTL = 0x000088d5 # macro
A6XX_RB_BLIT_GMEM_MSAA_CNTL_SAMPLES__MASK = 0x00000018 # macro
A6XX_RB_BLIT_GMEM_MSAA_CNTL_SAMPLES__SHIFT = 3 # macro
REG_A6XX_RB_BLIT_BASE_GMEM = 0x000088d6 # macro
REG_A6XX_RB_BLIT_DST_INFO = 0x000088d7 # macro
A6XX_RB_BLIT_DST_INFO_TILE_MODE__MASK = 0x00000003 # macro
A6XX_RB_BLIT_DST_INFO_TILE_MODE__SHIFT = 0 # macro
A6XX_RB_BLIT_DST_INFO_FLAGS = 0x00000004 # macro
A6XX_RB_BLIT_DST_INFO_SAMPLES__MASK = 0x00000018 # macro
A6XX_RB_BLIT_DST_INFO_SAMPLES__SHIFT = 3 # macro
A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__MASK = 0x00000060 # macro
A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__SHIFT = 5 # macro
A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__MASK = 0x00007f80 # macro
A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__SHIFT = 7 # macro
A6XX_RB_BLIT_DST_INFO_UNK15 = 0x00008000 # macro
REG_A6XX_RB_BLIT_DST = 0x000088d8 # macro
REG_A6XX_RB_BLIT_DST_PITCH = 0x000088da # macro
A6XX_RB_BLIT_DST_PITCH__MASK = 0x0000ffff # macro
A6XX_RB_BLIT_DST_PITCH__SHIFT = 0 # macro
REG_A6XX_RB_BLIT_DST_ARRAY_PITCH = 0x000088db # macro
A6XX_RB_BLIT_DST_ARRAY_PITCH__MASK = 0x1fffffff # macro
A6XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT = 0 # macro
REG_A6XX_RB_BLIT_FLAG_DST = 0x000088dc # macro
REG_A6XX_RB_BLIT_FLAG_DST_PITCH = 0x000088de # macro
A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__MASK = 0x000007ff # macro
A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__SHIFT = 0 # macro
A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__MASK = 0x0ffff800 # macro
A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__SHIFT = 11 # macro
REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0 = 0x000088df # macro
REG_A6XX_RB_BLIT_CLEAR_COLOR_DW1 = 0x000088e0 # macro
REG_A6XX_RB_BLIT_CLEAR_COLOR_DW2 = 0x000088e1 # macro
REG_A6XX_RB_BLIT_CLEAR_COLOR_DW3 = 0x000088e2 # macro
REG_A6XX_RB_BLIT_INFO = 0x000088e3 # macro
A6XX_RB_BLIT_INFO_UNK0 = 0x00000001 # macro
A6XX_RB_BLIT_INFO_GMEM = 0x00000002 # macro
A6XX_RB_BLIT_INFO_SAMPLE_0 = 0x00000004 # macro
A6XX_RB_BLIT_INFO_DEPTH = 0x00000008 # macro
A6XX_RB_BLIT_INFO_CLEAR_MASK__MASK = 0x000000f0 # macro
A6XX_RB_BLIT_INFO_CLEAR_MASK__SHIFT = 4 # macro
A6XX_RB_BLIT_INFO_LAST__MASK = 0x00000300 # macro
A6XX_RB_BLIT_INFO_LAST__SHIFT = 8 # macro
A6XX_RB_BLIT_INFO_BUFFER_ID__MASK = 0x0000f000 # macro
A6XX_RB_BLIT_INFO_BUFFER_ID__SHIFT = 12 # macro
REG_A7XX_RB_UNKNOWN_88E4 = 0x000088e4 # macro
A7XX_RB_UNKNOWN_88E4_UNK0 = 0x00000001 # macro
REG_A7XX_RB_CCU_CNTL2 = 0x000088e5 # macro
A7XX_RB_CCU_CNTL2_DEPTH_OFFSET_HI__MASK = 0x00000001 # macro
A7XX_RB_CCU_CNTL2_DEPTH_OFFSET_HI__SHIFT = 0 # macro
A7XX_RB_CCU_CNTL2_COLOR_OFFSET_HI__MASK = 0x00000004 # macro
A7XX_RB_CCU_CNTL2_COLOR_OFFSET_HI__SHIFT = 2 # macro
A7XX_RB_CCU_CNTL2_DEPTH_CACHE_SIZE__MASK = 0x00000c00 # macro
A7XX_RB_CCU_CNTL2_DEPTH_CACHE_SIZE__SHIFT = 10 # macro
A7XX_RB_CCU_CNTL2_DEPTH_OFFSET__MASK = 0x001ff000 # macro
A7XX_RB_CCU_CNTL2_DEPTH_OFFSET__SHIFT = 12 # macro
A7XX_RB_CCU_CNTL2_COLOR_CACHE_SIZE__MASK = 0x00600000 # macro
A7XX_RB_CCU_CNTL2_COLOR_CACHE_SIZE__SHIFT = 21 # macro
A7XX_RB_CCU_CNTL2_COLOR_OFFSET__MASK = 0xff800000 # macro
A7XX_RB_CCU_CNTL2_COLOR_OFFSET__SHIFT = 23 # macro
REG_A6XX_RB_UNKNOWN_88F0 = 0x000088f0 # macro
REG_A6XX_RB_UNK_FLAG_BUFFER_BASE = 0x000088f1 # macro
REG_A6XX_RB_UNK_FLAG_BUFFER_PITCH = 0x000088f3 # macro
A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__MASK = 0x000007ff # macro
A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__SHIFT = 0 # macro
A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK = 0x00fff800 # macro
A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT = 11 # macro
REG_A6XX_RB_UNKNOWN_88F4 = 0x000088f4 # macro
REG_A7XX_RB_UNKNOWN_88F5 = 0x000088f5 # macro
REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE = 0x00008900 # macro
REG_A6XX_RB_DEPTH_FLAG_BUFFER_PITCH = 0x00008902 # macro
A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__MASK = 0x0000007f # macro
A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__SHIFT = 0 # macro
A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__MASK = 0x00000700 # macro
A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__SHIFT = 8 # macro
A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK = 0x0ffff800 # macro
A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT = 11 # macro
# def REG_A6XX_RB_MRT_FLAG_BUFFER(i0): # macro
# return (0x00008903+0x3*i0)
A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__MASK = 0x000007ff # macro
A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__SHIFT = 0 # macro
A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK = 0x1ffff800 # macro
A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT = 11 # macro
REG_A6XX_RB_SAMPLE_COUNT_ADDR = 0x00008927 # macro
REG_A6XX_RB_UNKNOWN_8A00 = 0x00008a00 # macro
REG_A6XX_RB_UNKNOWN_8A10 = 0x00008a10 # macro
REG_A6XX_RB_UNKNOWN_8A20 = 0x00008a20 # macro
REG_A6XX_RB_UNKNOWN_8A30 = 0x00008a30 # macro
REG_A6XX_RB_2D_BLIT_CNTL = 0x00008c00 # macro
A6XX_RB_2D_BLIT_CNTL_ROTATE__MASK = 0x00000007 # macro
A6XX_RB_2D_BLIT_CNTL_ROTATE__SHIFT = 0 # macro
A6XX_RB_2D_BLIT_CNTL_OVERWRITEEN = 0x00000008 # macro
A6XX_RB_2D_BLIT_CNTL_UNK4__MASK = 0x00000070 # macro
A6XX_RB_2D_BLIT_CNTL_UNK4__SHIFT = 4 # macro
A6XX_RB_2D_BLIT_CNTL_SOLID_COLOR = 0x00000080 # macro
A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__MASK = 0x0000ff00 # macro
A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT = 8 # macro
A6XX_RB_2D_BLIT_CNTL_SCISSOR = 0x00010000 # macro
A6XX_RB_2D_BLIT_CNTL_UNK17__MASK = 0x00060000 # macro
A6XX_RB_2D_BLIT_CNTL_UNK17__SHIFT = 17 # macro
A6XX_RB_2D_BLIT_CNTL_D24S8 = 0x00080000 # macro
A6XX_RB_2D_BLIT_CNTL_MASK__MASK = 0x00f00000 # macro
A6XX_RB_2D_BLIT_CNTL_MASK__SHIFT = 20 # macro
A6XX_RB_2D_BLIT_CNTL_IFMT__MASK = 0x1f000000 # macro
A6XX_RB_2D_BLIT_CNTL_IFMT__SHIFT = 24 # macro
A6XX_RB_2D_BLIT_CNTL_RASTER_MODE__MASK = 0x20000000 # macro
A6XX_RB_2D_BLIT_CNTL_RASTER_MODE__SHIFT = 29 # macro
A6XX_RB_2D_BLIT_CNTL_UNK30 = 0x40000000 # macro
REG_A6XX_RB_2D_UNKNOWN_8C01 = 0x00008c01 # macro
REG_A6XX_RB_2D_DST_INFO = 0x00008c17 # macro
A6XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK = 0x000000ff # macro
A6XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT = 0 # macro
A6XX_RB_2D_DST_INFO_TILE_MODE__MASK = 0x00000300 # macro
A6XX_RB_2D_DST_INFO_TILE_MODE__SHIFT = 8 # macro
A6XX_RB_2D_DST_INFO_COLOR_SWAP__MASK = 0x00000c00 # macro
A6XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT = 10 # macro
A6XX_RB_2D_DST_INFO_FLAGS = 0x00001000 # macro
A6XX_RB_2D_DST_INFO_SRGB = 0x00002000 # macro
A6XX_RB_2D_DST_INFO_SAMPLES__MASK = 0x0000c000 # macro
A6XX_RB_2D_DST_INFO_SAMPLES__SHIFT = 14 # macro
A6XX_RB_2D_DST_INFO_FILTER = 0x00010000 # macro
A6XX_RB_2D_DST_INFO_UNK17 = 0x00020000 # macro
A6XX_RB_2D_DST_INFO_SAMPLES_AVERAGE = 0x00040000 # macro
A6XX_RB_2D_DST_INFO_UNK19 = 0x00080000 # macro
A6XX_RB_2D_DST_INFO_UNK20 = 0x00100000 # macro
A6XX_RB_2D_DST_INFO_UNK21 = 0x00200000 # macro
A6XX_RB_2D_DST_INFO_UNK22 = 0x00400000 # macro
A6XX_RB_2D_DST_INFO_UNK23__MASK = 0x07800000 # macro
A6XX_RB_2D_DST_INFO_UNK23__SHIFT = 23 # macro
A6XX_RB_2D_DST_INFO_UNK28 = 0x10000000 # macro
REG_A6XX_RB_2D_DST = 0x00008c18 # macro
REG_A6XX_RB_2D_DST_PITCH = 0x00008c1a # macro
A6XX_RB_2D_DST_PITCH__MASK = 0x0000ffff # macro
A6XX_RB_2D_DST_PITCH__SHIFT = 0 # macro
REG_A6XX_RB_2D_DST_PLANE1 = 0x00008c1b # macro
REG_A6XX_RB_2D_DST_PLANE_PITCH = 0x00008c1d # macro
A6XX_RB_2D_DST_PLANE_PITCH__MASK = 0x0000ffff # macro
A6XX_RB_2D_DST_PLANE_PITCH__SHIFT = 0 # macro
REG_A6XX_RB_2D_DST_PLANE2 = 0x00008c1e # macro
REG_A6XX_RB_2D_DST_FLAGS = 0x00008c20 # macro
REG_A6XX_RB_2D_DST_FLAGS_PITCH = 0x00008c22 # macro
A6XX_RB_2D_DST_FLAGS_PITCH__MASK = 0x000000ff # macro
A6XX_RB_2D_DST_FLAGS_PITCH__SHIFT = 0 # macro
REG_A6XX_RB_2D_DST_FLAGS_PLANE = 0x00008c23 # macro
REG_A6XX_RB_2D_DST_FLAGS_PLANE_PITCH = 0x00008c25 # macro
A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__MASK = 0x000000ff # macro
A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__SHIFT = 0 # macro
REG_A6XX_RB_2D_SRC_SOLID_C0 = 0x00008c2c # macro
REG_A6XX_RB_2D_SRC_SOLID_C1 = 0x00008c2d # macro
REG_A6XX_RB_2D_SRC_SOLID_C2 = 0x00008c2e # macro
REG_A6XX_RB_2D_SRC_SOLID_C3 = 0x00008c2f # macro
REG_A7XX_RB_UNKNOWN_8C34 = 0x00008c34 # macro
REG_A6XX_RB_UNKNOWN_8E01 = 0x00008e01 # macro
REG_A6XX_RB_DBG_ECO_CNTL = 0x00008e04 # macro
REG_A6XX_RB_ADDR_MODE_CNTL = 0x00008e05 # macro
REG_A7XX_RB_UNKNOWN_8E06 = 0x00008e06 # macro
REG_A6XX_RB_CCU_CNTL = 0x00008e07 # macro
A6XX_RB_CCU_CNTL_GMEM_FAST_CLEAR_DISABLE = 0x00000001 # macro
A6XX_RB_CCU_CNTL_CONCURRENT_RESOLVE = 0x00000004 # macro
A6XX_RB_CCU_CNTL_DEPTH_OFFSET_HI__MASK = 0x00000080 # macro
A6XX_RB_CCU_CNTL_DEPTH_OFFSET_HI__SHIFT = 7 # macro
A6XX_RB_CCU_CNTL_COLOR_OFFSET_HI__MASK = 0x00000200 # macro
A6XX_RB_CCU_CNTL_COLOR_OFFSET_HI__SHIFT = 9 # macro
A6XX_RB_CCU_CNTL_DEPTH_CACHE_SIZE__MASK = 0x00000c00 # macro
A6XX_RB_CCU_CNTL_DEPTH_CACHE_SIZE__SHIFT = 10 # macro
A6XX_RB_CCU_CNTL_DEPTH_OFFSET__MASK = 0x001ff000 # macro
A6XX_RB_CCU_CNTL_DEPTH_OFFSET__SHIFT = 12 # macro
A6XX_RB_CCU_CNTL_COLOR_CACHE_SIZE__MASK = 0x00600000 # macro
A6XX_RB_CCU_CNTL_COLOR_CACHE_SIZE__SHIFT = 21 # macro
A6XX_RB_CCU_CNTL_COLOR_OFFSET__MASK = 0xff800000 # macro
A6XX_RB_CCU_CNTL_COLOR_OFFSET__SHIFT = 23 # macro
REG_A7XX_RB_CCU_CNTL = 0x00008e07 # macro
A7XX_RB_CCU_CNTL_GMEM_FAST_CLEAR_DISABLE = 0x00000001 # macro
A7XX_RB_CCU_CNTL_CONCURRENT_RESOLVE = 0x00000004 # macro
REG_A6XX_RB_NC_MODE_CNTL = 0x00008e08 # macro
A6XX_RB_NC_MODE_CNTL_MODE = 0x00000001 # macro
A6XX_RB_NC_MODE_CNTL_LOWER_BIT__MASK = 0x00000006 # macro
A6XX_RB_NC_MODE_CNTL_LOWER_BIT__SHIFT = 1 # macro
A6XX_RB_NC_MODE_CNTL_MIN_ACCESS_LENGTH = 0x00000008 # macro
A6XX_RB_NC_MODE_CNTL_AMSBC = 0x00000010 # macro
A6XX_RB_NC_MODE_CNTL_UPPER_BIT__MASK = 0x00000400 # macro
A6XX_RB_NC_MODE_CNTL_UPPER_BIT__SHIFT = 10 # macro
A6XX_RB_NC_MODE_CNTL_RGB565_PREDICATOR = 0x00000800 # macro
A6XX_RB_NC_MODE_CNTL_UNK12__MASK = 0x00003000 # macro
A6XX_RB_NC_MODE_CNTL_UNK12__SHIFT = 12 # macro
REG_A7XX_RB_UNKNOWN_8E09 = 0x00008e09 # macro
# def REG_A6XX_RB_PERFCTR_RB_SEL(i0): # macro
# return (0x00008e10+0x1*i0)
# def REG_A6XX_RB_PERFCTR_CCU_SEL(i0): # macro
# return (0x00008e18+0x1*i0)
REG_A6XX_RB_CMP_DBG_ECO_CNTL = 0x00008e28 # macro
# def REG_A6XX_RB_PERFCTR_CMP_SEL(i0): # macro
# return (0x00008e2c+0x1*i0)
# def REG_A7XX_RB_PERFCTR_UFC_SEL(i0): # macro
# return (0x00008e30+0x1*i0)
REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST = 0x00008e3b # macro
REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD = 0x00008e3d # macro
REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE = 0x00008e50 # macro
REG_A6XX_RB_UNKNOWN_8E51 = 0x00008e51 # macro
REG_A7XX_RB_UNKNOWN_8E79 = 0x00008e79 # macro
REG_A6XX_VPC_GS_PARAM = 0x00009100 # macro
A6XX_VPC_GS_PARAM_LINELENGTHLOC__MASK = 0x000000ff # macro
A6XX_VPC_GS_PARAM_LINELENGTHLOC__SHIFT = 0 # macro
REG_A6XX_VPC_VS_CLIP_CNTL = 0x00009101 # macro
A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__MASK = 0x000000ff # macro
A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__SHIFT = 0 # macro
A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK = 0x0000ff00 # macro
A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT = 8 # macro
A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK = 0x00ff0000 # macro
A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT = 16 # macro
REG_A6XX_VPC_GS_CLIP_CNTL = 0x00009102 # macro
A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__MASK = 0x000000ff # macro
A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__SHIFT = 0 # macro
A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK = 0x0000ff00 # macro
A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT = 8 # macro
A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK = 0x00ff0000 # macro
A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT = 16 # macro
REG_A6XX_VPC_DS_CLIP_CNTL = 0x00009103 # macro
A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__MASK = 0x000000ff # macro
A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__SHIFT = 0 # macro
A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK = 0x0000ff00 # macro
A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT = 8 # macro
A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK = 0x00ff0000 # macro
A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT = 16 # macro
REG_A6XX_VPC_VS_CLIP_CNTL_V2 = 0x00009311 # macro
A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_MASK__MASK = 0x000000ff # macro
A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_MASK__SHIFT = 0 # macro
A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__MASK = 0x0000ff00 # macro
A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__SHIFT = 8 # macro
A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__MASK = 0x00ff0000 # macro
A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__SHIFT = 16 # macro
REG_A6XX_VPC_GS_CLIP_CNTL_V2 = 0x00009312 # macro
A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_MASK__MASK = 0x000000ff # macro
A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_MASK__SHIFT = 0 # macro
A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__MASK = 0x0000ff00 # macro
A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__SHIFT = 8 # macro
A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__MASK = 0x00ff0000 # macro
A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__SHIFT = 16 # macro
REG_A6XX_VPC_DS_CLIP_CNTL_V2 = 0x00009313 # macro
A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_MASK__MASK = 0x000000ff # macro
A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_MASK__SHIFT = 0 # macro
A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__MASK = 0x0000ff00 # macro
A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__SHIFT = 8 # macro
A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__MASK = 0x00ff0000 # macro
A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__SHIFT = 16 # macro
REG_A6XX_VPC_VS_LAYER_CNTL = 0x00009104 # macro
A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__MASK = 0x000000ff # macro
A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__SHIFT = 0 # macro
A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__MASK = 0x0000ff00 # macro
A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__SHIFT = 8 # macro
A6XX_VPC_VS_LAYER_CNTL_SHADINGRATELOC__MASK = 0x00ff0000 # macro
A6XX_VPC_VS_LAYER_CNTL_SHADINGRATELOC__SHIFT = 16 # macro
REG_A6XX_VPC_GS_LAYER_CNTL = 0x00009105 # macro
A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__MASK = 0x000000ff # macro
A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__SHIFT = 0 # macro
A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__MASK = 0x0000ff00 # macro
A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__SHIFT = 8 # macro
A6XX_VPC_GS_LAYER_CNTL_SHADINGRATELOC__MASK = 0x00ff0000 # macro
A6XX_VPC_GS_LAYER_CNTL_SHADINGRATELOC__SHIFT = 16 # macro
REG_A6XX_VPC_DS_LAYER_CNTL = 0x00009106 # macro
A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__MASK = 0x000000ff # macro
A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__SHIFT = 0 # macro
A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__MASK = 0x0000ff00 # macro
A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__SHIFT = 8 # macro
A6XX_VPC_DS_LAYER_CNTL_SHADINGRATELOC__MASK = 0x00ff0000 # macro
A6XX_VPC_DS_LAYER_CNTL_SHADINGRATELOC__SHIFT = 16 # macro
REG_A6XX_VPC_VS_LAYER_CNTL_V2 = 0x00009314 # macro
A6XX_VPC_VS_LAYER_CNTL_V2_LAYERLOC__MASK = 0x000000ff # macro
A6XX_VPC_VS_LAYER_CNTL_V2_LAYERLOC__SHIFT = 0 # macro
A6XX_VPC_VS_LAYER_CNTL_V2_VIEWLOC__MASK = 0x0000ff00 # macro
A6XX_VPC_VS_LAYER_CNTL_V2_VIEWLOC__SHIFT = 8 # macro
A6XX_VPC_VS_LAYER_CNTL_V2_SHADINGRATELOC__MASK = 0x00ff0000 # macro
A6XX_VPC_VS_LAYER_CNTL_V2_SHADINGRATELOC__SHIFT = 16 # macro
REG_A6XX_VPC_GS_LAYER_CNTL_V2 = 0x00009315 # macro
A6XX_VPC_GS_LAYER_CNTL_V2_LAYERLOC__MASK = 0x000000ff # macro
A6XX_VPC_GS_LAYER_CNTL_V2_LAYERLOC__SHIFT = 0 # macro
A6XX_VPC_GS_LAYER_CNTL_V2_VIEWLOC__MASK = 0x0000ff00 # macro
A6XX_VPC_GS_LAYER_CNTL_V2_VIEWLOC__SHIFT = 8 # macro
A6XX_VPC_GS_LAYER_CNTL_V2_SHADINGRATELOC__MASK = 0x00ff0000 # macro
A6XX_VPC_GS_LAYER_CNTL_V2_SHADINGRATELOC__SHIFT = 16 # macro
REG_A6XX_VPC_DS_LAYER_CNTL_V2 = 0x00009316 # macro
A6XX_VPC_DS_LAYER_CNTL_V2_LAYERLOC__MASK = 0x000000ff # macro
A6XX_VPC_DS_LAYER_CNTL_V2_LAYERLOC__SHIFT = 0 # macro
A6XX_VPC_DS_LAYER_CNTL_V2_VIEWLOC__MASK = 0x0000ff00 # macro
A6XX_VPC_DS_LAYER_CNTL_V2_VIEWLOC__SHIFT = 8 # macro
A6XX_VPC_DS_LAYER_CNTL_V2_SHADINGRATELOC__MASK = 0x00ff0000 # macro
A6XX_VPC_DS_LAYER_CNTL_V2_SHADINGRATELOC__SHIFT = 16 # macro
REG_A6XX_VPC_UNKNOWN_9107 = 0x00009107 # macro
A6XX_VPC_UNKNOWN_9107_RASTER_DISCARD = 0x00000001 # macro
A6XX_VPC_UNKNOWN_9107_UNK2 = 0x00000004 # macro
REG_A6XX_VPC_POLYGON_MODE = 0x00009108 # macro
A6XX_VPC_POLYGON_MODE_MODE__MASK = 0x00000003 # macro
A6XX_VPC_POLYGON_MODE_MODE__SHIFT = 0 # macro
REG_A7XX_VPC_PRIMITIVE_CNTL_0 = 0x00009109 # macro
A7XX_VPC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART = 0x00000001 # macro
A7XX_VPC_PRIMITIVE_CNTL_0_PROVOKING_VTX_LAST = 0x00000002 # macro
A7XX_VPC_PRIMITIVE_CNTL_0_D3D_VERTEX_ORDERING = 0x00000004 # macro
A7XX_VPC_PRIMITIVE_CNTL_0_UNK3 = 0x00000008 # macro
REG_A7XX_VPC_PRIMITIVE_CNTL_5 = 0x0000910a # macro
A7XX_VPC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__MASK = 0x000000ff # macro
A7XX_VPC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__SHIFT = 0 # macro
A7XX_VPC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__MASK = 0x00007c00 # macro
A7XX_VPC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__SHIFT = 10 # macro
A7XX_VPC_PRIMITIVE_CNTL_5_LINELENGTHEN = 0x00008000 # macro
A7XX_VPC_PRIMITIVE_CNTL_5_GS_OUTPUT__MASK = 0x00030000 # macro
A7XX_VPC_PRIMITIVE_CNTL_5_GS_OUTPUT__SHIFT = 16 # macro
A7XX_VPC_PRIMITIVE_CNTL_5_UNK18 = 0x00040000 # macro
REG_A7XX_VPC_MULTIVIEW_MASK = 0x0000910b # macro
REG_A7XX_VPC_MULTIVIEW_CNTL = 0x0000910c # macro
A7XX_VPC_MULTIVIEW_CNTL_ENABLE = 0x00000001 # macro
A7XX_VPC_MULTIVIEW_CNTL_DISABLEMULTIPOS = 0x00000002 # macro
A7XX_VPC_MULTIVIEW_CNTL_VIEWS__MASK = 0x0000007c # macro
A7XX_VPC_MULTIVIEW_CNTL_VIEWS__SHIFT = 2 # macro
# def REG_A6XX_VPC_VARYING_INTERP(i0): # macro
# return (0x00009200+0x1*i0)
# def REG_A6XX_VPC_VARYING_PS_REPL(i0): # macro
# return (0x00009208+0x1*i0)
REG_A6XX_VPC_UNKNOWN_9210 = 0x00009210 # macro
REG_A6XX_VPC_UNKNOWN_9211 = 0x00009211 # macro
# def REG_A6XX_VPC_VAR(i0): # macro
# return (0x00009212+0x1*i0)
REG_A6XX_VPC_SO_CNTL = 0x00009216 # macro
A6XX_VPC_SO_CNTL_ADDR__MASK = 0x000000ff # macro
A6XX_VPC_SO_CNTL_ADDR__SHIFT = 0 # macro
A6XX_VPC_SO_CNTL_RESET = 0x00010000 # macro
REG_A6XX_VPC_SO_PROG = 0x00009217 # macro
A6XX_VPC_SO_PROG_A_BUF__MASK = 0x00000003 # macro
A6XX_VPC_SO_PROG_A_BUF__SHIFT = 0 # macro
A6XX_VPC_SO_PROG_A_OFF__MASK = 0x000007fc # macro
A6XX_VPC_SO_PROG_A_OFF__SHIFT = 2 # macro
A6XX_VPC_SO_PROG_A_EN = 0x00000800 # macro
A6XX_VPC_SO_PROG_B_BUF__MASK = 0x00003000 # macro
A6XX_VPC_SO_PROG_B_BUF__SHIFT = 12 # macro
A6XX_VPC_SO_PROG_B_OFF__MASK = 0x007fc000 # macro
A6XX_VPC_SO_PROG_B_OFF__SHIFT = 14 # macro
A6XX_VPC_SO_PROG_B_EN = 0x00800000 # macro
REG_A6XX_VPC_SO_STREAM_COUNTS = 0x00009218 # macro
# def REG_A6XX_VPC_SO(i0): # macro
# return (0x0000921a+0x7*i0)
REG_A6XX_VPC_POINT_COORD_INVERT = 0x00009236 # macro
A6XX_VPC_POINT_COORD_INVERT_INVERT = 0x00000001 # macro
REG_A6XX_VPC_UNKNOWN_9300 = 0x00009300 # macro
REG_A6XX_VPC_VS_PACK = 0x00009301 # macro
A6XX_VPC_VS_PACK_STRIDE_IN_VPC__MASK = 0x000000ff # macro
A6XX_VPC_VS_PACK_STRIDE_IN_VPC__SHIFT = 0 # macro
A6XX_VPC_VS_PACK_POSITIONLOC__MASK = 0x0000ff00 # macro
A6XX_VPC_VS_PACK_POSITIONLOC__SHIFT = 8 # macro
A6XX_VPC_VS_PACK_PSIZELOC__MASK = 0x00ff0000 # macro
A6XX_VPC_VS_PACK_PSIZELOC__SHIFT = 16 # macro
A6XX_VPC_VS_PACK_EXTRAPOS__MASK = 0x0f000000 # macro
A6XX_VPC_VS_PACK_EXTRAPOS__SHIFT = 24 # macro
REG_A6XX_VPC_GS_PACK = 0x00009302 # macro
A6XX_VPC_GS_PACK_STRIDE_IN_VPC__MASK = 0x000000ff # macro
A6XX_VPC_GS_PACK_STRIDE_IN_VPC__SHIFT = 0 # macro
A6XX_VPC_GS_PACK_POSITIONLOC__MASK = 0x0000ff00 # macro
A6XX_VPC_GS_PACK_POSITIONLOC__SHIFT = 8 # macro
A6XX_VPC_GS_PACK_PSIZELOC__MASK = 0x00ff0000 # macro
A6XX_VPC_GS_PACK_PSIZELOC__SHIFT = 16 # macro
A6XX_VPC_GS_PACK_EXTRAPOS__MASK = 0x0f000000 # macro
A6XX_VPC_GS_PACK_EXTRAPOS__SHIFT = 24 # macro
REG_A6XX_VPC_DS_PACK = 0x00009303 # macro
A6XX_VPC_DS_PACK_STRIDE_IN_VPC__MASK = 0x000000ff # macro
A6XX_VPC_DS_PACK_STRIDE_IN_VPC__SHIFT = 0 # macro
A6XX_VPC_DS_PACK_POSITIONLOC__MASK = 0x0000ff00 # macro
A6XX_VPC_DS_PACK_POSITIONLOC__SHIFT = 8 # macro
A6XX_VPC_DS_PACK_PSIZELOC__MASK = 0x00ff0000 # macro
A6XX_VPC_DS_PACK_PSIZELOC__SHIFT = 16 # macro
A6XX_VPC_DS_PACK_EXTRAPOS__MASK = 0x0f000000 # macro
A6XX_VPC_DS_PACK_EXTRAPOS__SHIFT = 24 # macro
REG_A6XX_VPC_CNTL_0 = 0x00009304 # macro
A6XX_VPC_CNTL_0_NUMNONPOSVAR__MASK = 0x000000ff # macro
A6XX_VPC_CNTL_0_NUMNONPOSVAR__SHIFT = 0 # macro
A6XX_VPC_CNTL_0_PRIMIDLOC__MASK = 0x0000ff00 # macro
A6XX_VPC_CNTL_0_PRIMIDLOC__SHIFT = 8 # macro
A6XX_VPC_CNTL_0_VARYING = 0x00010000 # macro
A6XX_VPC_CNTL_0_VIEWIDLOC__MASK = 0xff000000 # macro
A6XX_VPC_CNTL_0_VIEWIDLOC__SHIFT = 24 # macro
REG_A6XX_VPC_SO_STREAM_CNTL = 0x00009305 # macro
A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__MASK = 0x00000007 # macro
A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__SHIFT = 0 # macro
A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__MASK = 0x00000038 # macro
A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__SHIFT = 3 # macro
A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__MASK = 0x000001c0 # macro
A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__SHIFT = 6 # macro
A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__MASK = 0x00000e00 # macro
A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__SHIFT = 9 # macro
A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__MASK = 0x00078000 # macro
A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__SHIFT = 15 # macro
REG_A6XX_VPC_SO_DISABLE = 0x00009306 # macro
A6XX_VPC_SO_DISABLE_DISABLE = 0x00000001 # macro
REG_A7XX_VPC_POLYGON_MODE2 = 0x00009307 # macro
A7XX_VPC_POLYGON_MODE2_MODE__MASK = 0x00000003 # macro
A7XX_VPC_POLYGON_MODE2_MODE__SHIFT = 0 # macro
REG_A7XX_VPC_ATTR_BUF_SIZE_GMEM = 0x00009308 # macro
A7XX_VPC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__MASK = 0xffffffff # macro
A7XX_VPC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__SHIFT = 0 # macro
REG_A7XX_VPC_ATTR_BUF_BASE_GMEM = 0x00009309 # macro
A7XX_VPC_ATTR_BUF_BASE_GMEM_BASE_GMEM__MASK = 0xffffffff # macro
A7XX_VPC_ATTR_BUF_BASE_GMEM_BASE_GMEM__SHIFT = 0 # macro
REG_A7XX_PC_ATTR_BUF_SIZE_GMEM = 0x00009b09 # macro
A7XX_PC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__MASK = 0xffffffff # macro
A7XX_PC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__SHIFT = 0 # macro
REG_A6XX_VPC_DBG_ECO_CNTL = 0x00009600 # macro
REG_A6XX_VPC_ADDR_MODE_CNTL = 0x00009601 # macro
REG_A6XX_VPC_UNKNOWN_9602 = 0x00009602 # macro
REG_A6XX_VPC_UNKNOWN_9603 = 0x00009603 # macro
# def REG_A6XX_VPC_PERFCTR_VPC_SEL(i0): # macro
# return (0x00009604+0x1*i0)
# def REG_A7XX_VPC_PERFCTR_VPC_SEL(i0): # macro
# return (0x0000960b+0x1*i0)
REG_A6XX_PC_TESS_NUM_VERTEX = 0x00009800 # macro
REG_A6XX_PC_HS_INPUT_SIZE = 0x00009801 # macro
A6XX_PC_HS_INPUT_SIZE_SIZE__MASK = 0x000007ff # macro
A6XX_PC_HS_INPUT_SIZE_SIZE__SHIFT = 0 # macro
A6XX_PC_HS_INPUT_SIZE_UNK13 = 0x00002000 # macro
REG_A6XX_PC_TESS_CNTL = 0x00009802 # macro
A6XX_PC_TESS_CNTL_SPACING__MASK = 0x00000003 # macro
A6XX_PC_TESS_CNTL_SPACING__SHIFT = 0 # macro
A6XX_PC_TESS_CNTL_OUTPUT__MASK = 0x0000000c # macro
A6XX_PC_TESS_CNTL_OUTPUT__SHIFT = 2 # macro
REG_A6XX_PC_RESTART_INDEX = 0x00009803 # macro
REG_A6XX_PC_MODE_CNTL = 0x00009804 # macro
REG_A6XX_PC_POWER_CNTL = 0x00009805 # macro
REG_A6XX_PC_PS_CNTL = 0x00009806 # macro
A6XX_PC_PS_CNTL_PRIMITIVEIDEN = 0x00000001 # macro
REG_A6XX_PC_SO_STREAM_CNTL = 0x00009808 # macro
A6XX_PC_SO_STREAM_CNTL_STREAM_ENABLE__MASK = 0x00078000 # macro
A6XX_PC_SO_STREAM_CNTL_STREAM_ENABLE__SHIFT = 15 # macro
REG_A6XX_PC_DGEN_SU_CONSERVATIVE_RAS_CNTL = 0x0000980a # macro
A6XX_PC_DGEN_SU_CONSERVATIVE_RAS_CNTL_CONSERVATIVERASEN = 0x00000001 # macro
REG_A6XX_PC_DRAW_CMD = 0x00009840 # macro
A6XX_PC_DRAW_CMD_STATE_ID__MASK = 0x000000ff # macro
A6XX_PC_DRAW_CMD_STATE_ID__SHIFT = 0 # macro
REG_A6XX_PC_DISPATCH_CMD = 0x00009841 # macro
A6XX_PC_DISPATCH_CMD_STATE_ID__MASK = 0x000000ff # macro
A6XX_PC_DISPATCH_CMD_STATE_ID__SHIFT = 0 # macro
REG_A6XX_PC_EVENT_CMD = 0x00009842 # macro
A6XX_PC_EVENT_CMD_STATE_ID__MASK = 0x00ff0000 # macro
A6XX_PC_EVENT_CMD_STATE_ID__SHIFT = 16 # macro
A6XX_PC_EVENT_CMD_EVENT__MASK = 0x0000007f # macro
A6XX_PC_EVENT_CMD_EVENT__SHIFT = 0 # macro
REG_A6XX_PC_MARKER = 0x00009880 # macro
REG_A6XX_PC_POLYGON_MODE = 0x00009981 # macro
A6XX_PC_POLYGON_MODE_MODE__MASK = 0x00000003 # macro
A6XX_PC_POLYGON_MODE_MODE__SHIFT = 0 # macro
REG_A7XX_PC_POLYGON_MODE = 0x00009809 # macro
A7XX_PC_POLYGON_MODE_MODE__MASK = 0x00000003 # macro
A7XX_PC_POLYGON_MODE_MODE__SHIFT = 0 # macro
REG_A6XX_PC_RASTER_CNTL = 0x00009980 # macro
A6XX_PC_RASTER_CNTL_STREAM__MASK = 0x00000003 # macro
A6XX_PC_RASTER_CNTL_STREAM__SHIFT = 0 # macro
A6XX_PC_RASTER_CNTL_DISCARD = 0x00000004 # macro
REG_A7XX_PC_RASTER_CNTL = 0x00009107 # macro
A7XX_PC_RASTER_CNTL_STREAM__MASK = 0x00000003 # macro
A7XX_PC_RASTER_CNTL_STREAM__SHIFT = 0 # macro
A7XX_PC_RASTER_CNTL_DISCARD = 0x00000004 # macro
REG_A7XX_PC_RASTER_CNTL_V2 = 0x00009317 # macro
A7XX_PC_RASTER_CNTL_V2_STREAM__MASK = 0x00000003 # macro
A7XX_PC_RASTER_CNTL_V2_STREAM__SHIFT = 0 # macro
A7XX_PC_RASTER_CNTL_V2_DISCARD = 0x00000004 # macro
REG_A7XX_PC_TESS_PARAM_SIZE = 0x00009885 # macro
REG_A7XX_PC_TESS_FACTOR_SIZE = 0x00009886 # macro
REG_A6XX_PC_PRIMITIVE_CNTL_0 = 0x00009b00 # macro
A6XX_PC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART = 0x00000001 # macro
A6XX_PC_PRIMITIVE_CNTL_0_PROVOKING_VTX_LAST = 0x00000002 # macro
A6XX_PC_PRIMITIVE_CNTL_0_D3D_VERTEX_ORDERING = 0x00000004 # macro
A6XX_PC_PRIMITIVE_CNTL_0_UNK3 = 0x00000008 # macro
REG_A6XX_PC_VS_OUT_CNTL = 0x00009b01 # macro
A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__MASK = 0x000000ff # macro
A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__SHIFT = 0 # macro
A6XX_PC_VS_OUT_CNTL_PSIZE = 0x00000100 # macro
A6XX_PC_VS_OUT_CNTL_LAYER = 0x00000200 # macro
A6XX_PC_VS_OUT_CNTL_VIEW = 0x00000400 # macro
A6XX_PC_VS_OUT_CNTL_PRIMITIVE_ID = 0x00000800 # macro
A6XX_PC_VS_OUT_CNTL_CLIP_MASK__MASK = 0x00ff0000 # macro
A6XX_PC_VS_OUT_CNTL_CLIP_MASK__SHIFT = 16 # macro
A6XX_PC_VS_OUT_CNTL_SHADINGRATE = 0x01000000 # macro
REG_A6XX_PC_GS_OUT_CNTL = 0x00009b02 # macro
A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__MASK = 0x000000ff # macro
A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__SHIFT = 0 # macro
A6XX_PC_GS_OUT_CNTL_PSIZE = 0x00000100 # macro
A6XX_PC_GS_OUT_CNTL_LAYER = 0x00000200 # macro
A6XX_PC_GS_OUT_CNTL_VIEW = 0x00000400 # macro
A6XX_PC_GS_OUT_CNTL_PRIMITIVE_ID = 0x00000800 # macro
A6XX_PC_GS_OUT_CNTL_CLIP_MASK__MASK = 0x00ff0000 # macro
A6XX_PC_GS_OUT_CNTL_CLIP_MASK__SHIFT = 16 # macro
A6XX_PC_GS_OUT_CNTL_SHADINGRATE = 0x01000000 # macro
REG_A6XX_PC_HS_OUT_CNTL = 0x00009b03 # macro
A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC__MASK = 0x000000ff # macro
A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC__SHIFT = 0 # macro
A6XX_PC_HS_OUT_CNTL_PSIZE = 0x00000100 # macro
A6XX_PC_HS_OUT_CNTL_LAYER = 0x00000200 # macro
A6XX_PC_HS_OUT_CNTL_VIEW = 0x00000400 # macro
A6XX_PC_HS_OUT_CNTL_PRIMITIVE_ID = 0x00000800 # macro
A6XX_PC_HS_OUT_CNTL_CLIP_MASK__MASK = 0x00ff0000 # macro
A6XX_PC_HS_OUT_CNTL_CLIP_MASK__SHIFT = 16 # macro
A6XX_PC_HS_OUT_CNTL_SHADINGRATE = 0x01000000 # macro
REG_A6XX_PC_DS_OUT_CNTL = 0x00009b04 # macro
A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__MASK = 0x000000ff # macro
A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__SHIFT = 0 # macro
A6XX_PC_DS_OUT_CNTL_PSIZE = 0x00000100 # macro
A6XX_PC_DS_OUT_CNTL_LAYER = 0x00000200 # macro
A6XX_PC_DS_OUT_CNTL_VIEW = 0x00000400 # macro
A6XX_PC_DS_OUT_CNTL_PRIMITIVE_ID = 0x00000800 # macro
A6XX_PC_DS_OUT_CNTL_CLIP_MASK__MASK = 0x00ff0000 # macro
A6XX_PC_DS_OUT_CNTL_CLIP_MASK__SHIFT = 16 # macro
A6XX_PC_DS_OUT_CNTL_SHADINGRATE = 0x01000000 # macro
REG_A6XX_PC_PRIMITIVE_CNTL_5 = 0x00009b05 # macro
A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__MASK = 0x000000ff # macro
A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__SHIFT = 0 # macro
A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__MASK = 0x00007c00 # macro
A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__SHIFT = 10 # macro
A6XX_PC_PRIMITIVE_CNTL_5_LINELENGTHEN = 0x00008000 # macro
A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__MASK = 0x00030000 # macro
A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__SHIFT = 16 # macro
A6XX_PC_PRIMITIVE_CNTL_5_UNK18 = 0x00040000 # macro
REG_A6XX_PC_PRIMITIVE_CNTL_6 = 0x00009b06 # macro
A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__MASK = 0x000007ff # macro
A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__SHIFT = 0 # macro
REG_A6XX_PC_MULTIVIEW_CNTL = 0x00009b07 # macro
A6XX_PC_MULTIVIEW_CNTL_ENABLE = 0x00000001 # macro
A6XX_PC_MULTIVIEW_CNTL_DISABLEMULTIPOS = 0x00000002 # macro
A6XX_PC_MULTIVIEW_CNTL_VIEWS__MASK = 0x0000007c # macro
A6XX_PC_MULTIVIEW_CNTL_VIEWS__SHIFT = 2 # macro
REG_A6XX_PC_MULTIVIEW_MASK = 0x00009b08 # macro
REG_A6XX_PC_2D_EVENT_CMD = 0x00009c00 # macro
A6XX_PC_2D_EVENT_CMD_EVENT__MASK = 0x0000007f # macro
A6XX_PC_2D_EVENT_CMD_EVENT__SHIFT = 0 # macro
A6XX_PC_2D_EVENT_CMD_STATE_ID__MASK = 0x0000ff00 # macro
A6XX_PC_2D_EVENT_CMD_STATE_ID__SHIFT = 8 # macro
REG_A6XX_PC_DBG_ECO_CNTL = 0x00009e00 # macro
REG_A6XX_PC_ADDR_MODE_CNTL = 0x00009e01 # macro
REG_A6XX_PC_DRAW_INDX_BASE = 0x00009e04 # macro
REG_A6XX_PC_DRAW_FIRST_INDX = 0x00009e06 # macro
REG_A6XX_PC_DRAW_MAX_INDICES = 0x00009e07 # macro
REG_A6XX_PC_TESSFACTOR_ADDR = 0x00009e08 # macro
REG_A7XX_PC_TESSFACTOR_ADDR = 0x00009810 # macro
REG_A6XX_PC_DRAW_INITIATOR = 0x00009e0b # macro
A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__MASK = 0x0000003f # macro
A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__SHIFT = 0 # macro
A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__MASK = 0x000000c0 # macro
A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__SHIFT = 6 # macro
A6XX_PC_DRAW_INITIATOR_VIS_CULL__MASK = 0x00000300 # macro
A6XX_PC_DRAW_INITIATOR_VIS_CULL__SHIFT = 8 # macro
A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__MASK = 0x00000c00 # macro
A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__SHIFT = 10 # macro
A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__MASK = 0x00003000 # macro
A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__SHIFT = 12 # macro
A6XX_PC_DRAW_INITIATOR_GS_ENABLE = 0x00010000 # macro
A6XX_PC_DRAW_INITIATOR_TESS_ENABLE = 0x00020000 # macro
REG_A6XX_PC_DRAW_NUM_INSTANCES = 0x00009e0c # macro
REG_A6XX_PC_DRAW_NUM_INDICES = 0x00009e0d # macro
REG_A6XX_PC_VSTREAM_CONTROL = 0x00009e11 # macro
A6XX_PC_VSTREAM_CONTROL_UNK0__MASK = 0x0000ffff # macro
A6XX_PC_VSTREAM_CONTROL_UNK0__SHIFT = 0 # macro
A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__MASK = 0x003f0000 # macro
A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__SHIFT = 16 # macro
A6XX_PC_VSTREAM_CONTROL_VSC_N__MASK = 0x07c00000 # macro
A6XX_PC_VSTREAM_CONTROL_VSC_N__SHIFT = 22 # macro
REG_A6XX_PC_BIN_PRIM_STRM = 0x00009e12 # macro
REG_A6XX_PC_BIN_DRAW_STRM = 0x00009e14 # macro
REG_A6XX_PC_VISIBILITY_OVERRIDE = 0x00009e1c # macro
A6XX_PC_VISIBILITY_OVERRIDE_OVERRIDE = 0x00000001 # macro
REG_A7XX_PC_UNKNOWN_9E24 = 0x00009e24 # macro
# def REG_A6XX_PC_PERFCTR_PC_SEL(i0): # macro
# return (0x00009e34+0x1*i0)
# def REG_A7XX_PC_PERFCTR_PC_SEL(i0): # macro
# return (0x00009e42+0x1*i0)
REG_A6XX_PC_UNKNOWN_9E72 = 0x00009e72 # macro
REG_A6XX_VFD_CONTROL_0 = 0x0000a000 # macro
A6XX_VFD_CONTROL_0_FETCH_CNT__MASK = 0x0000003f # macro
A6XX_VFD_CONTROL_0_FETCH_CNT__SHIFT = 0 # macro
A6XX_VFD_CONTROL_0_DECODE_CNT__MASK = 0x00003f00 # macro
A6XX_VFD_CONTROL_0_DECODE_CNT__SHIFT = 8 # macro
REG_A6XX_VFD_CONTROL_1 = 0x0000a001 # macro
A6XX_VFD_CONTROL_1_REGID4VTX__MASK = 0x000000ff # macro
A6XX_VFD_CONTROL_1_REGID4VTX__SHIFT = 0 # macro
A6XX_VFD_CONTROL_1_REGID4INST__MASK = 0x0000ff00 # macro
A6XX_VFD_CONTROL_1_REGID4INST__SHIFT = 8 # macro
A6XX_VFD_CONTROL_1_REGID4PRIMID__MASK = 0x00ff0000 # macro
A6XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT = 16 # macro
A6XX_VFD_CONTROL_1_REGID4VIEWID__MASK = 0xff000000 # macro
A6XX_VFD_CONTROL_1_REGID4VIEWID__SHIFT = 24 # macro
REG_A6XX_VFD_CONTROL_2 = 0x0000a002 # macro
A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID__MASK = 0x000000ff # macro
A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID__SHIFT = 0 # macro
A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__MASK = 0x0000ff00 # macro
A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__SHIFT = 8 # macro
REG_A6XX_VFD_CONTROL_3 = 0x0000a003 # macro
A6XX_VFD_CONTROL_3_REGID_DSPRIMID__MASK = 0x000000ff # macro
A6XX_VFD_CONTROL_3_REGID_DSPRIMID__SHIFT = 0 # macro
A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID__MASK = 0x0000ff00 # macro
A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID__SHIFT = 8 # macro
A6XX_VFD_CONTROL_3_REGID_TESSX__MASK = 0x00ff0000 # macro
A6XX_VFD_CONTROL_3_REGID_TESSX__SHIFT = 16 # macro
A6XX_VFD_CONTROL_3_REGID_TESSY__MASK = 0xff000000 # macro
A6XX_VFD_CONTROL_3_REGID_TESSY__SHIFT = 24 # macro
REG_A6XX_VFD_CONTROL_4 = 0x0000a004 # macro
A6XX_VFD_CONTROL_4_UNK0__MASK = 0x000000ff # macro
A6XX_VFD_CONTROL_4_UNK0__SHIFT = 0 # macro
REG_A6XX_VFD_CONTROL_5 = 0x0000a005 # macro
A6XX_VFD_CONTROL_5_REGID_GSHEADER__MASK = 0x000000ff # macro
A6XX_VFD_CONTROL_5_REGID_GSHEADER__SHIFT = 0 # macro
A6XX_VFD_CONTROL_5_UNK8__MASK = 0x0000ff00 # macro
A6XX_VFD_CONTROL_5_UNK8__SHIFT = 8 # macro
REG_A6XX_VFD_CONTROL_6 = 0x0000a006 # macro
A6XX_VFD_CONTROL_6_PRIMID4PSEN = 0x00000001 # macro
REG_A6XX_VFD_MODE_CNTL = 0x0000a007 # macro
A6XX_VFD_MODE_CNTL_RENDER_MODE__MASK = 0x00000007 # macro
A6XX_VFD_MODE_CNTL_RENDER_MODE__SHIFT = 0 # macro
REG_A6XX_VFD_MULTIVIEW_CNTL = 0x0000a008 # macro
A6XX_VFD_MULTIVIEW_CNTL_ENABLE = 0x00000001 # macro
A6XX_VFD_MULTIVIEW_CNTL_DISABLEMULTIPOS = 0x00000002 # macro
A6XX_VFD_MULTIVIEW_CNTL_VIEWS__MASK = 0x0000007c # macro
A6XX_VFD_MULTIVIEW_CNTL_VIEWS__SHIFT = 2 # macro
REG_A6XX_VFD_ADD_OFFSET = 0x0000a009 # macro
A6XX_VFD_ADD_OFFSET_VERTEX = 0x00000001 # macro
A6XX_VFD_ADD_OFFSET_INSTANCE = 0x00000002 # macro
REG_A6XX_VFD_INDEX_OFFSET = 0x0000a00e # macro
REG_A6XX_VFD_INSTANCE_START_OFFSET = 0x0000a00f # macro
# def REG_A6XX_VFD_FETCH(i0): # macro
# return (0x0000a010+0x4*i0)
# def REG_A6XX_VFD_DECODE(i0): # macro
# return (0x0000a090+0x2*i0)
A6XX_VFD_DECODE_INSTR_IDX__MASK = 0x0000001f # macro
A6XX_VFD_DECODE_INSTR_IDX__SHIFT = 0 # macro
A6XX_VFD_DECODE_INSTR_OFFSET__MASK = 0x0001ffe0 # macro
A6XX_VFD_DECODE_INSTR_OFFSET__SHIFT = 5 # macro
A6XX_VFD_DECODE_INSTR_INSTANCED = 0x00020000 # macro
A6XX_VFD_DECODE_INSTR_FORMAT__MASK = 0x0ff00000 # macro
A6XX_VFD_DECODE_INSTR_FORMAT__SHIFT = 20 # macro
A6XX_VFD_DECODE_INSTR_SWAP__MASK = 0x30000000 # macro
A6XX_VFD_DECODE_INSTR_SWAP__SHIFT = 28 # macro
A6XX_VFD_DECODE_INSTR_UNK30 = 0x40000000 # macro
A6XX_VFD_DECODE_INSTR_FLOAT = 0x80000000 # macro
# def REG_A6XX_VFD_DEST_CNTL(i0): # macro
# return (0x0000a0d0+0x1*i0)
A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK = 0x0000000f # macro
A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT = 0 # macro
A6XX_VFD_DEST_CNTL_INSTR_REGID__MASK = 0x00000ff0 # macro
A6XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT = 4 # macro
REG_A6XX_VFD_POWER_CNTL = 0x0000a0f8 # macro
REG_A7XX_VFD_UNKNOWN_A600 = 0x0000a600 # macro
REG_A6XX_VFD_ADDR_MODE_CNTL = 0x0000a601 # macro
# def REG_A6XX_VFD_PERFCTR_VFD_SEL(i0): # macro
# return (0x0000a610+0x1*i0)
# def REG_A7XX_VFD_PERFCTR_VFD_SEL(i0): # macro
# return (0x0000a610+0x1*i0)
REG_A6XX_SP_VS_CTRL_REG0 = 0x0000a800 # macro
A6XX_SP_VS_CTRL_REG0_THREADMODE__MASK = 0x00000001 # macro
A6XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT = 0 # macro
A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK = 0x0000007e # macro
A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT = 1 # macro
A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK = 0x00001f80 # macro
A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT = 7 # macro
A6XX_SP_VS_CTRL_REG0_UNK13 = 0x00002000 # macro
A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK = 0x000fc000 # macro
A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT = 14 # macro
A6XX_SP_VS_CTRL_REG0_MERGEDREGS = 0x00100000 # macro
A6XX_SP_VS_CTRL_REG0_EARLYPREAMBLE = 0x00200000 # macro
REG_A6XX_SP_VS_BRANCH_COND = 0x0000a801 # macro
REG_A6XX_SP_VS_PRIMITIVE_CNTL = 0x0000a802 # macro
A6XX_SP_VS_PRIMITIVE_CNTL_OUT__MASK = 0x0000003f # macro
A6XX_SP_VS_PRIMITIVE_CNTL_OUT__SHIFT = 0 # macro
A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__MASK = 0x00003fc0 # macro
A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT = 6 # macro
# def REG_A6XX_SP_VS_OUT(i0): # macro
# return (0x0000a803+0x1*i0)
A6XX_SP_VS_OUT_REG_A_REGID__MASK = 0x000000ff # macro
A6XX_SP_VS_OUT_REG_A_REGID__SHIFT = 0 # macro
A6XX_SP_VS_OUT_REG_A_COMPMASK__MASK = 0x00000f00 # macro
A6XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT = 8 # macro
A6XX_SP_VS_OUT_REG_B_REGID__MASK = 0x00ff0000 # macro
A6XX_SP_VS_OUT_REG_B_REGID__SHIFT = 16 # macro
A6XX_SP_VS_OUT_REG_B_COMPMASK__MASK = 0x0f000000 # macro
A6XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT = 24 # macro
# def REG_A6XX_SP_VS_VPC_DST(i0): # macro
# return (0x0000a813+0x1*i0)
A6XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK = 0x000000ff # macro
A6XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT = 0 # macro
A6XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK = 0x0000ff00 # macro
A6XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT = 8 # macro
A6XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK = 0x00ff0000 # macro
A6XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT = 16 # macro
A6XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK = 0xff000000 # macro
A6XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT = 24 # macro
REG_A6XX_SP_VS_OBJ_FIRST_EXEC_OFFSET = 0x0000a81b # macro
REG_A6XX_SP_VS_OBJ_START = 0x0000a81c # macro
REG_A6XX_SP_VS_PVT_MEM_PARAM = 0x0000a81e # macro
A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK = 0x000000ff # macro
A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT = 0 # macro
A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK = 0xff000000 # macro
A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT = 24 # macro
REG_A6XX_SP_VS_PVT_MEM_ADDR = 0x0000a81f # macro
REG_A6XX_SP_VS_PVT_MEM_SIZE = 0x0000a821 # macro
A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK = 0x0003ffff # macro
A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT = 0 # macro
A6XX_SP_VS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT = 0x80000000 # macro
REG_A6XX_SP_VS_TEX_COUNT = 0x0000a822 # macro
REG_A6XX_SP_VS_CONFIG = 0x0000a823 # macro
A6XX_SP_VS_CONFIG_BINDLESS_TEX = 0x00000001 # macro
A6XX_SP_VS_CONFIG_BINDLESS_SAMP = 0x00000002 # macro
A6XX_SP_VS_CONFIG_BINDLESS_IBO = 0x00000004 # macro
A6XX_SP_VS_CONFIG_BINDLESS_UBO = 0x00000008 # macro
A6XX_SP_VS_CONFIG_ENABLED = 0x00000100 # macro
A6XX_SP_VS_CONFIG_NTEX__MASK = 0x0001fe00 # macro
A6XX_SP_VS_CONFIG_NTEX__SHIFT = 9 # macro
A6XX_SP_VS_CONFIG_NSAMP__MASK = 0x003e0000 # macro
A6XX_SP_VS_CONFIG_NSAMP__SHIFT = 17 # macro
A6XX_SP_VS_CONFIG_NIBO__MASK = 0x1fc00000 # macro
A6XX_SP_VS_CONFIG_NIBO__SHIFT = 22 # macro
REG_A6XX_SP_VS_INSTRLEN = 0x0000a824 # macro
REG_A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET = 0x0000a825 # macro
A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK = 0x0007ffff # macro
A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT = 0 # macro
REG_A7XX_SP_VS_VGPR_CONFIG = 0x0000a82d # macro
REG_A6XX_SP_HS_CTRL_REG0 = 0x0000a830 # macro
A6XX_SP_HS_CTRL_REG0_THREADMODE__MASK = 0x00000001 # macro
A6XX_SP_HS_CTRL_REG0_THREADMODE__SHIFT = 0 # macro
A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK = 0x0000007e # macro
A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT = 1 # macro
A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK = 0x00001f80 # macro
A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT = 7 # macro
A6XX_SP_HS_CTRL_REG0_UNK13 = 0x00002000 # macro
A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK = 0x000fc000 # macro
A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT = 14 # macro
A6XX_SP_HS_CTRL_REG0_EARLYPREAMBLE = 0x00100000 # macro
REG_A6XX_SP_HS_WAVE_INPUT_SIZE = 0x0000a831 # macro
REG_A6XX_SP_HS_BRANCH_COND = 0x0000a832 # macro
REG_A6XX_SP_HS_OBJ_FIRST_EXEC_OFFSET = 0x0000a833 # macro
REG_A6XX_SP_HS_OBJ_START = 0x0000a834 # macro
REG_A6XX_SP_HS_PVT_MEM_PARAM = 0x0000a836 # macro
A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK = 0x000000ff # macro
A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT = 0 # macro
A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK = 0xff000000 # macro
A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT = 24 # macro
REG_A6XX_SP_HS_PVT_MEM_ADDR = 0x0000a837 # macro
REG_A6XX_SP_HS_PVT_MEM_SIZE = 0x0000a839 # macro
A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK = 0x0003ffff # macro
A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT = 0 # macro
A6XX_SP_HS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT = 0x80000000 # macro
REG_A6XX_SP_HS_TEX_COUNT = 0x0000a83a # macro
REG_A6XX_SP_HS_CONFIG = 0x0000a83b # macro
A6XX_SP_HS_CONFIG_BINDLESS_TEX = 0x00000001 # macro
A6XX_SP_HS_CONFIG_BINDLESS_SAMP = 0x00000002 # macro
A6XX_SP_HS_CONFIG_BINDLESS_IBO = 0x00000004 # macro
A6XX_SP_HS_CONFIG_BINDLESS_UBO = 0x00000008 # macro
A6XX_SP_HS_CONFIG_ENABLED = 0x00000100 # macro
A6XX_SP_HS_CONFIG_NTEX__MASK = 0x0001fe00 # macro
A6XX_SP_HS_CONFIG_NTEX__SHIFT = 9 # macro
A6XX_SP_HS_CONFIG_NSAMP__MASK = 0x003e0000 # macro
A6XX_SP_HS_CONFIG_NSAMP__SHIFT = 17 # macro
A6XX_SP_HS_CONFIG_NIBO__MASK = 0x1fc00000 # macro
A6XX_SP_HS_CONFIG_NIBO__SHIFT = 22 # macro
REG_A6XX_SP_HS_INSTRLEN = 0x0000a83c # macro
REG_A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET = 0x0000a83d # macro
A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK = 0x0007ffff # macro
A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT = 0 # macro
REG_A7XX_SP_HS_VGPR_CONFIG = 0x0000a82f # macro
REG_A6XX_SP_DS_CTRL_REG0 = 0x0000a840 # macro
A6XX_SP_DS_CTRL_REG0_THREADMODE__MASK = 0x00000001 # macro
A6XX_SP_DS_CTRL_REG0_THREADMODE__SHIFT = 0 # macro
A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK = 0x0000007e # macro
A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT = 1 # macro
A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK = 0x00001f80 # macro
A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT = 7 # macro
A6XX_SP_DS_CTRL_REG0_UNK13 = 0x00002000 # macro
A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK = 0x000fc000 # macro
A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT = 14 # macro
A6XX_SP_DS_CTRL_REG0_EARLYPREAMBLE = 0x00100000 # macro
REG_A6XX_SP_DS_BRANCH_COND = 0x0000a841 # macro
REG_A6XX_SP_DS_PRIMITIVE_CNTL = 0x0000a842 # macro
A6XX_SP_DS_PRIMITIVE_CNTL_OUT__MASK = 0x0000003f # macro
A6XX_SP_DS_PRIMITIVE_CNTL_OUT__SHIFT = 0 # macro
A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__MASK = 0x00003fc0 # macro
A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT = 6 # macro
# def REG_A6XX_SP_DS_OUT(i0): # macro
# return (0x0000a843+0x1*i0)
A6XX_SP_DS_OUT_REG_A_REGID__MASK = 0x000000ff # macro
A6XX_SP_DS_OUT_REG_A_REGID__SHIFT = 0 # macro
A6XX_SP_DS_OUT_REG_A_COMPMASK__MASK = 0x00000f00 # macro
A6XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT = 8 # macro
A6XX_SP_DS_OUT_REG_B_REGID__MASK = 0x00ff0000 # macro
A6XX_SP_DS_OUT_REG_B_REGID__SHIFT = 16 # macro
A6XX_SP_DS_OUT_REG_B_COMPMASK__MASK = 0x0f000000 # macro
A6XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT = 24 # macro
# def REG_A6XX_SP_DS_VPC_DST(i0): # macro
# return (0x0000a853+0x1*i0)
A6XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK = 0x000000ff # macro
A6XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT = 0 # macro
A6XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK = 0x0000ff00 # macro
A6XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT = 8 # macro
A6XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK = 0x00ff0000 # macro
A6XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT = 16 # macro
A6XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK = 0xff000000 # macro
A6XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT = 24 # macro
REG_A6XX_SP_DS_OBJ_FIRST_EXEC_OFFSET = 0x0000a85b # macro
REG_A6XX_SP_DS_OBJ_START = 0x0000a85c # macro
REG_A6XX_SP_DS_PVT_MEM_PARAM = 0x0000a85e # macro
A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK = 0x000000ff # macro
A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT = 0 # macro
A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK = 0xff000000 # macro
A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT = 24 # macro
REG_A6XX_SP_DS_PVT_MEM_ADDR = 0x0000a85f # macro
REG_A6XX_SP_DS_PVT_MEM_SIZE = 0x0000a861 # macro
A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK = 0x0003ffff # macro
A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT = 0 # macro
A6XX_SP_DS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT = 0x80000000 # macro
REG_A6XX_SP_DS_TEX_COUNT = 0x0000a862 # macro
REG_A6XX_SP_DS_CONFIG = 0x0000a863 # macro
A6XX_SP_DS_CONFIG_BINDLESS_TEX = 0x00000001 # macro
A6XX_SP_DS_CONFIG_BINDLESS_SAMP = 0x00000002 # macro
A6XX_SP_DS_CONFIG_BINDLESS_IBO = 0x00000004 # macro
A6XX_SP_DS_CONFIG_BINDLESS_UBO = 0x00000008 # macro
A6XX_SP_DS_CONFIG_ENABLED = 0x00000100 # macro
A6XX_SP_DS_CONFIG_NTEX__MASK = 0x0001fe00 # macro
A6XX_SP_DS_CONFIG_NTEX__SHIFT = 9 # macro
A6XX_SP_DS_CONFIG_NSAMP__MASK = 0x003e0000 # macro
A6XX_SP_DS_CONFIG_NSAMP__SHIFT = 17 # macro
A6XX_SP_DS_CONFIG_NIBO__MASK = 0x1fc00000 # macro
A6XX_SP_DS_CONFIG_NIBO__SHIFT = 22 # macro
REG_A6XX_SP_DS_INSTRLEN = 0x0000a864 # macro
REG_A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET = 0x0000a865 # macro
A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK = 0x0007ffff # macro
A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT = 0 # macro
REG_A7XX_SP_DS_VGPR_CONFIG = 0x0000a868 # macro
REG_A6XX_SP_GS_CTRL_REG0 = 0x0000a870 # macro
A6XX_SP_GS_CTRL_REG0_THREADMODE__MASK = 0x00000001 # macro
A6XX_SP_GS_CTRL_REG0_THREADMODE__SHIFT = 0 # macro
A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK = 0x0000007e # macro
A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT = 1 # macro
A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK = 0x00001f80 # macro
A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT = 7 # macro
A6XX_SP_GS_CTRL_REG0_UNK13 = 0x00002000 # macro
A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK = 0x000fc000 # macro
A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT = 14 # macro
A6XX_SP_GS_CTRL_REG0_EARLYPREAMBLE = 0x00100000 # macro
REG_A6XX_SP_GS_PRIM_SIZE = 0x0000a871 # macro
REG_A6XX_SP_GS_BRANCH_COND = 0x0000a872 # macro
REG_A6XX_SP_GS_PRIMITIVE_CNTL = 0x0000a873 # macro
A6XX_SP_GS_PRIMITIVE_CNTL_OUT__MASK = 0x0000003f # macro
A6XX_SP_GS_PRIMITIVE_CNTL_OUT__SHIFT = 0 # macro
A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__MASK = 0x00003fc0 # macro
A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT = 6 # macro
# def REG_A6XX_SP_GS_OUT(i0): # macro
# return (0x0000a874+0x1*i0)
A6XX_SP_GS_OUT_REG_A_REGID__MASK = 0x000000ff # macro
A6XX_SP_GS_OUT_REG_A_REGID__SHIFT = 0 # macro
A6XX_SP_GS_OUT_REG_A_COMPMASK__MASK = 0x00000f00 # macro
A6XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT = 8 # macro
A6XX_SP_GS_OUT_REG_B_REGID__MASK = 0x00ff0000 # macro
A6XX_SP_GS_OUT_REG_B_REGID__SHIFT = 16 # macro
A6XX_SP_GS_OUT_REG_B_COMPMASK__MASK = 0x0f000000 # macro
A6XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT = 24 # macro
# def REG_A6XX_SP_GS_VPC_DST(i0): # macro
# return (0x0000a884+0x1*i0)
A6XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK = 0x000000ff # macro
A6XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT = 0 # macro
A6XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK = 0x0000ff00 # macro
A6XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT = 8 # macro
A6XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK = 0x00ff0000 # macro
A6XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT = 16 # macro
A6XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK = 0xff000000 # macro
A6XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT = 24 # macro
REG_A6XX_SP_GS_OBJ_FIRST_EXEC_OFFSET = 0x0000a88c # macro
REG_A6XX_SP_GS_OBJ_START = 0x0000a88d # macro
REG_A6XX_SP_GS_PVT_MEM_PARAM = 0x0000a88f # macro
A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK = 0x000000ff # macro
A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT = 0 # macro
A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK = 0xff000000 # macro
A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT = 24 # macro
REG_A6XX_SP_GS_PVT_MEM_ADDR = 0x0000a890 # macro
REG_A6XX_SP_GS_PVT_MEM_SIZE = 0x0000a892 # macro
A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK = 0x0003ffff # macro
A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT = 0 # macro
A6XX_SP_GS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT = 0x80000000 # macro
REG_A6XX_SP_GS_TEX_COUNT = 0x0000a893 # macro
REG_A6XX_SP_GS_CONFIG = 0x0000a894 # macro
A6XX_SP_GS_CONFIG_BINDLESS_TEX = 0x00000001 # macro
A6XX_SP_GS_CONFIG_BINDLESS_SAMP = 0x00000002 # macro
A6XX_SP_GS_CONFIG_BINDLESS_IBO = 0x00000004 # macro
A6XX_SP_GS_CONFIG_BINDLESS_UBO = 0x00000008 # macro
A6XX_SP_GS_CONFIG_ENABLED = 0x00000100 # macro
A6XX_SP_GS_CONFIG_NTEX__MASK = 0x0001fe00 # macro
A6XX_SP_GS_CONFIG_NTEX__SHIFT = 9 # macro
A6XX_SP_GS_CONFIG_NSAMP__MASK = 0x003e0000 # macro
A6XX_SP_GS_CONFIG_NSAMP__SHIFT = 17 # macro
A6XX_SP_GS_CONFIG_NIBO__MASK = 0x1fc00000 # macro
A6XX_SP_GS_CONFIG_NIBO__SHIFT = 22 # macro
REG_A6XX_SP_GS_INSTRLEN = 0x0000a895 # macro
REG_A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET = 0x0000a896 # macro
A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK = 0x0007ffff # macro
A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT = 0 # macro
REG_A7XX_SP_GS_VGPR_CONFIG = 0x0000a899 # macro
REG_A6XX_SP_VS_TEX_SAMP = 0x0000a8a0 # macro
REG_A6XX_SP_HS_TEX_SAMP = 0x0000a8a2 # macro
REG_A6XX_SP_DS_TEX_SAMP = 0x0000a8a4 # macro
REG_A6XX_SP_GS_TEX_SAMP = 0x0000a8a6 # macro
REG_A6XX_SP_VS_TEX_CONST = 0x0000a8a8 # macro
REG_A6XX_SP_HS_TEX_CONST = 0x0000a8aa # macro
REG_A6XX_SP_DS_TEX_CONST = 0x0000a8ac # macro
REG_A6XX_SP_GS_TEX_CONST = 0x0000a8ae # macro
REG_A6XX_SP_FS_CTRL_REG0 = 0x0000a980 # macro
A6XX_SP_FS_CTRL_REG0_THREADMODE__MASK = 0x00000001 # macro
A6XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT = 0 # macro
A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK = 0x0000007e # macro
A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT = 1 # macro
A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK = 0x00001f80 # macro
A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT = 7 # macro
A6XX_SP_FS_CTRL_REG0_UNK13 = 0x00002000 # macro
A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK = 0x000fc000 # macro
A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT = 14 # macro
A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK = 0x00100000 # macro
A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT = 20 # macro
A6XX_SP_FS_CTRL_REG0_UNK21 = 0x00200000 # macro
A6XX_SP_FS_CTRL_REG0_VARYING = 0x00400000 # macro
A6XX_SP_FS_CTRL_REG0_LODPIXMASK = 0x00800000 # macro
A6XX_SP_FS_CTRL_REG0_UNK24 = 0x01000000 # macro
A6XX_SP_FS_CTRL_REG0_UNK25 = 0x02000000 # macro
A6XX_SP_FS_CTRL_REG0_PIXLODENABLE = 0x04000000 # macro
A6XX_SP_FS_CTRL_REG0_UNK27 = 0x08000000 # macro
A6XX_SP_FS_CTRL_REG0_EARLYPREAMBLE = 0x10000000 # macro
A6XX_SP_FS_CTRL_REG0_MERGEDREGS = 0x80000000 # macro
REG_A6XX_SP_FS_BRANCH_COND = 0x0000a981 # macro
REG_A6XX_SP_FS_OBJ_FIRST_EXEC_OFFSET = 0x0000a982 # macro
REG_A6XX_SP_FS_OBJ_START = 0x0000a983 # macro
REG_A6XX_SP_FS_PVT_MEM_PARAM = 0x0000a985 # macro
A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK = 0x000000ff # macro
A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT = 0 # macro
A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK = 0xff000000 # macro
A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT = 24 # macro
REG_A6XX_SP_FS_PVT_MEM_ADDR = 0x0000a986 # macro
REG_A6XX_SP_FS_PVT_MEM_SIZE = 0x0000a988 # macro
A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK = 0x0003ffff # macro
A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT = 0 # macro
A6XX_SP_FS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT = 0x80000000 # macro
REG_A6XX_SP_BLEND_CNTL = 0x0000a989 # macro
A6XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK = 0x000000ff # macro
A6XX_SP_BLEND_CNTL_ENABLE_BLEND__SHIFT = 0 # macro
A6XX_SP_BLEND_CNTL_UNK8 = 0x00000100 # macro
A6XX_SP_BLEND_CNTL_DUAL_COLOR_IN_ENABLE = 0x00000200 # macro
A6XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE = 0x00000400 # macro
REG_A6XX_SP_SRGB_CNTL = 0x0000a98a # macro
A6XX_SP_SRGB_CNTL_SRGB_MRT0 = 0x00000001 # macro
A6XX_SP_SRGB_CNTL_SRGB_MRT1 = 0x00000002 # macro
A6XX_SP_SRGB_CNTL_SRGB_MRT2 = 0x00000004 # macro
A6XX_SP_SRGB_CNTL_SRGB_MRT3 = 0x00000008 # macro
A6XX_SP_SRGB_CNTL_SRGB_MRT4 = 0x00000010 # macro
A6XX_SP_SRGB_CNTL_SRGB_MRT5 = 0x00000020 # macro
A6XX_SP_SRGB_CNTL_SRGB_MRT6 = 0x00000040 # macro
A6XX_SP_SRGB_CNTL_SRGB_MRT7 = 0x00000080 # macro
REG_A6XX_SP_FS_RENDER_COMPONENTS = 0x0000a98b # macro
A6XX_SP_FS_RENDER_COMPONENTS_RT0__MASK = 0x0000000f # macro
A6XX_SP_FS_RENDER_COMPONENTS_RT0__SHIFT = 0 # macro
A6XX_SP_FS_RENDER_COMPONENTS_RT1__MASK = 0x000000f0 # macro
A6XX_SP_FS_RENDER_COMPONENTS_RT1__SHIFT = 4 # macro
A6XX_SP_FS_RENDER_COMPONENTS_RT2__MASK = 0x00000f00 # macro
A6XX_SP_FS_RENDER_COMPONENTS_RT2__SHIFT = 8 # macro
A6XX_SP_FS_RENDER_COMPONENTS_RT3__MASK = 0x0000f000 # macro
A6XX_SP_FS_RENDER_COMPONENTS_RT3__SHIFT = 12 # macro
A6XX_SP_FS_RENDER_COMPONENTS_RT4__MASK = 0x000f0000 # macro
A6XX_SP_FS_RENDER_COMPONENTS_RT4__SHIFT = 16 # macro
A6XX_SP_FS_RENDER_COMPONENTS_RT5__MASK = 0x00f00000 # macro
A6XX_SP_FS_RENDER_COMPONENTS_RT5__SHIFT = 20 # macro
A6XX_SP_FS_RENDER_COMPONENTS_RT6__MASK = 0x0f000000 # macro
A6XX_SP_FS_RENDER_COMPONENTS_RT6__SHIFT = 24 # macro
A6XX_SP_FS_RENDER_COMPONENTS_RT7__MASK = 0xf0000000 # macro
A6XX_SP_FS_RENDER_COMPONENTS_RT7__SHIFT = 28 # macro
REG_A6XX_SP_FS_OUTPUT_CNTL0 = 0x0000a98c # macro
A6XX_SP_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE = 0x00000001 # macro
A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__MASK = 0x0000ff00 # macro
A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__SHIFT = 8 # macro
A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__MASK = 0x00ff0000 # macro
A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__SHIFT = 16 # macro
A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__MASK = 0xff000000 # macro
A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__SHIFT = 24 # macro
REG_A6XX_SP_FS_OUTPUT_CNTL1 = 0x0000a98d # macro
A6XX_SP_FS_OUTPUT_CNTL1_MRT__MASK = 0x0000000f # macro
A6XX_SP_FS_OUTPUT_CNTL1_MRT__SHIFT = 0 # macro
# def REG_A6XX_SP_FS_OUTPUT(i0): # macro
# return (0x0000a98e+0x1*i0)
A6XX_SP_FS_OUTPUT_REG_REGID__MASK = 0x000000ff # macro
A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT = 0 # macro
A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION = 0x00000100 # macro
# def REG_A6XX_SP_FS_MRT(i0): # macro
# return (0x0000a996+0x1*i0)
A6XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK = 0x000000ff # macro
A6XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT = 0 # macro
A6XX_SP_FS_MRT_REG_COLOR_SINT = 0x00000100 # macro
A6XX_SP_FS_MRT_REG_COLOR_UINT = 0x00000200 # macro
A6XX_SP_FS_MRT_REG_UNK10 = 0x00000400 # macro
REG_A6XX_SP_FS_PREFETCH_CNTL = 0x0000a99e # macro
A6XX_SP_FS_PREFETCH_CNTL_COUNT__MASK = 0x00000007 # macro
A6XX_SP_FS_PREFETCH_CNTL_COUNT__SHIFT = 0 # macro
A6XX_SP_FS_PREFETCH_CNTL_IJ_WRITE_DISABLE = 0x00000008 # macro
A6XX_SP_FS_PREFETCH_CNTL_ENDOFQUAD = 0x00000010 # macro
A6XX_SP_FS_PREFETCH_CNTL_WRITE_COLOR_TO_OUTPUT = 0x00000020 # macro
A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID__MASK = 0x00007fc0 # macro
A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID__SHIFT = 6 # macro
A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID4COORD__MASK = 0x01ff0000 # macro
A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID4COORD__SHIFT = 16 # macro
# def REG_A6XX_SP_FS_PREFETCH(i0): # macro
# return (0x0000a99f+0x1*i0)
A6XX_SP_FS_PREFETCH_CMD_SRC__MASK = 0x0000007f # macro
A6XX_SP_FS_PREFETCH_CMD_SRC__SHIFT = 0 # macro
A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__MASK = 0x00000780 # macro
A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__SHIFT = 7 # macro
A6XX_SP_FS_PREFETCH_CMD_TEX_ID__MASK = 0x0000f800 # macro
A6XX_SP_FS_PREFETCH_CMD_TEX_ID__SHIFT = 11 # macro
A6XX_SP_FS_PREFETCH_CMD_DST__MASK = 0x003f0000 # macro
A6XX_SP_FS_PREFETCH_CMD_DST__SHIFT = 16 # macro
A6XX_SP_FS_PREFETCH_CMD_WRMASK__MASK = 0x03c00000 # macro
A6XX_SP_FS_PREFETCH_CMD_WRMASK__SHIFT = 22 # macro
A6XX_SP_FS_PREFETCH_CMD_HALF = 0x04000000 # macro
A6XX_SP_FS_PREFETCH_CMD_UNK27 = 0x08000000 # macro
A6XX_SP_FS_PREFETCH_CMD_BINDLESS = 0x10000000 # macro
A6XX_SP_FS_PREFETCH_CMD_CMD__MASK = 0xe0000000 # macro
A6XX_SP_FS_PREFETCH_CMD_CMD__SHIFT = 29 # macro
# def REG_A7XX_SP_FS_PREFETCH(i0): # macro
# return (0x0000a99f+0x1*i0)
A7XX_SP_FS_PREFETCH_CMD_SRC__MASK = 0x0000007f # macro
A7XX_SP_FS_PREFETCH_CMD_SRC__SHIFT = 0 # macro
A7XX_SP_FS_PREFETCH_CMD_SAMP_ID__MASK = 0x00000380 # macro
A7XX_SP_FS_PREFETCH_CMD_SAMP_ID__SHIFT = 7 # macro
A7XX_SP_FS_PREFETCH_CMD_TEX_ID__MASK = 0x00001c00 # macro
A7XX_SP_FS_PREFETCH_CMD_TEX_ID__SHIFT = 10 # macro
A7XX_SP_FS_PREFETCH_CMD_DST__MASK = 0x0007e000 # macro
A7XX_SP_FS_PREFETCH_CMD_DST__SHIFT = 13 # macro
A7XX_SP_FS_PREFETCH_CMD_WRMASK__MASK = 0x00780000 # macro
A7XX_SP_FS_PREFETCH_CMD_WRMASK__SHIFT = 19 # macro
A7XX_SP_FS_PREFETCH_CMD_HALF = 0x00800000 # macro
A7XX_SP_FS_PREFETCH_CMD_BINDLESS = 0x02000000 # macro
A7XX_SP_FS_PREFETCH_CMD_CMD__MASK = 0x3c000000 # macro
A7XX_SP_FS_PREFETCH_CMD_CMD__SHIFT = 26 # macro
# def REG_A6XX_SP_FS_BINDLESS_PREFETCH(i0): # macro
# return (0x0000a9a3+0x1*i0)
A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__MASK = 0x0000ffff # macro
A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__SHIFT = 0 # macro
A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__MASK = 0xffff0000 # macro
A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__SHIFT = 16 # macro
REG_A6XX_SP_FS_TEX_COUNT = 0x0000a9a7 # macro
REG_A6XX_SP_UNKNOWN_A9A8 = 0x0000a9a8 # macro
REG_A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET = 0x0000a9a9 # macro
A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK = 0x0007ffff # macro
A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT = 0 # macro
REG_A6XX_SP_CS_CTRL_REG0 = 0x0000a9b0 # macro
A6XX_SP_CS_CTRL_REG0_THREADMODE__MASK = 0x00000001 # macro
A6XX_SP_CS_CTRL_REG0_THREADMODE__SHIFT = 0 # macro
A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK = 0x0000007e # macro
A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT = 1 # macro
A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK = 0x00001f80 # macro
A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT = 7 # macro
A6XX_SP_CS_CTRL_REG0_UNK13 = 0x00002000 # macro
A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK = 0x000fc000 # macro
A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT = 14 # macro
A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK = 0x00100000 # macro
A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT = 20 # macro
A6XX_SP_CS_CTRL_REG0_UNK21 = 0x00200000 # macro
A6XX_SP_CS_CTRL_REG0_UNK22 = 0x00400000 # macro
A6XX_SP_CS_CTRL_REG0_EARLYPREAMBLE = 0x00800000 # macro
A6XX_SP_CS_CTRL_REG0_MERGEDREGS = 0x80000000 # macro
REG_A6XX_SP_CS_UNKNOWN_A9B1 = 0x0000a9b1 # macro
A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__MASK = 0x0000001f # macro
A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__SHIFT = 0 # macro
A6XX_SP_CS_UNKNOWN_A9B1_UNK5 = 0x00000020 # macro
A6XX_SP_CS_UNKNOWN_A9B1_UNK6 = 0x00000040 # macro
REG_A6XX_SP_CS_BRANCH_COND = 0x0000a9b2 # macro
REG_A6XX_SP_CS_OBJ_FIRST_EXEC_OFFSET = 0x0000a9b3 # macro
REG_A6XX_SP_CS_OBJ_START = 0x0000a9b4 # macro
REG_A6XX_SP_CS_PVT_MEM_PARAM = 0x0000a9b6 # macro
A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK = 0x000000ff # macro
A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT = 0 # macro
A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK = 0xff000000 # macro
A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT = 24 # macro
REG_A6XX_SP_CS_PVT_MEM_ADDR = 0x0000a9b7 # macro
REG_A6XX_SP_CS_PVT_MEM_SIZE = 0x0000a9b9 # macro
A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK = 0x0003ffff # macro
A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT = 0 # macro
A6XX_SP_CS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT = 0x80000000 # macro
REG_A6XX_SP_CS_TEX_COUNT = 0x0000a9ba # macro
REG_A6XX_SP_CS_CONFIG = 0x0000a9bb # macro
A6XX_SP_CS_CONFIG_BINDLESS_TEX = 0x00000001 # macro
A6XX_SP_CS_CONFIG_BINDLESS_SAMP = 0x00000002 # macro
A6XX_SP_CS_CONFIG_BINDLESS_IBO = 0x00000004 # macro
A6XX_SP_CS_CONFIG_BINDLESS_UBO = 0x00000008 # macro
A6XX_SP_CS_CONFIG_ENABLED = 0x00000100 # macro
A6XX_SP_CS_CONFIG_NTEX__MASK = 0x0001fe00 # macro
A6XX_SP_CS_CONFIG_NTEX__SHIFT = 9 # macro
A6XX_SP_CS_CONFIG_NSAMP__MASK = 0x003e0000 # macro
A6XX_SP_CS_CONFIG_NSAMP__SHIFT = 17 # macro
A6XX_SP_CS_CONFIG_NIBO__MASK = 0x1fc00000 # macro
A6XX_SP_CS_CONFIG_NIBO__SHIFT = 22 # macro
REG_A6XX_SP_CS_INSTRLEN = 0x0000a9bc # macro
REG_A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET = 0x0000a9bd # macro
A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK = 0x0007ffff # macro
A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT = 0 # macro
REG_A7XX_SP_CS_UNKNOWN_A9BE = 0x0000a9be # macro
REG_A7XX_SP_CS_VGPR_CONFIG = 0x0000a9c5 # macro
REG_A6XX_SP_CS_CNTL_0 = 0x0000a9c2 # macro
A6XX_SP_CS_CNTL_0_WGIDCONSTID__MASK = 0x000000ff # macro
A6XX_SP_CS_CNTL_0_WGIDCONSTID__SHIFT = 0 # macro
A6XX_SP_CS_CNTL_0_WGSIZECONSTID__MASK = 0x0000ff00 # macro
A6XX_SP_CS_CNTL_0_WGSIZECONSTID__SHIFT = 8 # macro
A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID__MASK = 0x00ff0000 # macro
A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID__SHIFT = 16 # macro
A6XX_SP_CS_CNTL_0_LOCALIDREGID__MASK = 0xff000000 # macro
A6XX_SP_CS_CNTL_0_LOCALIDREGID__SHIFT = 24 # macro
REG_A6XX_SP_CS_CNTL_1 = 0x0000a9c3 # macro
A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__MASK = 0x000000ff # macro
A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT = 0 # macro
A6XX_SP_CS_CNTL_1_SINGLE_SP_CORE = 0x00000100 # macro
A6XX_SP_CS_CNTL_1_THREADSIZE__MASK = 0x00000200 # macro
A6XX_SP_CS_CNTL_1_THREADSIZE__SHIFT = 9 # macro
A6XX_SP_CS_CNTL_1_THREADSIZE_SCALAR = 0x00000400 # macro
REG_A7XX_SP_CS_CNTL_1 = 0x0000a9c3 # macro
A7XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__MASK = 0x000000ff # macro
A7XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT = 0 # macro
A7XX_SP_CS_CNTL_1_THREADSIZE__MASK = 0x00000100 # macro
A7XX_SP_CS_CNTL_1_THREADSIZE__SHIFT = 8 # macro
A7XX_SP_CS_CNTL_1_THREADSIZE_SCALAR = 0x00000200 # macro
A7XX_SP_CS_CNTL_1_UNK15 = 0x00008000 # macro
REG_A6XX_SP_FS_TEX_SAMP = 0x0000a9e0 # macro
REG_A6XX_SP_CS_TEX_SAMP = 0x0000a9e2 # macro
REG_A6XX_SP_FS_TEX_CONST = 0x0000a9e4 # macro
REG_A6XX_SP_CS_TEX_CONST = 0x0000a9e6 # macro
# def REG_A6XX_SP_CS_BINDLESS_BASE(i0): # macro
# return (0x0000a9e8+0x2*i0)
A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK = 0x00000003 # macro
A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT = 0 # macro
A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK = 0xfffffffffffffffc # macro
A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT = 2 # macro
# def REG_A7XX_SP_CS_BINDLESS_BASE(i0): # macro
# return (0x0000a9e8+0x2*i0)
A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK = 0x00000003 # macro
A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT = 0 # macro
A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK = 0xfffffffffffffffc # macro
A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT = 2 # macro
REG_A6XX_SP_CS_IBO = 0x0000a9f2 # macro
REG_A6XX_SP_CS_IBO_COUNT = 0x0000aa00 # macro
REG_A7XX_SP_FS_VGPR_CONFIG = 0x0000aa01 # macro
REG_A7XX_SP_PS_ALIASED_COMPONENTS_CONTROL = 0x0000aa02 # macro
A7XX_SP_PS_ALIASED_COMPONENTS_CONTROL_ENABLED = 0x00000001 # macro
REG_A7XX_SP_PS_ALIASED_COMPONENTS = 0x0000aa03 # macro
A7XX_SP_PS_ALIASED_COMPONENTS_RT0__MASK = 0x0000000f # macro
A7XX_SP_PS_ALIASED_COMPONENTS_RT0__SHIFT = 0 # macro
A7XX_SP_PS_ALIASED_COMPONENTS_RT1__MASK = 0x000000f0 # macro
A7XX_SP_PS_ALIASED_COMPONENTS_RT1__SHIFT = 4 # macro
A7XX_SP_PS_ALIASED_COMPONENTS_RT2__MASK = 0x00000f00 # macro
A7XX_SP_PS_ALIASED_COMPONENTS_RT2__SHIFT = 8 # macro
A7XX_SP_PS_ALIASED_COMPONENTS_RT3__MASK = 0x0000f000 # macro
A7XX_SP_PS_ALIASED_COMPONENTS_RT3__SHIFT = 12 # macro
A7XX_SP_PS_ALIASED_COMPONENTS_RT4__MASK = 0x000f0000 # macro
A7XX_SP_PS_ALIASED_COMPONENTS_RT4__SHIFT = 16 # macro
A7XX_SP_PS_ALIASED_COMPONENTS_RT5__MASK = 0x00f00000 # macro
A7XX_SP_PS_ALIASED_COMPONENTS_RT5__SHIFT = 20 # macro
A7XX_SP_PS_ALIASED_COMPONENTS_RT6__MASK = 0x0f000000 # macro
A7XX_SP_PS_ALIASED_COMPONENTS_RT6__SHIFT = 24 # macro
A7XX_SP_PS_ALIASED_COMPONENTS_RT7__MASK = 0xf0000000 # macro
A7XX_SP_PS_ALIASED_COMPONENTS_RT7__SHIFT = 28 # macro
REG_A6XX_SP_UNKNOWN_AAF2 = 0x0000aaf2 # macro
REG_A6XX_SP_MODE_CONTROL = 0x0000ab00 # macro
A6XX_SP_MODE_CONTROL_CONSTANT_DEMOTION_ENABLE = 0x00000001 # macro
A6XX_SP_MODE_CONTROL_ISAMMODE__MASK = 0x00000006 # macro
A6XX_SP_MODE_CONTROL_ISAMMODE__SHIFT = 1 # macro
A6XX_SP_MODE_CONTROL_SHARED_CONSTS_ENABLE = 0x00000008 # macro
REG_A7XX_SP_UNKNOWN_AB01 = 0x0000ab01 # macro
REG_A7XX_SP_UNKNOWN_AB02 = 0x0000ab02 # macro
REG_A6XX_SP_FS_CONFIG = 0x0000ab04 # macro
A6XX_SP_FS_CONFIG_BINDLESS_TEX = 0x00000001 # macro
A6XX_SP_FS_CONFIG_BINDLESS_SAMP = 0x00000002 # macro
A6XX_SP_FS_CONFIG_BINDLESS_IBO = 0x00000004 # macro
A6XX_SP_FS_CONFIG_BINDLESS_UBO = 0x00000008 # macro
A6XX_SP_FS_CONFIG_ENABLED = 0x00000100 # macro
A6XX_SP_FS_CONFIG_NTEX__MASK = 0x0001fe00 # macro
A6XX_SP_FS_CONFIG_NTEX__SHIFT = 9 # macro
A6XX_SP_FS_CONFIG_NSAMP__MASK = 0x003e0000 # macro
A6XX_SP_FS_CONFIG_NSAMP__SHIFT = 17 # macro
A6XX_SP_FS_CONFIG_NIBO__MASK = 0x1fc00000 # macro
A6XX_SP_FS_CONFIG_NIBO__SHIFT = 22 # macro
REG_A6XX_SP_FS_INSTRLEN = 0x0000ab05 # macro
# def REG_A6XX_SP_BINDLESS_BASE(i0): # macro
# return (0x0000ab10+0x2*i0)
A6XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK = 0x00000003 # macro
A6XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT = 0 # macro
A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK = 0xfffffffffffffffc # macro
A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT = 2 # macro
# def REG_A7XX_SP_BINDLESS_BASE(i0): # macro
# return (0x0000ab0a+0x2*i0)
A7XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK = 0x00000003 # macro
A7XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT = 0 # macro
A7XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK = 0xfffffffffffffffc # macro
A7XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT = 2 # macro
REG_A6XX_SP_IBO = 0x0000ab1a # macro
REG_A6XX_SP_IBO_COUNT = 0x0000ab20 # macro
REG_A7XX_SP_UNKNOWN_AB22 = 0x0000ab22 # macro
REG_A6XX_SP_2D_DST_FORMAT = 0x0000acc0 # macro
A6XX_SP_2D_DST_FORMAT_NORM = 0x00000001 # macro
A6XX_SP_2D_DST_FORMAT_SINT = 0x00000002 # macro
A6XX_SP_2D_DST_FORMAT_UINT = 0x00000004 # macro
A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__MASK = 0x000007f8 # macro
A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__SHIFT = 3 # macro
A6XX_SP_2D_DST_FORMAT_SRGB = 0x00000800 # macro
A6XX_SP_2D_DST_FORMAT_MASK__MASK = 0x0000f000 # macro
A6XX_SP_2D_DST_FORMAT_MASK__SHIFT = 12 # macro
REG_A7XX_SP_2D_DST_FORMAT = 0x0000a9bf # macro
A7XX_SP_2D_DST_FORMAT_NORM = 0x00000001 # macro
A7XX_SP_2D_DST_FORMAT_SINT = 0x00000002 # macro
A7XX_SP_2D_DST_FORMAT_UINT = 0x00000004 # macro
A7XX_SP_2D_DST_FORMAT_COLOR_FORMAT__MASK = 0x000007f8 # macro
A7XX_SP_2D_DST_FORMAT_COLOR_FORMAT__SHIFT = 3 # macro
A7XX_SP_2D_DST_FORMAT_SRGB = 0x00000800 # macro
A7XX_SP_2D_DST_FORMAT_MASK__MASK = 0x0000f000 # macro
A7XX_SP_2D_DST_FORMAT_MASK__SHIFT = 12 # macro
REG_A6XX_SP_DBG_ECO_CNTL = 0x0000ae00 # macro
REG_A6XX_SP_ADDR_MODE_CNTL = 0x0000ae01 # macro
REG_A6XX_SP_NC_MODE_CNTL = 0x0000ae02 # macro
REG_A6XX_SP_CHICKEN_BITS = 0x0000ae03 # macro
REG_A6XX_SP_FLOAT_CNTL = 0x0000ae04 # macro
A6XX_SP_FLOAT_CNTL_F16_NO_INF = 0x00000008 # macro
REG_A7XX_SP_UNKNOWN_AE06 = 0x0000ae06 # macro
REG_A7XX_SP_UNKNOWN_AE08 = 0x0000ae08 # macro
REG_A7XX_SP_UNKNOWN_AE09 = 0x0000ae09 # macro
REG_A7XX_SP_UNKNOWN_AE0A = 0x0000ae0a # macro
REG_A6XX_SP_PERFCTR_ENABLE = 0x0000ae0f # macro
A6XX_SP_PERFCTR_ENABLE_VS = 0x00000001 # macro
A6XX_SP_PERFCTR_ENABLE_HS = 0x00000002 # macro
A6XX_SP_PERFCTR_ENABLE_DS = 0x00000004 # macro
A6XX_SP_PERFCTR_ENABLE_GS = 0x00000008 # macro
A6XX_SP_PERFCTR_ENABLE_FS = 0x00000010 # macro
A6XX_SP_PERFCTR_ENABLE_CS = 0x00000020 # macro
# def REG_A6XX_SP_PERFCTR_SP_SEL(i0): # macro
# return (0x0000ae10+0x1*i0)
# def REG_A7XX_SP_PERFCTR_HLSQ_SEL(i0): # macro
# return (0x0000ae60+0x1*i0)
REG_A7XX_SP_UNKNOWN_AE6A = 0x0000ae6a # macro
REG_A7XX_SP_UNKNOWN_AE6B = 0x0000ae6b # macro
REG_A7XX_SP_UNKNOWN_AE6C = 0x0000ae6c # macro
REG_A7XX_SP_READ_SEL = 0x0000ae6d # macro
A7XX_SP_READ_SEL_LOCATION__MASK = 0x000c0000 # macro
A7XX_SP_READ_SEL_LOCATION__SHIFT = 18 # macro
A7XX_SP_READ_SEL_PIPE__MASK = 0x00030000 # macro
A7XX_SP_READ_SEL_PIPE__SHIFT = 16 # macro
A7XX_SP_READ_SEL_STATETYPE__MASK = 0x0000ff00 # macro
A7XX_SP_READ_SEL_STATETYPE__SHIFT = 8 # macro
A7XX_SP_READ_SEL_USPTP__MASK = 0x000000f0 # macro
A7XX_SP_READ_SEL_USPTP__SHIFT = 4 # macro
A7XX_SP_READ_SEL_SPTP__MASK = 0x0000000f # macro
A7XX_SP_READ_SEL_SPTP__SHIFT = 0 # macro
REG_A7XX_SP_DBG_CNTL = 0x0000ae71 # macro
REG_A7XX_SP_UNKNOWN_AE73 = 0x0000ae73 # macro
# def REG_A7XX_SP_PERFCTR_SP_SEL(i0): # macro
# return (0x0000ae80+0x1*i0)
REG_A6XX_SP_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE = 0x0000be22 # macro
REG_A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR = 0x0000b180 # macro
REG_A6XX_SP_UNKNOWN_B182 = 0x0000b182 # macro
REG_A6XX_SP_UNKNOWN_B183 = 0x0000b183 # macro
REG_A6XX_SP_UNKNOWN_B190 = 0x0000b190 # macro
REG_A6XX_SP_UNKNOWN_B191 = 0x0000b191 # macro
REG_A6XX_SP_TP_RAS_MSAA_CNTL = 0x0000b300 # macro
A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK = 0x00000003 # macro
A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT = 0 # macro
A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__MASK = 0x0000000c # macro
A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__SHIFT = 2 # macro
REG_A6XX_SP_TP_DEST_MSAA_CNTL = 0x0000b301 # macro
A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__MASK = 0x00000003 # macro
A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT = 0 # macro
A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE = 0x00000004 # macro
REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR = 0x0000b302 # macro
REG_A6XX_SP_TP_SAMPLE_CONFIG = 0x0000b304 # macro
A6XX_SP_TP_SAMPLE_CONFIG_UNK0 = 0x00000001 # macro
A6XX_SP_TP_SAMPLE_CONFIG_LOCATION_ENABLE = 0x00000002 # macro
REG_A6XX_SP_TP_SAMPLE_LOCATION_0 = 0x0000b305 # macro
A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK = 0x0000000f # macro
A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT = 0 # macro
A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK = 0x000000f0 # macro
A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT = 4 # macro
A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK = 0x00000f00 # macro
A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT = 8 # macro
A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK = 0x0000f000 # macro
A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT = 12 # macro
A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK = 0x000f0000 # macro
A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT = 16 # macro
A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK = 0x00f00000 # macro
A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT = 20 # macro
A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK = 0x0f000000 # macro
A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT = 24 # macro
A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK = 0xf0000000 # macro
A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT = 28 # macro
REG_A6XX_SP_TP_SAMPLE_LOCATION_1 = 0x0000b306 # macro
A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK = 0x0000000f # macro
A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT = 0 # macro
A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK = 0x000000f0 # macro
A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT = 4 # macro
A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK = 0x00000f00 # macro
A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT = 8 # macro
A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK = 0x0000f000 # macro
A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT = 12 # macro
A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK = 0x000f0000 # macro
A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT = 16 # macro
A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK = 0x00f00000 # macro
A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT = 20 # macro
A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK = 0x0f000000 # macro
A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT = 24 # macro
A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK = 0xf0000000 # macro
A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT = 28 # macro
REG_A6XX_SP_TP_WINDOW_OFFSET = 0x0000b307 # macro
A6XX_SP_TP_WINDOW_OFFSET_X__MASK = 0x00003fff # macro
A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT = 0 # macro
A6XX_SP_TP_WINDOW_OFFSET_Y__MASK = 0x3fff0000 # macro
A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT = 16 # macro
REG_A6XX_SP_TP_MODE_CNTL = 0x0000b309 # macro
A6XX_SP_TP_MODE_CNTL_ISAMMODE__MASK = 0x00000003 # macro
A6XX_SP_TP_MODE_CNTL_ISAMMODE__SHIFT = 0 # macro
A6XX_SP_TP_MODE_CNTL_UNK3__MASK = 0x000000fc # macro
A6XX_SP_TP_MODE_CNTL_UNK3__SHIFT = 2 # macro
REG_A7XX_SP_UNKNOWN_B310 = 0x0000b310 # macro
REG_A6XX_SP_PS_2D_SRC_INFO = 0x0000b4c0 # macro
A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK = 0x000000ff # macro
A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT = 0 # macro
A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK = 0x00000300 # macro
A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT = 8 # macro
A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK = 0x00000c00 # macro
A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT = 10 # macro
A6XX_SP_PS_2D_SRC_INFO_FLAGS = 0x00001000 # macro
A6XX_SP_PS_2D_SRC_INFO_SRGB = 0x00002000 # macro
A6XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK = 0x0000c000 # macro
A6XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT = 14 # macro
A6XX_SP_PS_2D_SRC_INFO_FILTER = 0x00010000 # macro
A6XX_SP_PS_2D_SRC_INFO_UNK17 = 0x00020000 # macro
A6XX_SP_PS_2D_SRC_INFO_SAMPLES_AVERAGE = 0x00040000 # macro
A6XX_SP_PS_2D_SRC_INFO_UNK19 = 0x00080000 # macro
A6XX_SP_PS_2D_SRC_INFO_UNK20 = 0x00100000 # macro
A6XX_SP_PS_2D_SRC_INFO_UNK21 = 0x00200000 # macro
A6XX_SP_PS_2D_SRC_INFO_UNK22 = 0x00400000 # macro
A6XX_SP_PS_2D_SRC_INFO_UNK23__MASK = 0x07800000 # macro
A6XX_SP_PS_2D_SRC_INFO_UNK23__SHIFT = 23 # macro
A6XX_SP_PS_2D_SRC_INFO_UNK28 = 0x10000000 # macro
REG_A6XX_SP_PS_2D_SRC_SIZE = 0x0000b4c1 # macro
A6XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK = 0x00007fff # macro
A6XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT = 0 # macro
A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK = 0x3fff8000 # macro
A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT = 15 # macro
REG_A6XX_SP_PS_2D_SRC = 0x0000b4c2 # macro
REG_A6XX_SP_PS_2D_SRC_PITCH = 0x0000b4c4 # macro
A6XX_SP_PS_2D_SRC_PITCH_UNK0__MASK = 0x000001ff # macro
A6XX_SP_PS_2D_SRC_PITCH_UNK0__SHIFT = 0 # macro
A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK = 0x00fffe00 # macro
A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT = 9 # macro
REG_A7XX_SP_PS_2D_SRC_INFO = 0x0000b2c0 # macro
A7XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK = 0x000000ff # macro
A7XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT = 0 # macro
A7XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK = 0x00000300 # macro
A7XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT = 8 # macro
A7XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK = 0x00000c00 # macro
A7XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT = 10 # macro
A7XX_SP_PS_2D_SRC_INFO_FLAGS = 0x00001000 # macro
A7XX_SP_PS_2D_SRC_INFO_SRGB = 0x00002000 # macro
A7XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK = 0x0000c000 # macro
A7XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT = 14 # macro
A7XX_SP_PS_2D_SRC_INFO_FILTER = 0x00010000 # macro
A7XX_SP_PS_2D_SRC_INFO_UNK17 = 0x00020000 # macro
A7XX_SP_PS_2D_SRC_INFO_SAMPLES_AVERAGE = 0x00040000 # macro
A7XX_SP_PS_2D_SRC_INFO_UNK19 = 0x00080000 # macro
A7XX_SP_PS_2D_SRC_INFO_UNK20 = 0x00100000 # macro
A7XX_SP_PS_2D_SRC_INFO_UNK21 = 0x00200000 # macro
A7XX_SP_PS_2D_SRC_INFO_UNK22 = 0x00400000 # macro
A7XX_SP_PS_2D_SRC_INFO_UNK23__MASK = 0x07800000 # macro
A7XX_SP_PS_2D_SRC_INFO_UNK23__SHIFT = 23 # macro
A7XX_SP_PS_2D_SRC_INFO_UNK28 = 0x10000000 # macro
REG_A7XX_SP_PS_2D_SRC_SIZE = 0x0000b2c1 # macro
A7XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK = 0x00007fff # macro
A7XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT = 0 # macro
A7XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK = 0x3fff8000 # macro
A7XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT = 15 # macro
REG_A7XX_SP_PS_2D_SRC = 0x0000b2c2 # macro
REG_A7XX_SP_PS_2D_SRC_PITCH = 0x0000b2c4 # macro
A7XX_SP_PS_2D_SRC_PITCH_UNK0__MASK = 0x000001ff # macro
A7XX_SP_PS_2D_SRC_PITCH_UNK0__SHIFT = 0 # macro
A7XX_SP_PS_2D_SRC_PITCH_PITCH__MASK = 0x00fffe00 # macro
A7XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT = 9 # macro
REG_A6XX_SP_PS_2D_SRC_PLANE1 = 0x0000b4c5 # macro
REG_A6XX_SP_PS_2D_SRC_PLANE_PITCH = 0x0000b4c7 # macro
A6XX_SP_PS_2D_SRC_PLANE_PITCH__MASK = 0x00000fff # macro
A6XX_SP_PS_2D_SRC_PLANE_PITCH__SHIFT = 0 # macro
REG_A6XX_SP_PS_2D_SRC_PLANE2 = 0x0000b4c8 # macro
REG_A7XX_SP_PS_2D_SRC_PLANE1 = 0x0000b2c5 # macro
REG_A7XX_SP_PS_2D_SRC_PLANE_PITCH = 0x0000b2c7 # macro
A7XX_SP_PS_2D_SRC_PLANE_PITCH__MASK = 0x00000fff # macro
A7XX_SP_PS_2D_SRC_PLANE_PITCH__SHIFT = 0 # macro
REG_A7XX_SP_PS_2D_SRC_PLANE2 = 0x0000b2c8 # macro
REG_A6XX_SP_PS_2D_SRC_FLAGS = 0x0000b4ca # macro
REG_A6XX_SP_PS_2D_SRC_FLAGS_PITCH = 0x0000b4cc # macro
A6XX_SP_PS_2D_SRC_FLAGS_PITCH__MASK = 0x000000ff # macro
A6XX_SP_PS_2D_SRC_FLAGS_PITCH__SHIFT = 0 # macro
REG_A7XX_SP_PS_2D_SRC_FLAGS = 0x0000b2ca # macro
REG_A7XX_SP_PS_2D_SRC_FLAGS_PITCH = 0x0000b2cc # macro
A7XX_SP_PS_2D_SRC_FLAGS_PITCH__MASK = 0x000000ff # macro
A7XX_SP_PS_2D_SRC_FLAGS_PITCH__SHIFT = 0 # macro
REG_A6XX_SP_PS_UNKNOWN_B4CD = 0x0000b4cd # macro
REG_A6XX_SP_PS_UNKNOWN_B4CE = 0x0000b4ce # macro
REG_A6XX_SP_PS_UNKNOWN_B4CF = 0x0000b4cf # macro
REG_A6XX_SP_PS_UNKNOWN_B4D0 = 0x0000b4d0 # macro
REG_A6XX_SP_WINDOW_OFFSET = 0x0000b4d1 # macro
A6XX_SP_WINDOW_OFFSET_X__MASK = 0x00003fff # macro
A6XX_SP_WINDOW_OFFSET_X__SHIFT = 0 # macro
A6XX_SP_WINDOW_OFFSET_Y__MASK = 0x3fff0000 # macro
A6XX_SP_WINDOW_OFFSET_Y__SHIFT = 16 # macro
REG_A7XX_SP_PS_UNKNOWN_B4CD = 0x0000b2cd # macro
REG_A7XX_SP_PS_UNKNOWN_B4CE = 0x0000b2ce # macro
REG_A7XX_SP_PS_UNKNOWN_B4CF = 0x0000b2cf # macro
REG_A7XX_SP_PS_UNKNOWN_B4D0 = 0x0000b2d0 # macro
REG_A7XX_SP_PS_2D_WINDOW_OFFSET = 0x0000b2d1 # macro
A7XX_SP_PS_2D_WINDOW_OFFSET_X__MASK = 0x00003fff # macro
A7XX_SP_PS_2D_WINDOW_OFFSET_X__SHIFT = 0 # macro
A7XX_SP_PS_2D_WINDOW_OFFSET_Y__MASK = 0x3fff0000 # macro
A7XX_SP_PS_2D_WINDOW_OFFSET_Y__SHIFT = 16 # macro
REG_A7XX_SP_PS_UNKNOWN_B2D2 = 0x0000b2d2 # macro
REG_A7XX_SP_WINDOW_OFFSET = 0x0000ab21 # macro
A7XX_SP_WINDOW_OFFSET_X__MASK = 0x00003fff # macro
A7XX_SP_WINDOW_OFFSET_X__SHIFT = 0 # macro
A7XX_SP_WINDOW_OFFSET_Y__MASK = 0x3fff0000 # macro
A7XX_SP_WINDOW_OFFSET_Y__SHIFT = 16 # macro
REG_A6XX_TPL1_DBG_ECO_CNTL = 0x0000b600 # macro
REG_A6XX_TPL1_ADDR_MODE_CNTL = 0x0000b601 # macro
REG_A6XX_TPL1_DBG_ECO_CNTL1 = 0x0000b602 # macro
A6XX_TPL1_DBG_ECO_CNTL1_UBWC_WORKAROUND = 0x00040000 # macro
REG_A6XX_TPL1_NC_MODE_CNTL = 0x0000b604 # macro
A6XX_TPL1_NC_MODE_CNTL_MODE = 0x00000001 # macro
A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__MASK = 0x00000006 # macro
A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__SHIFT = 1 # macro
A6XX_TPL1_NC_MODE_CNTL_MIN_ACCESS_LENGTH = 0x00000008 # macro
A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__MASK = 0x00000010 # macro
A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__SHIFT = 4 # macro
A6XX_TPL1_NC_MODE_CNTL_UNK6__MASK = 0x000000c0 # macro
A6XX_TPL1_NC_MODE_CNTL_UNK6__SHIFT = 6 # macro
REG_A6XX_TPL1_UNKNOWN_B605 = 0x0000b605 # macro
REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0 = 0x0000b608 # macro
REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1 = 0x0000b609 # macro
REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2 = 0x0000b60a # macro
REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3 = 0x0000b60b # macro
REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4 = 0x0000b60c # macro
REG_A7XX_TPL1_BICUBIC_WEIGHTS_TABLE_0 = 0x0000b608 # macro
REG_A7XX_TPL1_BICUBIC_WEIGHTS_TABLE_1 = 0x0000b609 # macro
REG_A7XX_TPL1_BICUBIC_WEIGHTS_TABLE_2 = 0x0000b60a # macro
REG_A7XX_TPL1_BICUBIC_WEIGHTS_TABLE_3 = 0x0000b60b # macro
REG_A7XX_TPL1_BICUBIC_WEIGHTS_TABLE_4 = 0x0000b60c # macro
# def REG_A6XX_TPL1_PERFCTR_TP_SEL(i0): # macro
# return (0x0000b610+0x1*i0)
# def REG_A7XX_TPL1_PERFCTR_TP_SEL(i0): # macro
# return (0x0000b610+0x1*i0)
REG_A6XX_HLSQ_VS_CNTL = 0x0000b800 # macro
A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK = 0x000000ff # macro
A6XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT = 0 # macro
A6XX_HLSQ_VS_CNTL_ENABLED = 0x00000100 # macro
A6XX_HLSQ_VS_CNTL_READ_IMM_SHARED_CONSTS = 0x00000200 # macro
REG_A6XX_HLSQ_HS_CNTL = 0x0000b801 # macro
A6XX_HLSQ_HS_CNTL_CONSTLEN__MASK = 0x000000ff # macro
A6XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT = 0 # macro
A6XX_HLSQ_HS_CNTL_ENABLED = 0x00000100 # macro
A6XX_HLSQ_HS_CNTL_READ_IMM_SHARED_CONSTS = 0x00000200 # macro
REG_A6XX_HLSQ_DS_CNTL = 0x0000b802 # macro
A6XX_HLSQ_DS_CNTL_CONSTLEN__MASK = 0x000000ff # macro
A6XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT = 0 # macro
A6XX_HLSQ_DS_CNTL_ENABLED = 0x00000100 # macro
A6XX_HLSQ_DS_CNTL_READ_IMM_SHARED_CONSTS = 0x00000200 # macro
REG_A6XX_HLSQ_GS_CNTL = 0x0000b803 # macro
A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK = 0x000000ff # macro
A6XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT = 0 # macro
A6XX_HLSQ_GS_CNTL_ENABLED = 0x00000100 # macro
A6XX_HLSQ_GS_CNTL_READ_IMM_SHARED_CONSTS = 0x00000200 # macro
REG_A7XX_HLSQ_VS_CNTL = 0x0000a827 # macro
A7XX_HLSQ_VS_CNTL_CONSTLEN__MASK = 0x000000ff # macro
A7XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT = 0 # macro
A7XX_HLSQ_VS_CNTL_ENABLED = 0x00000100 # macro
A7XX_HLSQ_VS_CNTL_READ_IMM_SHARED_CONSTS = 0x00000200 # macro
REG_A7XX_HLSQ_HS_CNTL = 0x0000a83f # macro
A7XX_HLSQ_HS_CNTL_CONSTLEN__MASK = 0x000000ff # macro
A7XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT = 0 # macro
A7XX_HLSQ_HS_CNTL_ENABLED = 0x00000100 # macro
A7XX_HLSQ_HS_CNTL_READ_IMM_SHARED_CONSTS = 0x00000200 # macro
REG_A7XX_HLSQ_DS_CNTL = 0x0000a867 # macro
A7XX_HLSQ_DS_CNTL_CONSTLEN__MASK = 0x000000ff # macro
A7XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT = 0 # macro
A7XX_HLSQ_DS_CNTL_ENABLED = 0x00000100 # macro
A7XX_HLSQ_DS_CNTL_READ_IMM_SHARED_CONSTS = 0x00000200 # macro
REG_A7XX_HLSQ_GS_CNTL = 0x0000a898 # macro
A7XX_HLSQ_GS_CNTL_CONSTLEN__MASK = 0x000000ff # macro
A7XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT = 0 # macro
A7XX_HLSQ_GS_CNTL_ENABLED = 0x00000100 # macro
A7XX_HLSQ_GS_CNTL_READ_IMM_SHARED_CONSTS = 0x00000200 # macro
REG_A7XX_HLSQ_FS_UNKNOWN_A9AA = 0x0000a9aa # macro
A7XX_HLSQ_FS_UNKNOWN_A9AA_CONSTS_LOAD_DISABLE = 0x00000001 # macro
REG_A7XX_HLSQ_UNKNOWN_A9AC = 0x0000a9ac # macro
REG_A7XX_HLSQ_UNKNOWN_A9AD = 0x0000a9ad # macro
REG_A7XX_HLSQ_UNKNOWN_A9AE = 0x0000a9ae # macro
A7XX_HLSQ_UNKNOWN_A9AE_SYSVAL_REGS_COUNT__MASK = 0x000000ff # macro
A7XX_HLSQ_UNKNOWN_A9AE_SYSVAL_REGS_COUNT__SHIFT = 0 # macro
A7XX_HLSQ_UNKNOWN_A9AE_UNK8 = 0x00000100 # macro
A7XX_HLSQ_UNKNOWN_A9AE_UNK9 = 0x00000200 # macro
REG_A6XX_HLSQ_LOAD_STATE_GEOM_CMD = 0x0000b820 # macro
REG_A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR = 0x0000b821 # macro
REG_A6XX_HLSQ_LOAD_STATE_GEOM_DATA = 0x0000b823 # macro
REG_A6XX_HLSQ_FS_CNTL_0 = 0x0000b980 # macro
A6XX_HLSQ_FS_CNTL_0_THREADSIZE__MASK = 0x00000001 # macro
A6XX_HLSQ_FS_CNTL_0_THREADSIZE__SHIFT = 0 # macro
A6XX_HLSQ_FS_CNTL_0_VARYINGS = 0x00000002 # macro
A6XX_HLSQ_FS_CNTL_0_UNK2__MASK = 0x00000ffc # macro
A6XX_HLSQ_FS_CNTL_0_UNK2__SHIFT = 2 # macro
REG_A6XX_HLSQ_UNKNOWN_B981 = 0x0000b981 # macro
REG_A6XX_HLSQ_CONTROL_1_REG = 0x0000b982 # macro
A6XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK = 0x00000007 # macro
A6XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT = 0 # macro
REG_A6XX_HLSQ_CONTROL_2_REG = 0x0000b983 # macro
A6XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK = 0x000000ff # macro
A6XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT = 0 # macro
A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK = 0x0000ff00 # macro
A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT = 8 # macro
A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK = 0x00ff0000 # macro
A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT = 16 # macro
A6XX_HLSQ_CONTROL_2_REG_CENTERRHW__MASK = 0xff000000 # macro
A6XX_HLSQ_CONTROL_2_REG_CENTERRHW__SHIFT = 24 # macro
REG_A6XX_HLSQ_CONTROL_3_REG = 0x0000b984 # macro
A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK = 0x000000ff # macro
A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT = 0 # macro
A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK = 0x0000ff00 # macro
A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT = 8 # macro
A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK = 0x00ff0000 # macro
A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT = 16 # macro
A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK = 0xff000000 # macro
A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT = 24 # macro
REG_A6XX_HLSQ_CONTROL_4_REG = 0x0000b985 # macro
A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK = 0x000000ff # macro
A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT = 0 # macro
A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK = 0x0000ff00 # macro
A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT = 8 # macro
A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK = 0x00ff0000 # macro
A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT = 16 # macro
A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK = 0xff000000 # macro
A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT = 24 # macro
REG_A6XX_HLSQ_CONTROL_5_REG = 0x0000b986 # macro
A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__MASK = 0x000000ff # macro
A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__SHIFT = 0 # macro
A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__MASK = 0x0000ff00 # macro
A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__SHIFT = 8 # macro
REG_A6XX_HLSQ_CS_CNTL = 0x0000b987 # macro
A6XX_HLSQ_CS_CNTL_CONSTLEN__MASK = 0x000000ff # macro
A6XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT = 0 # macro
A6XX_HLSQ_CS_CNTL_ENABLED = 0x00000100 # macro
A6XX_HLSQ_CS_CNTL_READ_IMM_SHARED_CONSTS = 0x00000200 # macro
REG_A7XX_HLSQ_FS_CNTL_0 = 0x0000a9c6 # macro
A7XX_HLSQ_FS_CNTL_0_THREADSIZE__MASK = 0x00000001 # macro
A7XX_HLSQ_FS_CNTL_0_THREADSIZE__SHIFT = 0 # macro
A7XX_HLSQ_FS_CNTL_0_VARYINGS = 0x00000002 # macro
A7XX_HLSQ_FS_CNTL_0_UNK2__MASK = 0x00000ffc # macro
A7XX_HLSQ_FS_CNTL_0_UNK2__SHIFT = 2 # macro
REG_A7XX_HLSQ_CONTROL_1_REG = 0x0000a9c7 # macro
A7XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK = 0x00000007 # macro
A7XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT = 0 # macro
REG_A7XX_HLSQ_CONTROL_2_REG = 0x0000a9c8 # macro
A7XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK = 0x000000ff # macro
A7XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT = 0 # macro
A7XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK = 0x0000ff00 # macro
A7XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT = 8 # macro
A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK = 0x00ff0000 # macro
A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT = 16 # macro
A7XX_HLSQ_CONTROL_2_REG_CENTERRHW__MASK = 0xff000000 # macro
A7XX_HLSQ_CONTROL_2_REG_CENTERRHW__SHIFT = 24 # macro
REG_A7XX_HLSQ_CONTROL_3_REG = 0x0000a9c9 # macro
A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK = 0x000000ff # macro
A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT = 0 # macro
A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK = 0x0000ff00 # macro
A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT = 8 # macro
A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK = 0x00ff0000 # macro
A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT = 16 # macro
A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK = 0xff000000 # macro
A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT = 24 # macro
REG_A7XX_HLSQ_CONTROL_4_REG = 0x0000a9ca # macro
A7XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK = 0x000000ff # macro
A7XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT = 0 # macro
A7XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK = 0x0000ff00 # macro
A7XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT = 8 # macro
A7XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK = 0x00ff0000 # macro
A7XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT = 16 # macro
A7XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK = 0xff000000 # macro
A7XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT = 24 # macro
REG_A7XX_HLSQ_CONTROL_5_REG = 0x0000a9cb # macro
A7XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__MASK = 0x000000ff # macro
A7XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__SHIFT = 0 # macro
A7XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__MASK = 0x0000ff00 # macro
A7XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__SHIFT = 8 # macro
REG_A7XX_HLSQ_CS_CNTL = 0x0000a9cd # macro
A7XX_HLSQ_CS_CNTL_CONSTLEN__MASK = 0x000000ff # macro
A7XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT = 0 # macro
A7XX_HLSQ_CS_CNTL_ENABLED = 0x00000100 # macro
A7XX_HLSQ_CS_CNTL_READ_IMM_SHARED_CONSTS = 0x00000200 # macro
REG_A6XX_HLSQ_CS_NDRANGE_0 = 0x0000b990 # macro
A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK = 0x00000003 # macro
A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT = 0 # macro
A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK = 0x00000ffc # macro
A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT = 2 # macro
A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK = 0x003ff000 # macro
A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT = 12 # macro
A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK = 0xffc00000 # macro
A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT = 22 # macro
REG_A6XX_HLSQ_CS_NDRANGE_1 = 0x0000b991 # macro
A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK = 0xffffffff # macro
A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT = 0 # macro
REG_A6XX_HLSQ_CS_NDRANGE_2 = 0x0000b992 # macro
A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK = 0xffffffff # macro
A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT = 0 # macro
REG_A6XX_HLSQ_CS_NDRANGE_3 = 0x0000b993 # macro
A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK = 0xffffffff # macro
A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT = 0 # macro
REG_A6XX_HLSQ_CS_NDRANGE_4 = 0x0000b994 # macro
A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK = 0xffffffff # macro
A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT = 0 # macro
REG_A6XX_HLSQ_CS_NDRANGE_5 = 0x0000b995 # macro
A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK = 0xffffffff # macro
A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT = 0 # macro
REG_A6XX_HLSQ_CS_NDRANGE_6 = 0x0000b996 # macro
A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK = 0xffffffff # macro
A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT = 0 # macro
REG_A6XX_HLSQ_CS_CNTL_0 = 0x0000b997 # macro
A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK = 0x000000ff # macro
A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT = 0 # macro
A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__MASK = 0x0000ff00 # macro
A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__SHIFT = 8 # macro
A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__MASK = 0x00ff0000 # macro
A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__SHIFT = 16 # macro
A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK = 0xff000000 # macro
A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT = 24 # macro
REG_A6XX_HLSQ_CS_CNTL_1 = 0x0000b998 # macro
A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__MASK = 0x000000ff # macro
A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT = 0 # macro
A6XX_HLSQ_CS_CNTL_1_SINGLE_SP_CORE = 0x00000100 # macro
A6XX_HLSQ_CS_CNTL_1_THREADSIZE__MASK = 0x00000200 # macro
A6XX_HLSQ_CS_CNTL_1_THREADSIZE__SHIFT = 9 # macro
A6XX_HLSQ_CS_CNTL_1_THREADSIZE_SCALAR = 0x00000400 # macro
REG_A6XX_HLSQ_CS_KERNEL_GROUP_X = 0x0000b999 # macro
REG_A6XX_HLSQ_CS_KERNEL_GROUP_Y = 0x0000b99a # macro
REG_A6XX_HLSQ_CS_KERNEL_GROUP_Z = 0x0000b99b # macro
REG_A7XX_HLSQ_CS_NDRANGE_0 = 0x0000a9d4 # macro
A7XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK = 0x00000003 # macro
A7XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT = 0 # macro
A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK = 0x00000ffc # macro
A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT = 2 # macro
A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK = 0x003ff000 # macro
A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT = 12 # macro
A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK = 0xffc00000 # macro
A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT = 22 # macro
REG_A7XX_HLSQ_CS_NDRANGE_1 = 0x0000a9d5 # macro
A7XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK = 0xffffffff # macro
A7XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT = 0 # macro
REG_A7XX_HLSQ_CS_NDRANGE_2 = 0x0000a9d6 # macro
A7XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK = 0xffffffff # macro
A7XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT = 0 # macro
REG_A7XX_HLSQ_CS_NDRANGE_3 = 0x0000a9d7 # macro
A7XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK = 0xffffffff # macro
A7XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT = 0 # macro
REG_A7XX_HLSQ_CS_NDRANGE_4 = 0x0000a9d8 # macro
A7XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK = 0xffffffff # macro
A7XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT = 0 # macro
REG_A7XX_HLSQ_CS_NDRANGE_5 = 0x0000a9d9 # macro
A7XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK = 0xffffffff # macro
A7XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT = 0 # macro
REG_A7XX_HLSQ_CS_NDRANGE_6 = 0x0000a9da # macro
A7XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK = 0xffffffff # macro
A7XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT = 0 # macro
REG_A7XX_HLSQ_CS_KERNEL_GROUP_X = 0x0000a9dc # macro
REG_A7XX_HLSQ_CS_KERNEL_GROUP_Y = 0x0000a9dd # macro
REG_A7XX_HLSQ_CS_KERNEL_GROUP_Z = 0x0000a9de # macro
REG_A7XX_HLSQ_CS_CNTL_1 = 0x0000a9db # macro
A7XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__MASK = 0x000000ff # macro
A7XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT = 0 # macro
A7XX_HLSQ_CS_CNTL_1_THREADSIZE__MASK = 0x00000200 # macro
A7XX_HLSQ_CS_CNTL_1_THREADSIZE__SHIFT = 9 # macro
A7XX_HLSQ_CS_CNTL_1_UNK11 = 0x00000800 # macro
A7XX_HLSQ_CS_CNTL_1_UNK22 = 0x00400000 # macro
A7XX_HLSQ_CS_CNTL_1_UNK26 = 0x04000000 # macro
A7XX_HLSQ_CS_CNTL_1_YALIGN__MASK = 0x78000000 # macro
A7XX_HLSQ_CS_CNTL_1_YALIGN__SHIFT = 27 # macro
REG_A7XX_HLSQ_CS_LOCAL_SIZE = 0x0000a9df # macro
A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEX__MASK = 0x00000ffc # macro
A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEX__SHIFT = 2 # macro
A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEY__MASK = 0x003ff000 # macro
A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEY__SHIFT = 12 # macro
A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEZ__MASK = 0xffc00000 # macro
A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEZ__SHIFT = 22 # macro
REG_A6XX_HLSQ_LOAD_STATE_FRAG_CMD = 0x0000b9a0 # macro
REG_A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR = 0x0000b9a1 # macro
REG_A6XX_HLSQ_LOAD_STATE_FRAG_DATA = 0x0000b9a3 # macro
# def REG_A6XX_HLSQ_CS_BINDLESS_BASE(i0): # macro
# return (0x0000b9c0+0x2*i0)
A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK = 0x00000003 # macro
A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT = 0 # macro
A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK = 0xfffffffffffffffc # macro
A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT = 2 # macro
REG_A6XX_HLSQ_CS_UNKNOWN_B9D0 = 0x0000b9d0 # macro
A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE__MASK = 0x0000001f # macro
A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE__SHIFT = 0 # macro
A6XX_HLSQ_CS_UNKNOWN_B9D0_UNK5 = 0x00000020 # macro
A6XX_HLSQ_CS_UNKNOWN_B9D0_UNK6 = 0x00000040 # macro
REG_A6XX_HLSQ_DRAW_CMD = 0x0000bb00 # macro
A6XX_HLSQ_DRAW_CMD_STATE_ID__MASK = 0x000000ff # macro
A6XX_HLSQ_DRAW_CMD_STATE_ID__SHIFT = 0 # macro
REG_A6XX_HLSQ_DISPATCH_CMD = 0x0000bb01 # macro
A6XX_HLSQ_DISPATCH_CMD_STATE_ID__MASK = 0x000000ff # macro
A6XX_HLSQ_DISPATCH_CMD_STATE_ID__SHIFT = 0 # macro
REG_A6XX_HLSQ_EVENT_CMD = 0x0000bb02 # macro
A6XX_HLSQ_EVENT_CMD_STATE_ID__MASK = 0x00ff0000 # macro
A6XX_HLSQ_EVENT_CMD_STATE_ID__SHIFT = 16 # macro
A6XX_HLSQ_EVENT_CMD_EVENT__MASK = 0x0000007f # macro
A6XX_HLSQ_EVENT_CMD_EVENT__SHIFT = 0 # macro
REG_A6XX_HLSQ_INVALIDATE_CMD = 0x0000bb08 # macro
A6XX_HLSQ_INVALIDATE_CMD_VS_STATE = 0x00000001 # macro
A6XX_HLSQ_INVALIDATE_CMD_HS_STATE = 0x00000002 # macro
A6XX_HLSQ_INVALIDATE_CMD_DS_STATE = 0x00000004 # macro
A6XX_HLSQ_INVALIDATE_CMD_GS_STATE = 0x00000008 # macro
A6XX_HLSQ_INVALIDATE_CMD_FS_STATE = 0x00000010 # macro
A6XX_HLSQ_INVALIDATE_CMD_CS_STATE = 0x00000020 # macro
A6XX_HLSQ_INVALIDATE_CMD_CS_IBO = 0x00000040 # macro
A6XX_HLSQ_INVALIDATE_CMD_GFX_IBO = 0x00000080 # macro
A6XX_HLSQ_INVALIDATE_CMD_CS_SHARED_CONST = 0x00080000 # macro
A6XX_HLSQ_INVALIDATE_CMD_GFX_SHARED_CONST = 0x00000100 # macro
A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__MASK = 0x00003e00 # macro
A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__SHIFT = 9 # macro
A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__MASK = 0x0007c000 # macro
A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__SHIFT = 14 # macro
REG_A7XX_HLSQ_DRAW_CMD = 0x0000ab1c # macro
A7XX_HLSQ_DRAW_CMD_STATE_ID__MASK = 0x000000ff # macro
A7XX_HLSQ_DRAW_CMD_STATE_ID__SHIFT = 0 # macro
REG_A7XX_HLSQ_DISPATCH_CMD = 0x0000ab1d # macro
A7XX_HLSQ_DISPATCH_CMD_STATE_ID__MASK = 0x000000ff # macro
A7XX_HLSQ_DISPATCH_CMD_STATE_ID__SHIFT = 0 # macro
REG_A7XX_HLSQ_EVENT_CMD = 0x0000ab1e # macro
A7XX_HLSQ_EVENT_CMD_STATE_ID__MASK = 0x00ff0000 # macro
A7XX_HLSQ_EVENT_CMD_STATE_ID__SHIFT = 16 # macro
A7XX_HLSQ_EVENT_CMD_EVENT__MASK = 0x0000007f # macro
A7XX_HLSQ_EVENT_CMD_EVENT__SHIFT = 0 # macro
REG_A7XX_HLSQ_INVALIDATE_CMD = 0x0000ab1f # macro
A7XX_HLSQ_INVALIDATE_CMD_VS_STATE = 0x00000001 # macro
A7XX_HLSQ_INVALIDATE_CMD_HS_STATE = 0x00000002 # macro
A7XX_HLSQ_INVALIDATE_CMD_DS_STATE = 0x00000004 # macro
A7XX_HLSQ_INVALIDATE_CMD_GS_STATE = 0x00000008 # macro
A7XX_HLSQ_INVALIDATE_CMD_FS_STATE = 0x00000010 # macro
A7XX_HLSQ_INVALIDATE_CMD_CS_STATE = 0x00000020 # macro
A7XX_HLSQ_INVALIDATE_CMD_CS_IBO = 0x00000040 # macro
A7XX_HLSQ_INVALIDATE_CMD_GFX_IBO = 0x00000080 # macro
A7XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__MASK = 0x0001fe00 # macro
A7XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__SHIFT = 9 # macro
A7XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__MASK = 0x01fe0000 # macro
A7XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__SHIFT = 17 # macro
REG_A6XX_HLSQ_FS_CNTL = 0x0000bb10 # macro
A6XX_HLSQ_FS_CNTL_CONSTLEN__MASK = 0x000000ff # macro
A6XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT = 0 # macro
A6XX_HLSQ_FS_CNTL_ENABLED = 0x00000100 # macro
A6XX_HLSQ_FS_CNTL_READ_IMM_SHARED_CONSTS = 0x00000200 # macro
REG_A7XX_HLSQ_FS_CNTL = 0x0000ab03 # macro
A7XX_HLSQ_FS_CNTL_CONSTLEN__MASK = 0x000000ff # macro
A7XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT = 0 # macro
A7XX_HLSQ_FS_CNTL_ENABLED = 0x00000100 # macro
A7XX_HLSQ_FS_CNTL_READ_IMM_SHARED_CONSTS = 0x00000200 # macro
# def REG_A7XX_HLSQ_SHARED_CONSTS_IMM(i0): # macro
# return (0x0000ab40+0x1*i0)
REG_A6XX_HLSQ_SHARED_CONSTS = 0x0000bb11 # macro
A6XX_HLSQ_SHARED_CONSTS_ENABLE = 0x00000001 # macro
# def REG_A6XX_HLSQ_BINDLESS_BASE(i0): # macro
# return (0x0000bb20+0x2*i0)
A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK = 0x00000003 # macro
A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT = 0 # macro
A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK = 0xfffffffffffffffc # macro
A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT = 2 # macro
REG_A6XX_HLSQ_2D_EVENT_CMD = 0x0000bd80 # macro
A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__MASK = 0x0000ff00 # macro
A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__SHIFT = 8 # macro
A6XX_HLSQ_2D_EVENT_CMD_EVENT__MASK = 0x0000007f # macro
A6XX_HLSQ_2D_EVENT_CMD_EVENT__SHIFT = 0 # macro
REG_A6XX_HLSQ_UNKNOWN_BE00 = 0x0000be00 # macro
REG_A6XX_HLSQ_UNKNOWN_BE01 = 0x0000be01 # macro
REG_A6XX_HLSQ_DBG_ECO_CNTL = 0x0000be04 # macro
REG_A6XX_HLSQ_ADDR_MODE_CNTL = 0x0000be05 # macro
REG_A6XX_HLSQ_UNKNOWN_BE08 = 0x0000be08 # macro
# def REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL(i0): # macro
# return (0x0000be10+0x1*i0)
REG_A6XX_HLSQ_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE = 0x0000be22 # macro
REG_A7XX_SP_AHB_READ_APERTURE = 0x0000c000 # macro
REG_A7XX_SP_UNKNOWN_0CE2 = 0x00000ce2 # macro
REG_A7XX_SP_UNKNOWN_0CE4 = 0x00000ce4 # macro
REG_A7XX_SP_UNKNOWN_0CE6 = 0x00000ce6 # macro
REG_A6XX_CP_EVENT_START = 0x0000d600 # macro
A6XX_CP_EVENT_START_STATE_ID__MASK = 0x000000ff # macro
A6XX_CP_EVENT_START_STATE_ID__SHIFT = 0 # macro
REG_A6XX_CP_EVENT_END = 0x0000d601 # macro
A6XX_CP_EVENT_END_STATE_ID__MASK = 0x000000ff # macro
A6XX_CP_EVENT_END_STATE_ID__SHIFT = 0 # macro
REG_A6XX_CP_2D_EVENT_START = 0x0000d700 # macro
A6XX_CP_2D_EVENT_START_STATE_ID__MASK = 0x000000ff # macro
A6XX_CP_2D_EVENT_START_STATE_ID__SHIFT = 0 # macro
REG_A6XX_CP_2D_EVENT_END = 0x0000d701 # macro
A6XX_CP_2D_EVENT_END_STATE_ID__MASK = 0x000000ff # macro
A6XX_CP_2D_EVENT_END_STATE_ID__SHIFT = 0 # macro
REG_A6XX_TEX_SAMP_0 = 0x00000000 # macro
A6XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR = 0x00000001 # macro
A6XX_TEX_SAMP_0_XY_MAG__MASK = 0x00000006 # macro
A6XX_TEX_SAMP_0_XY_MAG__SHIFT = 1 # macro
A6XX_TEX_SAMP_0_XY_MIN__MASK = 0x00000018 # macro
A6XX_TEX_SAMP_0_XY_MIN__SHIFT = 3 # macro
A6XX_TEX_SAMP_0_WRAP_S__MASK = 0x000000e0 # macro
A6XX_TEX_SAMP_0_WRAP_S__SHIFT = 5 # macro
A6XX_TEX_SAMP_0_WRAP_T__MASK = 0x00000700 # macro
A6XX_TEX_SAMP_0_WRAP_T__SHIFT = 8 # macro
A6XX_TEX_SAMP_0_WRAP_R__MASK = 0x00003800 # macro
A6XX_TEX_SAMP_0_WRAP_R__SHIFT = 11 # macro
A6XX_TEX_SAMP_0_ANISO__MASK = 0x0001c000 # macro
A6XX_TEX_SAMP_0_ANISO__SHIFT = 14 # macro
A6XX_TEX_SAMP_0_LOD_BIAS__MASK = 0xfff80000 # macro
A6XX_TEX_SAMP_0_LOD_BIAS__SHIFT = 19 # macro
REG_A6XX_TEX_SAMP_1 = 0x00000001 # macro
A6XX_TEX_SAMP_1_CLAMPENABLE = 0x00000001 # macro
A6XX_TEX_SAMP_1_COMPARE_FUNC__MASK = 0x0000000e # macro
A6XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT = 1 # macro
A6XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF = 0x00000010 # macro
A6XX_TEX_SAMP_1_UNNORM_COORDS = 0x00000020 # macro
A6XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR = 0x00000040 # macro
A6XX_TEX_SAMP_1_MAX_LOD__MASK = 0x000fff00 # macro
A6XX_TEX_SAMP_1_MAX_LOD__SHIFT = 8 # macro
A6XX_TEX_SAMP_1_MIN_LOD__MASK = 0xfff00000 # macro
A6XX_TEX_SAMP_1_MIN_LOD__SHIFT = 20 # macro
REG_A6XX_TEX_SAMP_2 = 0x00000002 # macro
A6XX_TEX_SAMP_2_REDUCTION_MODE__MASK = 0x00000003 # macro
A6XX_TEX_SAMP_2_REDUCTION_MODE__SHIFT = 0 # macro
A6XX_TEX_SAMP_2_CHROMA_LINEAR = 0x00000020 # macro
A6XX_TEX_SAMP_2_BCOLOR__MASK = 0xffffff80 # macro
A6XX_TEX_SAMP_2_BCOLOR__SHIFT = 7 # macro
REG_A6XX_TEX_SAMP_3 = 0x00000003 # macro
REG_A6XX_TEX_CONST_0 = 0x00000000 # macro
A6XX_TEX_CONST_0_TILE_MODE__MASK = 0x00000003 # macro
A6XX_TEX_CONST_0_TILE_MODE__SHIFT = 0 # macro
A6XX_TEX_CONST_0_SRGB = 0x00000004 # macro
A6XX_TEX_CONST_0_SWIZ_X__MASK = 0x00000070 # macro
A6XX_TEX_CONST_0_SWIZ_X__SHIFT = 4 # macro
A6XX_TEX_CONST_0_SWIZ_Y__MASK = 0x00000380 # macro
A6XX_TEX_CONST_0_SWIZ_Y__SHIFT = 7 # macro
A6XX_TEX_CONST_0_SWIZ_Z__MASK = 0x00001c00 # macro
A6XX_TEX_CONST_0_SWIZ_Z__SHIFT = 10 # macro
A6XX_TEX_CONST_0_SWIZ_W__MASK = 0x0000e000 # macro
A6XX_TEX_CONST_0_SWIZ_W__SHIFT = 13 # macro
A6XX_TEX_CONST_0_MIPLVLS__MASK = 0x000f0000 # macro
A6XX_TEX_CONST_0_MIPLVLS__SHIFT = 16 # macro
A6XX_TEX_CONST_0_CHROMA_MIDPOINT_X = 0x00010000 # macro
A6XX_TEX_CONST_0_CHROMA_MIDPOINT_Y = 0x00040000 # macro
A6XX_TEX_CONST_0_SAMPLES__MASK = 0x00300000 # macro
A6XX_TEX_CONST_0_SAMPLES__SHIFT = 20 # macro
A6XX_TEX_CONST_0_FMT__MASK = 0x3fc00000 # macro
A6XX_TEX_CONST_0_FMT__SHIFT = 22 # macro
A6XX_TEX_CONST_0_SWAP__MASK = 0xc0000000 # macro
A6XX_TEX_CONST_0_SWAP__SHIFT = 30 # macro
REG_A6XX_TEX_CONST_1 = 0x00000001 # macro
A6XX_TEX_CONST_1_WIDTH__MASK = 0x00007fff # macro
A6XX_TEX_CONST_1_WIDTH__SHIFT = 0 # macro
A6XX_TEX_CONST_1_HEIGHT__MASK = 0x3fff8000 # macro
A6XX_TEX_CONST_1_HEIGHT__SHIFT = 15 # macro
REG_A6XX_TEX_CONST_2 = 0x00000002 # macro
A6XX_TEX_CONST_2_STRUCTSIZETEXELS__MASK = 0x0000fff0 # macro
A6XX_TEX_CONST_2_STRUCTSIZETEXELS__SHIFT = 4 # macro
A6XX_TEX_CONST_2_STARTOFFSETTEXELS__MASK = 0x003f0000 # macro
A6XX_TEX_CONST_2_STARTOFFSETTEXELS__SHIFT = 16 # macro
A6XX_TEX_CONST_2_PITCHALIGN__MASK = 0x0000000f # macro
A6XX_TEX_CONST_2_PITCHALIGN__SHIFT = 0 # macro
A6XX_TEX_CONST_2_PITCH__MASK = 0x1fffff80 # macro
A6XX_TEX_CONST_2_PITCH__SHIFT = 7 # macro
A6XX_TEX_CONST_2_TYPE__MASK = 0xe0000000 # macro
A6XX_TEX_CONST_2_TYPE__SHIFT = 29 # macro
REG_A6XX_TEX_CONST_3 = 0x00000003 # macro
A6XX_TEX_CONST_3_ARRAY_PITCH__MASK = 0x007fffff # macro
A6XX_TEX_CONST_3_ARRAY_PITCH__SHIFT = 0 # macro
A6XX_TEX_CONST_3_MIN_LAYERSZ__MASK = 0x07800000 # macro
A6XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT = 23 # macro
A6XX_TEX_CONST_3_TILE_ALL = 0x08000000 # macro
A6XX_TEX_CONST_3_FLAG = 0x10000000 # macro
REG_A6XX_TEX_CONST_4 = 0x00000004 # macro
A6XX_TEX_CONST_4_BASE_LO__MASK = 0xffffffe0 # macro
A6XX_TEX_CONST_4_BASE_LO__SHIFT = 5 # macro
REG_A6XX_TEX_CONST_5 = 0x00000005 # macro
A6XX_TEX_CONST_5_BASE_HI__MASK = 0x0001ffff # macro
A6XX_TEX_CONST_5_BASE_HI__SHIFT = 0 # macro
A6XX_TEX_CONST_5_DEPTH__MASK = 0x3ffe0000 # macro
A6XX_TEX_CONST_5_DEPTH__SHIFT = 17 # macro
REG_A6XX_TEX_CONST_6 = 0x00000006 # macro
A6XX_TEX_CONST_6_MIN_LOD_CLAMP__MASK = 0x00000fff # macro
A6XX_TEX_CONST_6_MIN_LOD_CLAMP__SHIFT = 0 # macro
A6XX_TEX_CONST_6_PLANE_PITCH__MASK = 0xffffff00 # macro
A6XX_TEX_CONST_6_PLANE_PITCH__SHIFT = 8 # macro
REG_A6XX_TEX_CONST_7 = 0x00000007 # macro
A6XX_TEX_CONST_7_FLAG_LO__MASK = 0xffffffe0 # macro
A6XX_TEX_CONST_7_FLAG_LO__SHIFT = 5 # macro
REG_A6XX_TEX_CONST_8 = 0x00000008 # macro
A6XX_TEX_CONST_8_FLAG_HI__MASK = 0x0001ffff # macro
A6XX_TEX_CONST_8_FLAG_HI__SHIFT = 0 # macro
REG_A6XX_TEX_CONST_9 = 0x00000009 # macro
A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__MASK = 0x0001ffff # macro
A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT = 0 # macro
REG_A6XX_TEX_CONST_10 = 0x0000000a # macro
A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__MASK = 0x0000007f # macro
A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__SHIFT = 0 # macro
A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__MASK = 0x00000f00 # macro
A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__SHIFT = 8 # macro
A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__MASK = 0x0000f000 # macro
A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__SHIFT = 12 # macro
REG_A6XX_TEX_CONST_11 = 0x0000000b # macro
REG_A6XX_TEX_CONST_12 = 0x0000000c # macro
REG_A6XX_TEX_CONST_13 = 0x0000000d # macro
REG_A6XX_TEX_CONST_14 = 0x0000000e # macro
REG_A6XX_TEX_CONST_15 = 0x0000000f # macro
REG_A6XX_UBO_0 = 0x00000000 # macro
A6XX_UBO_0_BASE_LO__MASK = 0xffffffff # macro
A6XX_UBO_0_BASE_LO__SHIFT = 0 # macro
REG_A6XX_UBO_1 = 0x00000001 # macro
A6XX_UBO_1_BASE_HI__MASK = 0x0001ffff # macro
A6XX_UBO_1_BASE_HI__SHIFT = 0 # macro
A6XX_UBO_1_SIZE__MASK = 0xfffe0000 # macro
A6XX_UBO_1_SIZE__SHIFT = 17 # macro
REG_A6XX_PDC_GPU_ENABLE_PDC = 0x00001140 # macro
REG_A6XX_PDC_GPU_SEQ_START_ADDR = 0x00001148 # macro
REG_A6XX_PDC_GPU_TCS0_CONTROL = 0x00001540 # macro
REG_A6XX_PDC_GPU_TCS0_CMD_ENABLE_BANK = 0x00001541 # macro
REG_A6XX_PDC_GPU_TCS0_CMD_WAIT_FOR_CMPL_BANK = 0x00001542 # macro
REG_A6XX_PDC_GPU_TCS0_CMD0_MSGID = 0x00001543 # macro
REG_A6XX_PDC_GPU_TCS0_CMD0_ADDR = 0x00001544 # macro
REG_A6XX_PDC_GPU_TCS0_CMD0_DATA = 0x00001545 # macro
REG_A6XX_PDC_GPU_TCS1_CONTROL = 0x00001572 # macro
REG_A6XX_PDC_GPU_TCS1_CMD_ENABLE_BANK = 0x00001573 # macro
REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK = 0x00001574 # macro
REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID = 0x00001575 # macro
REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR = 0x00001576 # macro
REG_A6XX_PDC_GPU_TCS1_CMD0_DATA = 0x00001577 # macro
REG_A6XX_PDC_GPU_TCS2_CONTROL = 0x000015a4 # macro
REG_A6XX_PDC_GPU_TCS2_CMD_ENABLE_BANK = 0x000015a5 # macro
REG_A6XX_PDC_GPU_TCS2_CMD_WAIT_FOR_CMPL_BANK = 0x000015a6 # macro
REG_A6XX_PDC_GPU_TCS2_CMD0_MSGID = 0x000015a7 # macro
REG_A6XX_PDC_GPU_TCS2_CMD0_ADDR = 0x000015a8 # macro
REG_A6XX_PDC_GPU_TCS2_CMD0_DATA = 0x000015a9 # macro
REG_A6XX_PDC_GPU_TCS3_CONTROL = 0x000015d6 # macro
REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK = 0x000015d7 # macro
REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK = 0x000015d8 # macro
REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID = 0x000015d9 # macro
REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR = 0x000015da # macro
REG_A6XX_PDC_GPU_TCS3_CMD0_DATA = 0x000015db # macro
REG_A6XX_PDC_GPU_SEQ_MEM_0 = 0x00000000 # macro
REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_A = 0x00000000 # macro
A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__MASK = 0x000000ff # macro
A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__SHIFT = 0 # macro
A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__MASK = 0x0000ff00 # macro
A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__SHIFT = 8 # macro
REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_B = 0x00000001 # macro
REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_C = 0x00000002 # macro
REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_D = 0x00000003 # macro
REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLT = 0x00000004 # macro
A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK = 0x0000003f # macro
A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT = 0 # macro
A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK = 0x00007000 # macro
A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT = 12 # macro
A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK = 0xf0000000 # macro
A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT = 28 # macro
REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLM = 0x00000005 # macro
A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK = 0x0f000000 # macro
A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT = 24 # macro
REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_0 = 0x00000008 # macro
REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_1 = 0x00000009 # macro
REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_2 = 0x0000000a # macro
REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_3 = 0x0000000b # macro
REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_0 = 0x0000000c # macro
REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_1 = 0x0000000d # macro
REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_2 = 0x0000000e # macro
REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_3 = 0x0000000f # macro
REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0 = 0x00000010 # macro
A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK = 0x0000000f # macro
A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT = 0 # macro
A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK = 0x000000f0 # macro
A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT = 4 # macro
A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK = 0x00000f00 # macro
A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT = 8 # macro
A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK = 0x0000f000 # macro
A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT = 12 # macro
A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK = 0x000f0000 # macro
A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT = 16 # macro
A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK = 0x00f00000 # macro
A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT = 20 # macro
A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK = 0x0f000000 # macro
A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT = 24 # macro
A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK = 0xf0000000 # macro
A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT = 28 # macro
REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1 = 0x00000011 # macro
A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK = 0x0000000f # macro
A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT = 0 # macro
A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK = 0x000000f0 # macro
A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT = 4 # macro
A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK = 0x00000f00 # macro
A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT = 8 # macro
A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK = 0x0000f000 # macro
A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT = 12 # macro
A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK = 0x000f0000 # macro
A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT = 16 # macro
A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK = 0x00f00000 # macro
A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT = 20 # macro
A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK = 0x0f000000 # macro
A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT = 24 # macro
A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK = 0xf0000000 # macro
A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT = 28 # macro
REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF1 = 0x0000002f # macro
REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF2 = 0x00000030 # macro
REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_0 = 0x00000001 # macro
REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_1 = 0x00000002 # macro
REG_A7XX_CX_MISC_TCM_RET_CNTL = 0x00000039 # macro
REG_A7XX_CX_MISC_SW_FUSE_VALUE = 0x00000400 # macro
A7XX_CX_MISC_SW_FUSE_VALUE_FASTBLEND = 0x00000001 # macro
A7XX_CX_MISC_SW_FUSE_VALUE_LPAC = 0x00000002 # macro
A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING = 0x00000004 # macro
# values for enumeration 'vgt_event_type'
vgt_event_type__enumvalues = {
0: 'VS_DEALLOC',
1: 'PS_DEALLOC',
2: 'VS_DONE_TS',
3: 'PS_DONE_TS',
4: 'CACHE_FLUSH_TS',
5: 'CONTEXT_DONE',
6: 'CACHE_FLUSH',
7: 'VIZQUERY_START',
7: 'HLSQ_FLUSH',
8: 'VIZQUERY_END',
9: 'SC_WAIT_WC',
9: 'WRITE_PRIMITIVE_COUNTS',
11: 'START_PRIMITIVE_CTRS',
12: 'STOP_PRIMITIVE_CTRS',
13: 'RST_PIX_CNT',
14: 'RST_VTX_CNT',
15: 'TILE_FLUSH',
16: 'STAT_EVENT',
20: 'CACHE_FLUSH_AND_INV_TS_EVENT',
21: 'ZPASS_DONE',
22: 'CACHE_FLUSH_AND_INV_EVENT',
22: 'RB_DONE_TS',
23: 'PERFCOUNTER_START',
24: 'PERFCOUNTER_STOP',
27: 'VS_FETCH_DONE',
28: 'FACENESS_FLUSH',
8: 'WT_DONE_TS',
13: 'START_FRAGMENT_CTRS',
14: 'STOP_FRAGMENT_CTRS',
15: 'START_COMPUTE_CTRS',
16: 'STOP_COMPUTE_CTRS',
17: 'FLUSH_SO_0',
18: 'FLUSH_SO_1',
19: 'FLUSH_SO_2',
20: 'FLUSH_SO_3',
24: 'PC_CCU_INVALIDATE_DEPTH',
25: 'PC_CCU_INVALIDATE_COLOR',
26: 'PC_CCU_RESOLVE_TS',
28: 'PC_CCU_FLUSH_DEPTH_TS',
29: 'PC_CCU_FLUSH_COLOR_TS',
30: 'BLIT',
36: 'LRZ_FLIP_BUFFER',
37: 'LRZ_CLEAR',
38: 'LRZ_FLUSH',
39: 'BLIT_OP_FILL_2D',
40: 'BLIT_OP_COPY_2D',
40: 'UNK_40',
42: 'BLIT_OP_SCALE_2D',
43: 'CONTEXT_DONE_2D',
44: 'UNK_2C',
45: 'UNK_2D',
49: 'CACHE_INVALIDATE',
63: 'LABEL',
1: 'DUMMY_EVENT',
24: 'CCU_INVALIDATE_DEPTH',
25: 'CCU_INVALIDATE_COLOR',
26: 'CCU_RESOLVE_CLEAN',
28: 'CCU_FLUSH_DEPTH',
29: 'CCU_FLUSH_COLOR',
30: 'CCU_RESOLVE',
31: 'CCU_END_RESOLVE_GROUP',
32: 'CCU_CLEAN_DEPTH',
33: 'CCU_CLEAN_COLOR',
48: 'CACHE_RESET',
49: 'CACHE_CLEAN',
50: 'CACHE_FLUSH7',
51: 'CACHE_INVALIDATE7',
}
VS_DEALLOC = 0
PS_DEALLOC = 1
VS_DONE_TS = 2
PS_DONE_TS = 3
CACHE_FLUSH_TS = 4
CONTEXT_DONE = 5
CACHE_FLUSH = 6
VIZQUERY_START = 7
HLSQ_FLUSH = 7
VIZQUERY_END = 8
SC_WAIT_WC = 9
WRITE_PRIMITIVE_COUNTS = 9
START_PRIMITIVE_CTRS = 11
STOP_PRIMITIVE_CTRS = 12
RST_PIX_CNT = 13
RST_VTX_CNT = 14
TILE_FLUSH = 15
STAT_EVENT = 16
CACHE_FLUSH_AND_INV_TS_EVENT = 20
ZPASS_DONE = 21
CACHE_FLUSH_AND_INV_EVENT = 22
RB_DONE_TS = 22
PERFCOUNTER_START = 23
PERFCOUNTER_STOP = 24
VS_FETCH_DONE = 27
FACENESS_FLUSH = 28
WT_DONE_TS = 8
START_FRAGMENT_CTRS = 13
STOP_FRAGMENT_CTRS = 14
START_COMPUTE_CTRS = 15
STOP_COMPUTE_CTRS = 16
FLUSH_SO_0 = 17
FLUSH_SO_1 = 18
FLUSH_SO_2 = 19
FLUSH_SO_3 = 20
PC_CCU_INVALIDATE_DEPTH = 24
PC_CCU_INVALIDATE_COLOR = 25
PC_CCU_RESOLVE_TS = 26
PC_CCU_FLUSH_DEPTH_TS = 28
PC_CCU_FLUSH_COLOR_TS = 29
BLIT = 30
LRZ_FLIP_BUFFER = 36
LRZ_CLEAR = 37
LRZ_FLUSH = 38
BLIT_OP_FILL_2D = 39
BLIT_OP_COPY_2D = 40
UNK_40 = 40
BLIT_OP_SCALE_2D = 42
CONTEXT_DONE_2D = 43
UNK_2C = 44
UNK_2D = 45
CACHE_INVALIDATE = 49
LABEL = 63
DUMMY_EVENT = 1
CCU_INVALIDATE_DEPTH = 24
CCU_INVALIDATE_COLOR = 25
CCU_RESOLVE_CLEAN = 26
CCU_FLUSH_DEPTH = 28
CCU_FLUSH_COLOR = 29
CCU_RESOLVE = 30
CCU_END_RESOLVE_GROUP = 31
CCU_CLEAN_DEPTH = 32
CCU_CLEAN_COLOR = 33
CACHE_RESET = 48
CACHE_CLEAN = 49
CACHE_FLUSH7 = 50
CACHE_INVALIDATE7 = 51
vgt_event_type = ctypes.c_uint32 # enum
# values for enumeration 'pc_di_primtype'
pc_di_primtype__enumvalues = {
0: 'DI_PT_NONE',
1: 'DI_PT_POINTLIST_PSIZE',
2: 'DI_PT_LINELIST',
3: 'DI_PT_LINESTRIP',
4: 'DI_PT_TRILIST',
5: 'DI_PT_TRIFAN',
6: 'DI_PT_TRISTRIP',
7: 'DI_PT_LINELOOP',
8: 'DI_PT_RECTLIST',
9: 'DI_PT_POINTLIST',
10: 'DI_PT_LINE_ADJ',
11: 'DI_PT_LINESTRIP_ADJ',
12: 'DI_PT_TRI_ADJ',
13: 'DI_PT_TRISTRIP_ADJ',
31: 'DI_PT_PATCHES0',
32: 'DI_PT_PATCHES1',
33: 'DI_PT_PATCHES2',
34: 'DI_PT_PATCHES3',
35: 'DI_PT_PATCHES4',
36: 'DI_PT_PATCHES5',
37: 'DI_PT_PATCHES6',
38: 'DI_PT_PATCHES7',
39: 'DI_PT_PATCHES8',
40: 'DI_PT_PATCHES9',
41: 'DI_PT_PATCHES10',
42: 'DI_PT_PATCHES11',
43: 'DI_PT_PATCHES12',
44: 'DI_PT_PATCHES13',
45: 'DI_PT_PATCHES14',
46: 'DI_PT_PATCHES15',
47: 'DI_PT_PATCHES16',
48: 'DI_PT_PATCHES17',
49: 'DI_PT_PATCHES18',
50: 'DI_PT_PATCHES19',
51: 'DI_PT_PATCHES20',
52: 'DI_PT_PATCHES21',
53: 'DI_PT_PATCHES22',
54: 'DI_PT_PATCHES23',
55: 'DI_PT_PATCHES24',
56: 'DI_PT_PATCHES25',
57: 'DI_PT_PATCHES26',
58: 'DI_PT_PATCHES27',
59: 'DI_PT_PATCHES28',
60: 'DI_PT_PATCHES29',
61: 'DI_PT_PATCHES30',
62: 'DI_PT_PATCHES31',
}
DI_PT_NONE = 0
DI_PT_POINTLIST_PSIZE = 1
DI_PT_LINELIST = 2
DI_PT_LINESTRIP = 3
DI_PT_TRILIST = 4
DI_PT_TRIFAN = 5
DI_PT_TRISTRIP = 6
DI_PT_LINELOOP = 7
DI_PT_RECTLIST = 8
DI_PT_POINTLIST = 9
DI_PT_LINE_ADJ = 10
DI_PT_LINESTRIP_ADJ = 11
DI_PT_TRI_ADJ = 12
DI_PT_TRISTRIP_ADJ = 13
DI_PT_PATCHES0 = 31
DI_PT_PATCHES1 = 32
DI_PT_PATCHES2 = 33
DI_PT_PATCHES3 = 34
DI_PT_PATCHES4 = 35
DI_PT_PATCHES5 = 36
DI_PT_PATCHES6 = 37
DI_PT_PATCHES7 = 38
DI_PT_PATCHES8 = 39
DI_PT_PATCHES9 = 40
DI_PT_PATCHES10 = 41
DI_PT_PATCHES11 = 42
DI_PT_PATCHES12 = 43
DI_PT_PATCHES13 = 44
DI_PT_PATCHES14 = 45
DI_PT_PATCHES15 = 46
DI_PT_PATCHES16 = 47
DI_PT_PATCHES17 = 48
DI_PT_PATCHES18 = 49
DI_PT_PATCHES19 = 50
DI_PT_PATCHES20 = 51
DI_PT_PATCHES21 = 52
DI_PT_PATCHES22 = 53
DI_PT_PATCHES23 = 54
DI_PT_PATCHES24 = 55
DI_PT_PATCHES25 = 56
DI_PT_PATCHES26 = 57
DI_PT_PATCHES27 = 58
DI_PT_PATCHES28 = 59
DI_PT_PATCHES29 = 60
DI_PT_PATCHES30 = 61
DI_PT_PATCHES31 = 62
pc_di_primtype = ctypes.c_uint32 # enum
# values for enumeration 'pc_di_src_sel'
pc_di_src_sel__enumvalues = {
0: 'DI_SRC_SEL_DMA',
1: 'DI_SRC_SEL_IMMEDIATE',
2: 'DI_SRC_SEL_AUTO_INDEX',
3: 'DI_SRC_SEL_AUTO_XFB',
}
DI_SRC_SEL_DMA = 0
DI_SRC_SEL_IMMEDIATE = 1
DI_SRC_SEL_AUTO_INDEX = 2
DI_SRC_SEL_AUTO_XFB = 3
pc_di_src_sel = ctypes.c_uint32 # enum
# values for enumeration 'pc_di_face_cull_sel'
pc_di_face_cull_sel__enumvalues = {
0: 'DI_FACE_CULL_NONE',
1: 'DI_FACE_CULL_FETCH',
2: 'DI_FACE_BACKFACE_CULL',
3: 'DI_FACE_FRONTFACE_CULL',
}
DI_FACE_CULL_NONE = 0
DI_FACE_CULL_FETCH = 1
DI_FACE_BACKFACE_CULL = 2
DI_FACE_FRONTFACE_CULL = 3
pc_di_face_cull_sel = ctypes.c_uint32 # enum
# values for enumeration 'pc_di_index_size'
pc_di_index_size__enumvalues = {
0: 'INDEX_SIZE_IGN',
0: 'INDEX_SIZE_16_BIT',
1: 'INDEX_SIZE_32_BIT',
2: 'INDEX_SIZE_8_BIT',
0: 'INDEX_SIZE_INVALID',
}
INDEX_SIZE_IGN = 0
INDEX_SIZE_16_BIT = 0
INDEX_SIZE_32_BIT = 1
INDEX_SIZE_8_BIT = 2
INDEX_SIZE_INVALID = 0
pc_di_index_size = ctypes.c_uint32 # enum
# values for enumeration 'pc_di_vis_cull_mode'
pc_di_vis_cull_mode__enumvalues = {
0: 'IGNORE_VISIBILITY',
1: 'USE_VISIBILITY',
}
IGNORE_VISIBILITY = 0
USE_VISIBILITY = 1
pc_di_vis_cull_mode = ctypes.c_uint32 # enum
# values for enumeration 'adreno_pm4_packet_type'
adreno_pm4_packet_type__enumvalues = {
0: 'CP_TYPE0_PKT',
1073741824: 'CP_TYPE1_PKT',
2147483648: 'CP_TYPE2_PKT',
3221225472: 'CP_TYPE3_PKT',
1073741824: 'CP_TYPE4_PKT',
1879048192: 'CP_TYPE7_PKT',
}
CP_TYPE0_PKT = 0
CP_TYPE1_PKT = 1073741824
CP_TYPE2_PKT = 2147483648
CP_TYPE3_PKT = 3221225472
CP_TYPE4_PKT = 1073741824
CP_TYPE7_PKT = 1879048192
adreno_pm4_packet_type = ctypes.c_uint32 # enum
# values for enumeration 'adreno_pm4_type3_packets'
adreno_pm4_type3_packets__enumvalues = {
72: 'CP_ME_INIT',
16: 'CP_NOP',
28: 'CP_PREEMPT_ENABLE',
30: 'CP_PREEMPT_TOKEN',
63: 'CP_INDIRECT_BUFFER',
87: 'CP_INDIRECT_BUFFER_CHAIN',
55: 'CP_INDIRECT_BUFFER_PFD',
38: 'CP_WAIT_FOR_IDLE',
60: 'CP_WAIT_REG_MEM',
82: 'CP_WAIT_REG_EQ',
83: 'CP_WAIT_REG_GTE',
92: 'CP_WAIT_UNTIL_READ',
93: 'CP_WAIT_IB_PFD_COMPLETE',
33: 'CP_REG_RMW',
47: 'CP_SET_BIN_DATA',
47: 'CP_SET_BIN_DATA5',
62: 'CP_REG_TO_MEM',
61: 'CP_MEM_WRITE',
79: 'CP_MEM_WRITE_CNTR',
68: 'CP_COND_EXEC',
69: 'CP_COND_WRITE',
69: 'CP_COND_WRITE5',
70: 'CP_EVENT_WRITE',
70: 'CP_EVENT_WRITE7',
88: 'CP_EVENT_WRITE_SHD',
89: 'CP_EVENT_WRITE_CFL',
91: 'CP_EVENT_WRITE_ZPD',
49: 'CP_RUN_OPENCL',
34: 'CP_DRAW_INDX',
54: 'CP_DRAW_INDX_2',
52: 'CP_DRAW_INDX_BIN',
53: 'CP_DRAW_INDX_2_BIN',
35: 'CP_VIZ_QUERY',
37: 'CP_SET_STATE',
45: 'CP_SET_CONSTANT',
39: 'CP_IM_LOAD',
43: 'CP_IM_LOAD_IMMEDIATE',
46: 'CP_LOAD_CONSTANT_CONTEXT',
59: 'CP_INVALIDATE_STATE',
74: 'CP_SET_SHADER_BASES',
80: 'CP_SET_BIN_MASK',
81: 'CP_SET_BIN_SELECT',
94: 'CP_CONTEXT_UPDATE',
64: 'CP_INTERRUPT',
44: 'CP_IM_STORE',
75: 'CP_SET_DRAW_INIT_FLAGS',
95: 'CP_SET_PROTECTED_MODE',
111: 'CP_BOOTSTRAP_UCODE',
48: 'CP_LOAD_STATE',
48: 'CP_LOAD_STATE4',
58: 'CP_COND_INDIRECT_BUFFER_PFE',
50: 'CP_COND_INDIRECT_BUFFER_PFD',
63: 'CP_INDIRECT_BUFFER_PFE',
76: 'CP_SET_BIN',
113: 'CP_TEST_TWO_MEMS',
120: 'CP_REG_WR_NO_CTXT',
17: 'CP_RECORD_PFP_TIMESTAMP',
102: 'CP_SET_SECURE_MODE',
19: 'CP_WAIT_FOR_ME',
67: 'CP_SET_DRAW_STATE',
56: 'CP_DRAW_INDX_OFFSET',
40: 'CP_DRAW_INDIRECT',
41: 'CP_DRAW_INDX_INDIRECT',
42: 'CP_DRAW_INDIRECT_MULTI',
36: 'CP_DRAW_AUTO',
25: 'CP_DRAW_PRED_ENABLE_GLOBAL',
26: 'CP_DRAW_PRED_ENABLE_LOCAL',
78: 'CP_DRAW_PRED_SET',
116: 'CP_WIDE_REG_WRITE',
77: 'CP_SCRATCH_TO_REG',
74: 'CP_REG_TO_SCRATCH',
18: 'CP_WAIT_MEM_WRITES',
71: 'CP_COND_REG_EXEC',
66: 'CP_MEM_TO_REG',
65: 'CP_EXEC_CS_INDIRECT',
51: 'CP_EXEC_CS',
80: 'CP_PERFCOUNTER_ACTION',
83: 'CP_SMMU_TABLE_UPDATE',
101: 'CP_SET_MARKER',
86: 'CP_SET_PSEUDO_REG',
92: 'CP_CONTEXT_REG_BUNCH',
28: 'CP_YIELD_ENABLE',
29: 'CP_SKIP_IB2_ENABLE_GLOBAL',
35: 'CP_SKIP_IB2_ENABLE_LOCAL',
53: 'CP_SET_SUBDRAW_SIZE',
98: 'CP_WHERE_AM_I',
100: 'CP_SET_VISIBILITY_OVERRIDE',
105: 'CP_PREEMPT_ENABLE_GLOBAL',
106: 'CP_PREEMPT_ENABLE_LOCAL',
107: 'CP_CONTEXT_SWITCH_YIELD',
108: 'CP_SET_RENDER_MODE',
110: 'CP_COMPUTE_CHECKPOINT',
115: 'CP_MEM_TO_MEM',
44: 'CP_BLIT',
57: 'CP_REG_TEST',
99: 'CP_SET_MODE',
50: 'CP_LOAD_STATE6_GEOM',
52: 'CP_LOAD_STATE6_FRAG',
54: 'CP_LOAD_STATE6',
23: 'IN_IB_PREFETCH_END',
31: 'IN_SUBBLK_PREFETCH',
32: 'IN_INSTR_PREFETCH',
71: 'IN_INSTR_MATCH',
73: 'IN_CONST_PREFETCH',
85: 'IN_INCR_UPDT_STATE',
86: 'IN_INCR_UPDT_CONST',
87: 'IN_INCR_UPDT_INSTR',
4: 'PKT4',
10: 'IN_IB_END',
11: 'IN_GMU_INTERRUPT',
15: 'IN_PREEMPT',
76: 'CP_SCRATCH_WRITE',
116: 'CP_REG_TO_MEM_OFFSET_MEM',
114: 'CP_REG_TO_MEM_OFFSET_REG',
20: 'CP_WAIT_MEM_GTE',
112: 'CP_WAIT_TWO_REGS',
117: 'CP_MEMCPY',
46: 'CP_SET_BIN_DATA5_OFFSET',
45: 'CP_SET_UNK_BIN_DATA',
84: 'CP_CONTEXT_SWITCH',
85: 'CP_SET_CTXSWITCH_IB',
109: 'CP_REG_WRITE',
80: 'CP_START_BIN',
81: 'CP_END_BIN',
108: 'CP_PREEMPT_DISABLE',
20: 'CP_WAIT_TIMESTAMP',
21: 'CP_GLOBAL_TIMESTAMP',
22: 'CP_LOCAL_TIMESTAMP',
23: 'CP_THREAD_CONTROL',
24: 'CP_RESOURCE_LIST',
27: 'CP_BV_BR_COUNT_OPS',
28: 'CP_MODIFY_TIMESTAMP',
93: 'CP_CONTEXT_REG_BUNCH2',
73: 'CP_MEM_TO_SCRATCH_MEM',
127: 'CP_FIXED_STRIDE_DRAW_TABLE',
31: 'CP_RESET_CONTEXT_STATE',
58: 'CP_CCHE_INVALIDATE',
}
CP_ME_INIT = 72
CP_NOP = 16
CP_PREEMPT_ENABLE = 28
CP_PREEMPT_TOKEN = 30
CP_INDIRECT_BUFFER = 63
CP_INDIRECT_BUFFER_CHAIN = 87
CP_INDIRECT_BUFFER_PFD = 55
CP_WAIT_FOR_IDLE = 38
CP_WAIT_REG_MEM = 60
CP_WAIT_REG_EQ = 82
CP_WAIT_REG_GTE = 83
CP_WAIT_UNTIL_READ = 92
CP_WAIT_IB_PFD_COMPLETE = 93
CP_REG_RMW = 33
CP_SET_BIN_DATA = 47
CP_SET_BIN_DATA5 = 47
CP_REG_TO_MEM = 62
CP_MEM_WRITE = 61
CP_MEM_WRITE_CNTR = 79
CP_COND_EXEC = 68
CP_COND_WRITE = 69
CP_COND_WRITE5 = 69
CP_EVENT_WRITE = 70
CP_EVENT_WRITE7 = 70
CP_EVENT_WRITE_SHD = 88
CP_EVENT_WRITE_CFL = 89
CP_EVENT_WRITE_ZPD = 91
CP_RUN_OPENCL = 49
CP_DRAW_INDX = 34
CP_DRAW_INDX_2 = 54
CP_DRAW_INDX_BIN = 52
CP_DRAW_INDX_2_BIN = 53
CP_VIZ_QUERY = 35
CP_SET_STATE = 37
CP_SET_CONSTANT = 45
CP_IM_LOAD = 39
CP_IM_LOAD_IMMEDIATE = 43
CP_LOAD_CONSTANT_CONTEXT = 46
CP_INVALIDATE_STATE = 59
CP_SET_SHADER_BASES = 74
CP_SET_BIN_MASK = 80
CP_SET_BIN_SELECT = 81
CP_CONTEXT_UPDATE = 94
CP_INTERRUPT = 64
CP_IM_STORE = 44
CP_SET_DRAW_INIT_FLAGS = 75
CP_SET_PROTECTED_MODE = 95
CP_BOOTSTRAP_UCODE = 111
CP_LOAD_STATE = 48
CP_LOAD_STATE4 = 48
CP_COND_INDIRECT_BUFFER_PFE = 58
CP_COND_INDIRECT_BUFFER_PFD = 50
CP_INDIRECT_BUFFER_PFE = 63
CP_SET_BIN = 76
CP_TEST_TWO_MEMS = 113
CP_REG_WR_NO_CTXT = 120
CP_RECORD_PFP_TIMESTAMP = 17
CP_SET_SECURE_MODE = 102
CP_WAIT_FOR_ME = 19
CP_SET_DRAW_STATE = 67
CP_DRAW_INDX_OFFSET = 56
CP_DRAW_INDIRECT = 40
CP_DRAW_INDX_INDIRECT = 41
CP_DRAW_INDIRECT_MULTI = 42
CP_DRAW_AUTO = 36
CP_DRAW_PRED_ENABLE_GLOBAL = 25
CP_DRAW_PRED_ENABLE_LOCAL = 26
CP_DRAW_PRED_SET = 78
CP_WIDE_REG_WRITE = 116
CP_SCRATCH_TO_REG = 77
CP_REG_TO_SCRATCH = 74
CP_WAIT_MEM_WRITES = 18
CP_COND_REG_EXEC = 71
CP_MEM_TO_REG = 66
CP_EXEC_CS_INDIRECT = 65
CP_EXEC_CS = 51
CP_PERFCOUNTER_ACTION = 80
CP_SMMU_TABLE_UPDATE = 83
CP_SET_MARKER = 101
CP_SET_PSEUDO_REG = 86
CP_CONTEXT_REG_BUNCH = 92
CP_YIELD_ENABLE = 28
CP_SKIP_IB2_ENABLE_GLOBAL = 29
CP_SKIP_IB2_ENABLE_LOCAL = 35
CP_SET_SUBDRAW_SIZE = 53
CP_WHERE_AM_I = 98
CP_SET_VISIBILITY_OVERRIDE = 100
CP_PREEMPT_ENABLE_GLOBAL = 105
CP_PREEMPT_ENABLE_LOCAL = 106
CP_CONTEXT_SWITCH_YIELD = 107
CP_SET_RENDER_MODE = 108
CP_COMPUTE_CHECKPOINT = 110
CP_MEM_TO_MEM = 115
CP_BLIT = 44
CP_REG_TEST = 57
CP_SET_MODE = 99
CP_LOAD_STATE6_GEOM = 50
CP_LOAD_STATE6_FRAG = 52
CP_LOAD_STATE6 = 54
IN_IB_PREFETCH_END = 23
IN_SUBBLK_PREFETCH = 31
IN_INSTR_PREFETCH = 32
IN_INSTR_MATCH = 71
IN_CONST_PREFETCH = 73
IN_INCR_UPDT_STATE = 85
IN_INCR_UPDT_CONST = 86
IN_INCR_UPDT_INSTR = 87
PKT4 = 4
IN_IB_END = 10
IN_GMU_INTERRUPT = 11
IN_PREEMPT = 15
CP_SCRATCH_WRITE = 76
CP_REG_TO_MEM_OFFSET_MEM = 116
CP_REG_TO_MEM_OFFSET_REG = 114
CP_WAIT_MEM_GTE = 20
CP_WAIT_TWO_REGS = 112
CP_MEMCPY = 117
CP_SET_BIN_DATA5_OFFSET = 46
CP_SET_UNK_BIN_DATA = 45
CP_CONTEXT_SWITCH = 84
CP_SET_CTXSWITCH_IB = 85
CP_REG_WRITE = 109
CP_START_BIN = 80
CP_END_BIN = 81
CP_PREEMPT_DISABLE = 108
CP_WAIT_TIMESTAMP = 20
CP_GLOBAL_TIMESTAMP = 21
CP_LOCAL_TIMESTAMP = 22
CP_THREAD_CONTROL = 23
CP_RESOURCE_LIST = 24
CP_BV_BR_COUNT_OPS = 27
CP_MODIFY_TIMESTAMP = 28
CP_CONTEXT_REG_BUNCH2 = 93
CP_MEM_TO_SCRATCH_MEM = 73
CP_FIXED_STRIDE_DRAW_TABLE = 127
CP_RESET_CONTEXT_STATE = 31
CP_CCHE_INVALIDATE = 58
adreno_pm4_type3_packets = ctypes.c_uint32 # enum
# values for enumeration 'adreno_state_block'
adreno_state_block__enumvalues = {
0: 'SB_VERT_TEX',
1: 'SB_VERT_MIPADDR',
2: 'SB_FRAG_TEX',
3: 'SB_FRAG_MIPADDR',
4: 'SB_VERT_SHADER',
5: 'SB_GEOM_SHADER',
6: 'SB_FRAG_SHADER',
7: 'SB_COMPUTE_SHADER',
}
SB_VERT_TEX = 0
SB_VERT_MIPADDR = 1
SB_FRAG_TEX = 2
SB_FRAG_MIPADDR = 3
SB_VERT_SHADER = 4
SB_GEOM_SHADER = 5
SB_FRAG_SHADER = 6
SB_COMPUTE_SHADER = 7
adreno_state_block = ctypes.c_uint32 # enum
# values for enumeration 'adreno_state_type'
adreno_state_type__enumvalues = {
0: 'ST_SHADER',
1: 'ST_CONSTANTS',
}
ST_SHADER = 0
ST_CONSTANTS = 1
adreno_state_type = ctypes.c_uint32 # enum
# values for enumeration 'adreno_state_src'
adreno_state_src__enumvalues = {
0: 'SS_DIRECT',
2: 'SS_INVALID_ALL_IC',
3: 'SS_INVALID_PART_IC',
4: 'SS_INDIRECT',
5: 'SS_INDIRECT_TCM',
6: 'SS_INDIRECT_STM',
}
SS_DIRECT = 0
SS_INVALID_ALL_IC = 2
SS_INVALID_PART_IC = 3
SS_INDIRECT = 4
SS_INDIRECT_TCM = 5
SS_INDIRECT_STM = 6
adreno_state_src = ctypes.c_uint32 # enum
# values for enumeration 'a4xx_state_block'
a4xx_state_block__enumvalues = {
0: 'SB4_VS_TEX',
1: 'SB4_HS_TEX',
2: 'SB4_DS_TEX',
3: 'SB4_GS_TEX',
4: 'SB4_FS_TEX',
5: 'SB4_CS_TEX',
8: 'SB4_VS_SHADER',
9: 'SB4_HS_SHADER',
10: 'SB4_DS_SHADER',
11: 'SB4_GS_SHADER',
12: 'SB4_FS_SHADER',
13: 'SB4_CS_SHADER',
14: 'SB4_SSBO',
15: 'SB4_CS_SSBO',
}
SB4_VS_TEX = 0
SB4_HS_TEX = 1
SB4_DS_TEX = 2
SB4_GS_TEX = 3
SB4_FS_TEX = 4
SB4_CS_TEX = 5
SB4_VS_SHADER = 8
SB4_HS_SHADER = 9
SB4_DS_SHADER = 10
SB4_GS_SHADER = 11
SB4_FS_SHADER = 12
SB4_CS_SHADER = 13
SB4_SSBO = 14
SB4_CS_SSBO = 15
a4xx_state_block = ctypes.c_uint32 # enum
# values for enumeration 'a4xx_state_type'
a4xx_state_type__enumvalues = {
0: 'ST4_SHADER',
1: 'ST4_CONSTANTS',
2: 'ST4_UBO',
}
ST4_SHADER = 0
ST4_CONSTANTS = 1
ST4_UBO = 2
a4xx_state_type = ctypes.c_uint32 # enum
# values for enumeration 'a4xx_state_src'
a4xx_state_src__enumvalues = {
0: 'SS4_DIRECT',
2: 'SS4_INDIRECT',
}
SS4_DIRECT = 0
SS4_INDIRECT = 2
a4xx_state_src = ctypes.c_uint32 # enum
# values for enumeration 'a6xx_state_block'
a6xx_state_block__enumvalues = {
0: 'SB6_VS_TEX',
1: 'SB6_HS_TEX',
2: 'SB6_DS_TEX',
3: 'SB6_GS_TEX',
4: 'SB6_FS_TEX',
5: 'SB6_CS_TEX',
8: 'SB6_VS_SHADER',
9: 'SB6_HS_SHADER',
10: 'SB6_DS_SHADER',
11: 'SB6_GS_SHADER',
12: 'SB6_FS_SHADER',
13: 'SB6_CS_SHADER',
14: 'SB6_IBO',
15: 'SB6_CS_IBO',
}
SB6_VS_TEX = 0
SB6_HS_TEX = 1
SB6_DS_TEX = 2
SB6_GS_TEX = 3
SB6_FS_TEX = 4
SB6_CS_TEX = 5
SB6_VS_SHADER = 8
SB6_HS_SHADER = 9
SB6_DS_SHADER = 10
SB6_GS_SHADER = 11
SB6_FS_SHADER = 12
SB6_CS_SHADER = 13
SB6_IBO = 14
SB6_CS_IBO = 15
a6xx_state_block = ctypes.c_uint32 # enum
# values for enumeration 'a6xx_state_type'
a6xx_state_type__enumvalues = {
0: 'ST6_SHADER',
1: 'ST6_CONSTANTS',
2: 'ST6_UBO',
3: 'ST6_IBO',
}
ST6_SHADER = 0
ST6_CONSTANTS = 1
ST6_UBO = 2
ST6_IBO = 3
a6xx_state_type = ctypes.c_uint32 # enum
# values for enumeration 'a6xx_state_src'
a6xx_state_src__enumvalues = {
0: 'SS6_DIRECT',
1: 'SS6_BINDLESS',
2: 'SS6_INDIRECT',
3: 'SS6_UBO',
}
SS6_DIRECT = 0
SS6_BINDLESS = 1
SS6_INDIRECT = 2
SS6_UBO = 3
a6xx_state_src = ctypes.c_uint32 # enum
# values for enumeration 'a4xx_index_size'
a4xx_index_size__enumvalues = {
0: 'INDEX4_SIZE_8_BIT',
1: 'INDEX4_SIZE_16_BIT',
2: 'INDEX4_SIZE_32_BIT',
}
INDEX4_SIZE_8_BIT = 0
INDEX4_SIZE_16_BIT = 1
INDEX4_SIZE_32_BIT = 2
a4xx_index_size = ctypes.c_uint32 # enum
# values for enumeration 'a6xx_patch_type'
a6xx_patch_type__enumvalues = {
0: 'TESS_QUADS',
1: 'TESS_TRIANGLES',
2: 'TESS_ISOLINES',
}
TESS_QUADS = 0
TESS_TRIANGLES = 1
TESS_ISOLINES = 2
a6xx_patch_type = ctypes.c_uint32 # enum
# values for enumeration 'a6xx_draw_indirect_opcode'
a6xx_draw_indirect_opcode__enumvalues = {
2: 'INDIRECT_OP_NORMAL',
4: 'INDIRECT_OP_INDEXED',
6: 'INDIRECT_OP_INDIRECT_COUNT',
7: 'INDIRECT_OP_INDIRECT_COUNT_INDEXED',
}
INDIRECT_OP_NORMAL = 2
INDIRECT_OP_INDEXED = 4
INDIRECT_OP_INDIRECT_COUNT = 6
INDIRECT_OP_INDIRECT_COUNT_INDEXED = 7
a6xx_draw_indirect_opcode = ctypes.c_uint32 # enum
# values for enumeration 'cp_draw_pred_src'
cp_draw_pred_src__enumvalues = {
5: 'PRED_SRC_MEM',
}
PRED_SRC_MEM = 5
cp_draw_pred_src = ctypes.c_uint32 # enum
# values for enumeration 'cp_draw_pred_test'
cp_draw_pred_test__enumvalues = {
0: 'NE_0_PASS',
1: 'EQ_0_PASS',
}
NE_0_PASS = 0
EQ_0_PASS = 1
cp_draw_pred_test = ctypes.c_uint32 # enum
# values for enumeration 'cp_cond_function'
cp_cond_function__enumvalues = {
0: 'WRITE_ALWAYS',
1: 'WRITE_LT',
2: 'WRITE_LE',
3: 'WRITE_EQ',
4: 'WRITE_NE',
5: 'WRITE_GE',
6: 'WRITE_GT',
}
WRITE_ALWAYS = 0
WRITE_LT = 1
WRITE_LE = 2
WRITE_EQ = 3
WRITE_NE = 4
WRITE_GE = 5
WRITE_GT = 6
cp_cond_function = ctypes.c_uint32 # enum
# values for enumeration 'poll_memory_type'
poll_memory_type__enumvalues = {
0: 'POLL_REGISTER',
1: 'POLL_MEMORY',
2: 'POLL_SCRATCH',
3: 'POLL_ON_CHIP',
}
POLL_REGISTER = 0
POLL_MEMORY = 1
POLL_SCRATCH = 2
POLL_ON_CHIP = 3
poll_memory_type = ctypes.c_uint32 # enum
# values for enumeration 'render_mode_cmd'
render_mode_cmd__enumvalues = {
1: 'BYPASS',
2: 'BINNING',
3: 'GMEM',
5: 'BLIT2D',
7: 'BLIT2DSCALE',
8: 'END2D',
}
BYPASS = 1
BINNING = 2
GMEM = 3
BLIT2D = 5
BLIT2DSCALE = 7
END2D = 8
render_mode_cmd = ctypes.c_uint32 # enum
# values for enumeration 'event_write_src'
event_write_src__enumvalues = {
0: 'EV_WRITE_USER_32B',
1: 'EV_WRITE_USER_64B',
2: 'EV_WRITE_TIMESTAMP_SUM',
3: 'EV_WRITE_ALWAYSON',
4: 'EV_WRITE_REGS_CONTENT',
}
EV_WRITE_USER_32B = 0
EV_WRITE_USER_64B = 1
EV_WRITE_TIMESTAMP_SUM = 2
EV_WRITE_ALWAYSON = 3
EV_WRITE_REGS_CONTENT = 4
event_write_src = ctypes.c_uint32 # enum
# values for enumeration 'event_write_dst'
event_write_dst__enumvalues = {
0: 'EV_DST_RAM',
1: 'EV_DST_ONCHIP',
}
EV_DST_RAM = 0
EV_DST_ONCHIP = 1
event_write_dst = ctypes.c_uint32 # enum
# values for enumeration 'cp_blit_cmd'
cp_blit_cmd__enumvalues = {
0: 'BLIT_OP_FILL',
1: 'BLIT_OP_COPY',
3: 'BLIT_OP_SCALE',
}
BLIT_OP_FILL = 0
BLIT_OP_COPY = 1
BLIT_OP_SCALE = 3
cp_blit_cmd = ctypes.c_uint32 # enum
# values for enumeration 'a6xx_marker'
a6xx_marker__enumvalues = {
1: 'RM6_BYPASS',
2: 'RM6_BINNING',
4: 'RM6_GMEM',
5: 'RM6_ENDVIS',
6: 'RM6_RESOLVE',
7: 'RM6_YIELD',
8: 'RM6_COMPUTE',
12: 'RM6_BLIT2DSCALE',
13: 'RM6_IB1LIST_START',
14: 'RM6_IB1LIST_END',
256: 'RM6_IFPC_ENABLE',
257: 'RM6_IFPC_DISABLE',
}
RM6_BYPASS = 1
RM6_BINNING = 2
RM6_GMEM = 4
RM6_ENDVIS = 5
RM6_RESOLVE = 6
RM6_YIELD = 7
RM6_COMPUTE = 8
RM6_BLIT2DSCALE = 12
RM6_IB1LIST_START = 13
RM6_IB1LIST_END = 14
RM6_IFPC_ENABLE = 256
RM6_IFPC_DISABLE = 257
a6xx_marker = ctypes.c_uint32 # enum
# values for enumeration 'pseudo_reg'
pseudo_reg__enumvalues = {
0: 'SMMU_INFO',
1: 'NON_SECURE_SAVE_ADDR',
2: 'SECURE_SAVE_ADDR',
3: 'NON_PRIV_SAVE_ADDR',
4: 'COUNTER',
8: 'DRAW_STRM_ADDRESS',
9: 'DRAW_STRM_SIZE_ADDRESS',
10: 'PRIM_STRM_ADDRESS',
11: 'UNK_STRM_ADDRESS',
12: 'UNK_STRM_SIZE_ADDRESS',
16: 'BINDLESS_BASE_0_ADDR',
17: 'BINDLESS_BASE_1_ADDR',
18: 'BINDLESS_BASE_2_ADDR',
19: 'BINDLESS_BASE_3_ADDR',
20: 'BINDLESS_BASE_4_ADDR',
21: 'BINDLESS_BASE_5_ADDR',
22: 'BINDLESS_BASE_6_ADDR',
}
SMMU_INFO = 0
NON_SECURE_SAVE_ADDR = 1
SECURE_SAVE_ADDR = 2
NON_PRIV_SAVE_ADDR = 3
COUNTER = 4
DRAW_STRM_ADDRESS = 8
DRAW_STRM_SIZE_ADDRESS = 9
PRIM_STRM_ADDRESS = 10
UNK_STRM_ADDRESS = 11
UNK_STRM_SIZE_ADDRESS = 12
BINDLESS_BASE_0_ADDR = 16
BINDLESS_BASE_1_ADDR = 17
BINDLESS_BASE_2_ADDR = 18
BINDLESS_BASE_3_ADDR = 19
BINDLESS_BASE_4_ADDR = 20
BINDLESS_BASE_5_ADDR = 21
BINDLESS_BASE_6_ADDR = 22
pseudo_reg = ctypes.c_uint32 # enum
# values for enumeration 'source_type'
source_type__enumvalues = {
0: 'SOURCE_REG',
1: 'SOURCE_SCRATCH_MEM',
}
SOURCE_REG = 0
SOURCE_SCRATCH_MEM = 1
source_type = ctypes.c_uint32 # enum
# values for enumeration 'compare_mode'
compare_mode__enumvalues = {
1: 'PRED_TEST',
2: 'REG_COMPARE',
3: 'RENDER_MODE',
4: 'REG_COMPARE_IMM',
5: 'THREAD_MODE',
}
PRED_TEST = 1
REG_COMPARE = 2
RENDER_MODE = 3
REG_COMPARE_IMM = 4
THREAD_MODE = 5
compare_mode = ctypes.c_uint32 # enum
# values for enumeration 'ctxswitch_ib'
ctxswitch_ib__enumvalues = {
0: 'RESTORE_IB',
1: 'YIELD_RESTORE_IB',
2: 'SAVE_IB',
3: 'RB_SAVE_IB',
}
RESTORE_IB = 0
YIELD_RESTORE_IB = 1
SAVE_IB = 2
RB_SAVE_IB = 3
ctxswitch_ib = ctypes.c_uint32 # enum
# values for enumeration 'reg_tracker'
reg_tracker__enumvalues = {
1: 'TRACK_CNTL_REG',
2: 'TRACK_RENDER_CNTL',
4: 'UNK_EVENT_WRITE',
8: 'TRACK_LRZ',
}
TRACK_CNTL_REG = 1
TRACK_RENDER_CNTL = 2
UNK_EVENT_WRITE = 4
TRACK_LRZ = 8
reg_tracker = ctypes.c_uint32 # enum
# values for enumeration 'ts_wait_value_src'
ts_wait_value_src__enumvalues = {
0: 'TS_WAIT_GE_32B',
1: 'TS_WAIT_GE_64B',
2: 'TS_WAIT_GE_TIMESTAMP_SUM',
}
TS_WAIT_GE_32B = 0
TS_WAIT_GE_64B = 1
TS_WAIT_GE_TIMESTAMP_SUM = 2
ts_wait_value_src = ctypes.c_uint32 # enum
# values for enumeration 'ts_wait_type'
ts_wait_type__enumvalues = {
0: 'TS_WAIT_RAM',
1: 'TS_WAIT_ONCHIP',
}
TS_WAIT_RAM = 0
TS_WAIT_ONCHIP = 1
ts_wait_type = ctypes.c_uint32 # enum
# values for enumeration 'pipe_count_op'
pipe_count_op__enumvalues = {
1: 'PIPE_CLEAR_BV_BR',
2: 'PIPE_SET_BR_OFFSET',
3: 'PIPE_BR_WAIT_FOR_BV',
4: 'PIPE_BV_WAIT_FOR_BR',
}
PIPE_CLEAR_BV_BR = 1
PIPE_SET_BR_OFFSET = 2
PIPE_BR_WAIT_FOR_BV = 3
PIPE_BV_WAIT_FOR_BR = 4
pipe_count_op = ctypes.c_uint32 # enum
# values for enumeration 'timestamp_op'
timestamp_op__enumvalues = {
0: 'MODIFY_TIMESTAMP_CLEAR',
1: 'MODIFY_TIMESTAMP_ADD_GLOBAL',
2: 'MODIFY_TIMESTAMP_ADD_LOCAL',
}
MODIFY_TIMESTAMP_CLEAR = 0
MODIFY_TIMESTAMP_ADD_GLOBAL = 1
MODIFY_TIMESTAMP_ADD_LOCAL = 2
timestamp_op = ctypes.c_uint32 # enum
# values for enumeration 'cp_thread'
cp_thread__enumvalues = {
1: 'CP_SET_THREAD_BR',
2: 'CP_SET_THREAD_BV',
3: 'CP_SET_THREAD_BOTH',
}
CP_SET_THREAD_BR = 1
CP_SET_THREAD_BV = 2
CP_SET_THREAD_BOTH = 3
cp_thread = ctypes.c_uint32 # enum
# values for enumeration 'chip'
chip__enumvalues = {
2: 'A2XX',
3: 'A3XX',
4: 'A4XX',
5: 'A5XX',
6: 'A6XX',
7: 'A7XX',
}
A2XX = 2
A3XX = 3
A4XX = 4
A5XX = 5
A6XX = 6
A7XX = 7
chip = ctypes.c_uint32 # enum
# values for enumeration 'adreno_pa_su_sc_draw'
adreno_pa_su_sc_draw__enumvalues = {
0: 'PC_DRAW_POINTS',
1: 'PC_DRAW_LINES',
2: 'PC_DRAW_TRIANGLES',
}
PC_DRAW_POINTS = 0
PC_DRAW_LINES = 1
PC_DRAW_TRIANGLES = 2
adreno_pa_su_sc_draw = ctypes.c_uint32 # enum
# values for enumeration 'adreno_compare_func'
adreno_compare_func__enumvalues = {
0: 'FUNC_NEVER',
1: 'FUNC_LESS',
2: 'FUNC_EQUAL',
3: 'FUNC_LEQUAL',
4: 'FUNC_GREATER',
5: 'FUNC_NOTEQUAL',
6: 'FUNC_GEQUAL',
7: 'FUNC_ALWAYS',
}
FUNC_NEVER = 0
FUNC_LESS = 1
FUNC_EQUAL = 2
FUNC_LEQUAL = 3
FUNC_GREATER = 4
FUNC_NOTEQUAL = 5
FUNC_GEQUAL = 6
FUNC_ALWAYS = 7
adreno_compare_func = ctypes.c_uint32 # enum
# values for enumeration 'adreno_stencil_op'
adreno_stencil_op__enumvalues = {
0: 'STENCIL_KEEP',
1: 'STENCIL_ZERO',
2: 'STENCIL_REPLACE',
3: 'STENCIL_INCR_CLAMP',
4: 'STENCIL_DECR_CLAMP',
5: 'STENCIL_INVERT',
6: 'STENCIL_INCR_WRAP',
7: 'STENCIL_DECR_WRAP',
}
STENCIL_KEEP = 0
STENCIL_ZERO = 1
STENCIL_REPLACE = 2
STENCIL_INCR_CLAMP = 3
STENCIL_DECR_CLAMP = 4
STENCIL_INVERT = 5
STENCIL_INCR_WRAP = 6
STENCIL_DECR_WRAP = 7
adreno_stencil_op = ctypes.c_uint32 # enum
# values for enumeration 'adreno_rb_blend_factor'
adreno_rb_blend_factor__enumvalues = {
0: 'FACTOR_ZERO',
1: 'FACTOR_ONE',
4: 'FACTOR_SRC_COLOR',
5: 'FACTOR_ONE_MINUS_SRC_COLOR',
6: 'FACTOR_SRC_ALPHA',
7: 'FACTOR_ONE_MINUS_SRC_ALPHA',
8: 'FACTOR_DST_COLOR',
9: 'FACTOR_ONE_MINUS_DST_COLOR',
10: 'FACTOR_DST_ALPHA',
11: 'FACTOR_ONE_MINUS_DST_ALPHA',
12: 'FACTOR_CONSTANT_COLOR',
13: 'FACTOR_ONE_MINUS_CONSTANT_COLOR',
14: 'FACTOR_CONSTANT_ALPHA',
15: 'FACTOR_ONE_MINUS_CONSTANT_ALPHA',
16: 'FACTOR_SRC_ALPHA_SATURATE',
20: 'FACTOR_SRC1_COLOR',
21: 'FACTOR_ONE_MINUS_SRC1_COLOR',
22: 'FACTOR_SRC1_ALPHA',
23: 'FACTOR_ONE_MINUS_SRC1_ALPHA',
}
FACTOR_ZERO = 0
FACTOR_ONE = 1
FACTOR_SRC_COLOR = 4
FACTOR_ONE_MINUS_SRC_COLOR = 5
FACTOR_SRC_ALPHA = 6
FACTOR_ONE_MINUS_SRC_ALPHA = 7
FACTOR_DST_COLOR = 8
FACTOR_ONE_MINUS_DST_COLOR = 9
FACTOR_DST_ALPHA = 10
FACTOR_ONE_MINUS_DST_ALPHA = 11
FACTOR_CONSTANT_COLOR = 12
FACTOR_ONE_MINUS_CONSTANT_COLOR = 13
FACTOR_CONSTANT_ALPHA = 14
FACTOR_ONE_MINUS_CONSTANT_ALPHA = 15
FACTOR_SRC_ALPHA_SATURATE = 16
FACTOR_SRC1_COLOR = 20
FACTOR_ONE_MINUS_SRC1_COLOR = 21
FACTOR_SRC1_ALPHA = 22
FACTOR_ONE_MINUS_SRC1_ALPHA = 23
adreno_rb_blend_factor = ctypes.c_uint32 # enum
# values for enumeration 'adreno_rb_surface_endian'
adreno_rb_surface_endian__enumvalues = {
0: 'ENDIAN_NONE',
1: 'ENDIAN_8IN16',
2: 'ENDIAN_8IN32',
3: 'ENDIAN_16IN32',
4: 'ENDIAN_8IN64',
5: 'ENDIAN_8IN128',
}
ENDIAN_NONE = 0
ENDIAN_8IN16 = 1
ENDIAN_8IN32 = 2
ENDIAN_16IN32 = 3
ENDIAN_8IN64 = 4
ENDIAN_8IN128 = 5
adreno_rb_surface_endian = ctypes.c_uint32 # enum
# values for enumeration 'adreno_rb_dither_mode'
adreno_rb_dither_mode__enumvalues = {
0: 'DITHER_DISABLE',
1: 'DITHER_ALWAYS',
2: 'DITHER_IF_ALPHA_OFF',
}
DITHER_DISABLE = 0
DITHER_ALWAYS = 1
DITHER_IF_ALPHA_OFF = 2
adreno_rb_dither_mode = ctypes.c_uint32 # enum
# values for enumeration 'adreno_rb_depth_format'
adreno_rb_depth_format__enumvalues = {
0: 'DEPTHX_16',
1: 'DEPTHX_24_8',
2: 'DEPTHX_32',
}
DEPTHX_16 = 0
DEPTHX_24_8 = 1
DEPTHX_32 = 2
adreno_rb_depth_format = ctypes.c_uint32 # enum
# values for enumeration 'adreno_rb_copy_control_mode'
adreno_rb_copy_control_mode__enumvalues = {
1: 'RB_COPY_RESOLVE',
2: 'RB_COPY_CLEAR',
5: 'RB_COPY_DEPTH_STENCIL',
}
RB_COPY_RESOLVE = 1
RB_COPY_CLEAR = 2
RB_COPY_DEPTH_STENCIL = 5
adreno_rb_copy_control_mode = ctypes.c_uint32 # enum
# values for enumeration 'a3xx_rop_code'
a3xx_rop_code__enumvalues = {
0: 'ROP_CLEAR',
1: 'ROP_NOR',
2: 'ROP_AND_INVERTED',
3: 'ROP_COPY_INVERTED',
4: 'ROP_AND_REVERSE',
5: 'ROP_INVERT',
6: 'ROP_XOR',
7: 'ROP_NAND',
8: 'ROP_AND',
9: 'ROP_EQUIV',
10: 'ROP_NOOP',
11: 'ROP_OR_INVERTED',
12: 'ROP_COPY',
13: 'ROP_OR_REVERSE',
14: 'ROP_OR',
15: 'ROP_SET',
}
ROP_CLEAR = 0
ROP_NOR = 1
ROP_AND_INVERTED = 2
ROP_COPY_INVERTED = 3
ROP_AND_REVERSE = 4
ROP_INVERT = 5
ROP_XOR = 6
ROP_NAND = 7
ROP_AND = 8
ROP_EQUIV = 9
ROP_NOOP = 10
ROP_OR_INVERTED = 11
ROP_COPY = 12
ROP_OR_REVERSE = 13
ROP_OR = 14
ROP_SET = 15
a3xx_rop_code = ctypes.c_uint32 # enum
# values for enumeration 'a3xx_render_mode'
a3xx_render_mode__enumvalues = {
0: 'RB_RENDERING_PASS',
1: 'RB_TILING_PASS',
2: 'RB_RESOLVE_PASS',
3: 'RB_COMPUTE_PASS',
}
RB_RENDERING_PASS = 0
RB_TILING_PASS = 1
RB_RESOLVE_PASS = 2
RB_COMPUTE_PASS = 3
a3xx_render_mode = ctypes.c_uint32 # enum
# values for enumeration 'a3xx_msaa_samples'
a3xx_msaa_samples__enumvalues = {
0: 'MSAA_ONE',
1: 'MSAA_TWO',
2: 'MSAA_FOUR',
3: 'MSAA_EIGHT',
}
MSAA_ONE = 0
MSAA_TWO = 1
MSAA_FOUR = 2
MSAA_EIGHT = 3
a3xx_msaa_samples = ctypes.c_uint32 # enum
# values for enumeration 'a3xx_threadmode'
a3xx_threadmode__enumvalues = {
0: 'MULTI',
1: 'SINGLE',
}
MULTI = 0
SINGLE = 1
a3xx_threadmode = ctypes.c_uint32 # enum
# values for enumeration 'a3xx_instrbuffermode'
a3xx_instrbuffermode__enumvalues = {
0: 'CACHE',
1: 'BUFFER',
}
CACHE = 0
BUFFER = 1
a3xx_instrbuffermode = ctypes.c_uint32 # enum
# values for enumeration 'a3xx_threadsize'
a3xx_threadsize__enumvalues = {
0: 'TWO_QUADS',
1: 'FOUR_QUADS',
}
TWO_QUADS = 0
FOUR_QUADS = 1
a3xx_threadsize = ctypes.c_uint32 # enum
# values for enumeration 'a3xx_color_swap'
a3xx_color_swap__enumvalues = {
0: 'WZYX',
1: 'WXYZ',
2: 'ZYXW',
3: 'XYZW',
}
WZYX = 0
WXYZ = 1
ZYXW = 2
XYZW = 3
a3xx_color_swap = ctypes.c_uint32 # enum
# values for enumeration 'a3xx_rb_blend_opcode'
a3xx_rb_blend_opcode__enumvalues = {
0: 'BLEND_DST_PLUS_SRC',
1: 'BLEND_SRC_MINUS_DST',
2: 'BLEND_DST_MINUS_SRC',
3: 'BLEND_MIN_DST_SRC',
4: 'BLEND_MAX_DST_SRC',
}
BLEND_DST_PLUS_SRC = 0
BLEND_SRC_MINUS_DST = 1
BLEND_DST_MINUS_SRC = 2
BLEND_MIN_DST_SRC = 3
BLEND_MAX_DST_SRC = 4
a3xx_rb_blend_opcode = ctypes.c_uint32 # enum
# values for enumeration 'a4xx_tess_spacing'
a4xx_tess_spacing__enumvalues = {
0: 'EQUAL_SPACING',
2: 'ODD_SPACING',
3: 'EVEN_SPACING',
}
EQUAL_SPACING = 0
ODD_SPACING = 2
EVEN_SPACING = 3
a4xx_tess_spacing = ctypes.c_uint32 # enum
# values for enumeration 'a5xx_address_mode'
a5xx_address_mode__enumvalues = {
0: 'ADDR_32B',
1: 'ADDR_64B',
}
ADDR_32B = 0
ADDR_64B = 1
a5xx_address_mode = ctypes.c_uint32 # enum
# values for enumeration 'a5xx_line_mode'
a5xx_line_mode__enumvalues = {
0: 'BRESENHAM',
1: 'RECTANGULAR',
}
BRESENHAM = 0
RECTANGULAR = 1
a5xx_line_mode = ctypes.c_uint32 # enum
# values for enumeration 'a6xx_tex_prefetch_cmd'
a6xx_tex_prefetch_cmd__enumvalues = {
0: 'TEX_PREFETCH_UNK0',
1: 'TEX_PREFETCH_SAM',
2: 'TEX_PREFETCH_GATHER4R',
3: 'TEX_PREFETCH_GATHER4G',
4: 'TEX_PREFETCH_GATHER4B',
5: 'TEX_PREFETCH_GATHER4A',
6: 'TEX_PREFETCH_UNK6',
7: 'TEX_PREFETCH_UNK7',
}
TEX_PREFETCH_UNK0 = 0
TEX_PREFETCH_SAM = 1
TEX_PREFETCH_GATHER4R = 2
TEX_PREFETCH_GATHER4G = 3
TEX_PREFETCH_GATHER4B = 4
TEX_PREFETCH_GATHER4A = 5
TEX_PREFETCH_UNK6 = 6
TEX_PREFETCH_UNK7 = 7
a6xx_tex_prefetch_cmd = ctypes.c_uint32 # enum
# values for enumeration 'a6xx_tile_mode'
a6xx_tile_mode__enumvalues = {
0: 'TILE6_LINEAR',
2: 'TILE6_2',
3: 'TILE6_3',
}
TILE6_LINEAR = 0
TILE6_2 = 2
TILE6_3 = 3
a6xx_tile_mode = ctypes.c_uint32 # enum
# values for enumeration 'a6xx_format'
a6xx_format__enumvalues = {
2: 'FMT6_A8_UNORM',
3: 'FMT6_8_UNORM',
4: 'FMT6_8_SNORM',
5: 'FMT6_8_UINT',
6: 'FMT6_8_SINT',
8: 'FMT6_4_4_4_4_UNORM',
10: 'FMT6_5_5_5_1_UNORM',
12: 'FMT6_1_5_5_5_UNORM',
14: 'FMT6_5_6_5_UNORM',
15: 'FMT6_8_8_UNORM',
16: 'FMT6_8_8_SNORM',
17: 'FMT6_8_8_UINT',
18: 'FMT6_8_8_SINT',
19: 'FMT6_L8_A8_UNORM',
21: 'FMT6_16_UNORM',
22: 'FMT6_16_SNORM',
23: 'FMT6_16_FLOAT',
24: 'FMT6_16_UINT',
25: 'FMT6_16_SINT',
33: 'FMT6_8_8_8_UNORM',
34: 'FMT6_8_8_8_SNORM',
35: 'FMT6_8_8_8_UINT',
36: 'FMT6_8_8_8_SINT',
48: 'FMT6_8_8_8_8_UNORM',
49: 'FMT6_8_8_8_X8_UNORM',
50: 'FMT6_8_8_8_8_SNORM',
51: 'FMT6_8_8_8_8_UINT',
52: 'FMT6_8_8_8_8_SINT',
53: 'FMT6_9_9_9_E5_FLOAT',
54: 'FMT6_10_10_10_2_UNORM',
55: 'FMT6_10_10_10_2_UNORM_DEST',
57: 'FMT6_10_10_10_2_SNORM',
58: 'FMT6_10_10_10_2_UINT',
59: 'FMT6_10_10_10_2_SINT',
66: 'FMT6_11_11_10_FLOAT',
67: 'FMT6_16_16_UNORM',
68: 'FMT6_16_16_SNORM',
69: 'FMT6_16_16_FLOAT',
70: 'FMT6_16_16_UINT',
71: 'FMT6_16_16_SINT',
72: 'FMT6_32_UNORM',
73: 'FMT6_32_SNORM',
74: 'FMT6_32_FLOAT',
75: 'FMT6_32_UINT',
76: 'FMT6_32_SINT',
77: 'FMT6_32_FIXED',
88: 'FMT6_16_16_16_UNORM',
89: 'FMT6_16_16_16_SNORM',
90: 'FMT6_16_16_16_FLOAT',
91: 'FMT6_16_16_16_UINT',
92: 'FMT6_16_16_16_SINT',
96: 'FMT6_16_16_16_16_UNORM',
97: 'FMT6_16_16_16_16_SNORM',
98: 'FMT6_16_16_16_16_FLOAT',
99: 'FMT6_16_16_16_16_UINT',
100: 'FMT6_16_16_16_16_SINT',
101: 'FMT6_32_32_UNORM',
102: 'FMT6_32_32_SNORM',
103: 'FMT6_32_32_FLOAT',
104: 'FMT6_32_32_UINT',
105: 'FMT6_32_32_SINT',
106: 'FMT6_32_32_FIXED',
112: 'FMT6_32_32_32_UNORM',
113: 'FMT6_32_32_32_SNORM',
114: 'FMT6_32_32_32_UINT',
115: 'FMT6_32_32_32_SINT',
116: 'FMT6_32_32_32_FLOAT',
117: 'FMT6_32_32_32_FIXED',
128: 'FMT6_32_32_32_32_UNORM',
129: 'FMT6_32_32_32_32_SNORM',
130: 'FMT6_32_32_32_32_FLOAT',
131: 'FMT6_32_32_32_32_UINT',
132: 'FMT6_32_32_32_32_SINT',
133: 'FMT6_32_32_32_32_FIXED',
140: 'FMT6_G8R8B8R8_422_UNORM',
141: 'FMT6_R8G8R8B8_422_UNORM',
142: 'FMT6_R8_G8B8_2PLANE_420_UNORM',
143: 'FMT6_NV21',
144: 'FMT6_R8_G8_B8_3PLANE_420_UNORM',
145: 'FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8',
148: 'FMT6_NV12_Y',
149: 'FMT6_NV12_UV',
150: 'FMT6_NV12_VU',
151: 'FMT6_NV12_4R',
152: 'FMT6_NV12_4R_Y',
153: 'FMT6_NV12_4R_UV',
154: 'FMT6_P010',
155: 'FMT6_P010_Y',
156: 'FMT6_P010_UV',
157: 'FMT6_TP10',
158: 'FMT6_TP10_Y',
159: 'FMT6_TP10_UV',
160: 'FMT6_Z24_UNORM_S8_UINT',
171: 'FMT6_ETC2_RG11_UNORM',
172: 'FMT6_ETC2_RG11_SNORM',
173: 'FMT6_ETC2_R11_UNORM',
174: 'FMT6_ETC2_R11_SNORM',
175: 'FMT6_ETC1',
176: 'FMT6_ETC2_RGB8',
177: 'FMT6_ETC2_RGBA8',
178: 'FMT6_ETC2_RGB8A1',
179: 'FMT6_DXT1',
180: 'FMT6_DXT3',
181: 'FMT6_DXT5',
183: 'FMT6_RGTC1_UNORM',
184: 'FMT6_RGTC1_SNORM',
187: 'FMT6_RGTC2_UNORM',
188: 'FMT6_RGTC2_SNORM',
190: 'FMT6_BPTC_UFLOAT',
191: 'FMT6_BPTC_FLOAT',
192: 'FMT6_BPTC',
193: 'FMT6_ASTC_4x4',
194: 'FMT6_ASTC_5x4',
195: 'FMT6_ASTC_5x5',
196: 'FMT6_ASTC_6x5',
197: 'FMT6_ASTC_6x6',
198: 'FMT6_ASTC_8x5',
199: 'FMT6_ASTC_8x6',
200: 'FMT6_ASTC_8x8',
201: 'FMT6_ASTC_10x5',
202: 'FMT6_ASTC_10x6',
203: 'FMT6_ASTC_10x8',
204: 'FMT6_ASTC_10x10',
205: 'FMT6_ASTC_12x10',
206: 'FMT6_ASTC_12x12',
234: 'FMT6_Z24_UINT_S8_UINT',
255: 'FMT6_NONE',
}
FMT6_A8_UNORM = 2
FMT6_8_UNORM = 3
FMT6_8_SNORM = 4
FMT6_8_UINT = 5
FMT6_8_SINT = 6
FMT6_4_4_4_4_UNORM = 8
FMT6_5_5_5_1_UNORM = 10
FMT6_1_5_5_5_UNORM = 12
FMT6_5_6_5_UNORM = 14
FMT6_8_8_UNORM = 15
FMT6_8_8_SNORM = 16
FMT6_8_8_UINT = 17
FMT6_8_8_SINT = 18
FMT6_L8_A8_UNORM = 19
FMT6_16_UNORM = 21
FMT6_16_SNORM = 22
FMT6_16_FLOAT = 23
FMT6_16_UINT = 24
FMT6_16_SINT = 25
FMT6_8_8_8_UNORM = 33
FMT6_8_8_8_SNORM = 34
FMT6_8_8_8_UINT = 35
FMT6_8_8_8_SINT = 36
FMT6_8_8_8_8_UNORM = 48
FMT6_8_8_8_X8_UNORM = 49
FMT6_8_8_8_8_SNORM = 50
FMT6_8_8_8_8_UINT = 51
FMT6_8_8_8_8_SINT = 52
FMT6_9_9_9_E5_FLOAT = 53
FMT6_10_10_10_2_UNORM = 54
FMT6_10_10_10_2_UNORM_DEST = 55
FMT6_10_10_10_2_SNORM = 57
FMT6_10_10_10_2_UINT = 58
FMT6_10_10_10_2_SINT = 59
FMT6_11_11_10_FLOAT = 66
FMT6_16_16_UNORM = 67
FMT6_16_16_SNORM = 68
FMT6_16_16_FLOAT = 69
FMT6_16_16_UINT = 70
FMT6_16_16_SINT = 71
FMT6_32_UNORM = 72
FMT6_32_SNORM = 73
FMT6_32_FLOAT = 74
FMT6_32_UINT = 75
FMT6_32_SINT = 76
FMT6_32_FIXED = 77
FMT6_16_16_16_UNORM = 88
FMT6_16_16_16_SNORM = 89
FMT6_16_16_16_FLOAT = 90
FMT6_16_16_16_UINT = 91
FMT6_16_16_16_SINT = 92
FMT6_16_16_16_16_UNORM = 96
FMT6_16_16_16_16_SNORM = 97
FMT6_16_16_16_16_FLOAT = 98
FMT6_16_16_16_16_UINT = 99
FMT6_16_16_16_16_SINT = 100
FMT6_32_32_UNORM = 101
FMT6_32_32_SNORM = 102
FMT6_32_32_FLOAT = 103
FMT6_32_32_UINT = 104
FMT6_32_32_SINT = 105
FMT6_32_32_FIXED = 106
FMT6_32_32_32_UNORM = 112
FMT6_32_32_32_SNORM = 113
FMT6_32_32_32_UINT = 114
FMT6_32_32_32_SINT = 115
FMT6_32_32_32_FLOAT = 116
FMT6_32_32_32_FIXED = 117
FMT6_32_32_32_32_UNORM = 128
FMT6_32_32_32_32_SNORM = 129
FMT6_32_32_32_32_FLOAT = 130
FMT6_32_32_32_32_UINT = 131
FMT6_32_32_32_32_SINT = 132
FMT6_32_32_32_32_FIXED = 133
FMT6_G8R8B8R8_422_UNORM = 140
FMT6_R8G8R8B8_422_UNORM = 141
FMT6_R8_G8B8_2PLANE_420_UNORM = 142
FMT6_NV21 = 143
FMT6_R8_G8_B8_3PLANE_420_UNORM = 144
FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8 = 145
FMT6_NV12_Y = 148
FMT6_NV12_UV = 149
FMT6_NV12_VU = 150
FMT6_NV12_4R = 151
FMT6_NV12_4R_Y = 152
FMT6_NV12_4R_UV = 153
FMT6_P010 = 154
FMT6_P010_Y = 155
FMT6_P010_UV = 156
FMT6_TP10 = 157
FMT6_TP10_Y = 158
FMT6_TP10_UV = 159
FMT6_Z24_UNORM_S8_UINT = 160
FMT6_ETC2_RG11_UNORM = 171
FMT6_ETC2_RG11_SNORM = 172
FMT6_ETC2_R11_UNORM = 173
FMT6_ETC2_R11_SNORM = 174
FMT6_ETC1 = 175
FMT6_ETC2_RGB8 = 176
FMT6_ETC2_RGBA8 = 177
FMT6_ETC2_RGB8A1 = 178
FMT6_DXT1 = 179
FMT6_DXT3 = 180
FMT6_DXT5 = 181
FMT6_RGTC1_UNORM = 183
FMT6_RGTC1_SNORM = 184
FMT6_RGTC2_UNORM = 187
FMT6_RGTC2_SNORM = 188
FMT6_BPTC_UFLOAT = 190
FMT6_BPTC_FLOAT = 191
FMT6_BPTC = 192
FMT6_ASTC_4x4 = 193
FMT6_ASTC_5x4 = 194
FMT6_ASTC_5x5 = 195
FMT6_ASTC_6x5 = 196
FMT6_ASTC_6x6 = 197
FMT6_ASTC_8x5 = 198
FMT6_ASTC_8x6 = 199
FMT6_ASTC_8x8 = 200
FMT6_ASTC_10x5 = 201
FMT6_ASTC_10x6 = 202
FMT6_ASTC_10x8 = 203
FMT6_ASTC_10x10 = 204
FMT6_ASTC_12x10 = 205
FMT6_ASTC_12x12 = 206
FMT6_Z24_UINT_S8_UINT = 234
FMT6_NONE = 255
a6xx_format = ctypes.c_uint32 # enum
# values for enumeration 'a6xx_polygon_mode'
a6xx_polygon_mode__enumvalues = {
1: 'POLYMODE6_POINTS',
2: 'POLYMODE6_LINES',
3: 'POLYMODE6_TRIANGLES',
}
POLYMODE6_POINTS = 1
POLYMODE6_LINES = 2
POLYMODE6_TRIANGLES = 3
a6xx_polygon_mode = ctypes.c_uint32 # enum
# values for enumeration 'a6xx_depth_format'
a6xx_depth_format__enumvalues = {
0: 'DEPTH6_NONE',
1: 'DEPTH6_16',
2: 'DEPTH6_24_8',
4: 'DEPTH6_32',
}
DEPTH6_NONE = 0
DEPTH6_16 = 1
DEPTH6_24_8 = 2
DEPTH6_32 = 4
a6xx_depth_format = ctypes.c_uint32 # enum
# values for enumeration 'a6xx_shader_id'
a6xx_shader_id__enumvalues = {
9: 'A6XX_TP0_TMO_DATA',
10: 'A6XX_TP0_SMO_DATA',
11: 'A6XX_TP0_MIPMAP_BASE_DATA',
25: 'A6XX_TP1_TMO_DATA',
26: 'A6XX_TP1_SMO_DATA',
27: 'A6XX_TP1_MIPMAP_BASE_DATA',
41: 'A6XX_SP_INST_DATA',
42: 'A6XX_SP_LB_0_DATA',
43: 'A6XX_SP_LB_1_DATA',
44: 'A6XX_SP_LB_2_DATA',
45: 'A6XX_SP_LB_3_DATA',
46: 'A6XX_SP_LB_4_DATA',
47: 'A6XX_SP_LB_5_DATA',
48: 'A6XX_SP_CB_BINDLESS_DATA',
49: 'A6XX_SP_CB_LEGACY_DATA',
50: 'A6XX_SP_UAV_DATA',
51: 'A6XX_SP_INST_TAG',
52: 'A6XX_SP_CB_BINDLESS_TAG',
53: 'A6XX_SP_TMO_UMO_TAG',
54: 'A6XX_SP_SMO_TAG',
55: 'A6XX_SP_STATE_DATA',
73: 'A6XX_HLSQ_CHUNK_CVS_RAM',
74: 'A6XX_HLSQ_CHUNK_CPS_RAM',
75: 'A6XX_HLSQ_CHUNK_CVS_RAM_TAG',
76: 'A6XX_HLSQ_CHUNK_CPS_RAM_TAG',
77: 'A6XX_HLSQ_ICB_CVS_CB_BASE_TAG',
78: 'A6XX_HLSQ_ICB_CPS_CB_BASE_TAG',
80: 'A6XX_HLSQ_CVS_MISC_RAM',
81: 'A6XX_HLSQ_CPS_MISC_RAM',
82: 'A6XX_HLSQ_INST_RAM',
83: 'A6XX_HLSQ_GFX_CVS_CONST_RAM',
84: 'A6XX_HLSQ_GFX_CPS_CONST_RAM',
85: 'A6XX_HLSQ_CVS_MISC_RAM_TAG',
86: 'A6XX_HLSQ_CPS_MISC_RAM_TAG',
87: 'A6XX_HLSQ_INST_RAM_TAG',
88: 'A6XX_HLSQ_GFX_CVS_CONST_RAM_TAG',
89: 'A6XX_HLSQ_GFX_CPS_CONST_RAM_TAG',
90: 'A6XX_HLSQ_PWR_REST_RAM',
91: 'A6XX_HLSQ_PWR_REST_TAG',
96: 'A6XX_HLSQ_DATAPATH_META',
97: 'A6XX_HLSQ_FRONTEND_META',
98: 'A6XX_HLSQ_INDIRECT_META',
99: 'A6XX_HLSQ_BACKEND_META',
112: 'A6XX_SP_LB_6_DATA',
113: 'A6XX_SP_LB_7_DATA',
115: 'A6XX_HLSQ_INST_RAM_1',
}
A6XX_TP0_TMO_DATA = 9
A6XX_TP0_SMO_DATA = 10
A6XX_TP0_MIPMAP_BASE_DATA = 11
A6XX_TP1_TMO_DATA = 25
A6XX_TP1_SMO_DATA = 26
A6XX_TP1_MIPMAP_BASE_DATA = 27
A6XX_SP_INST_DATA = 41
A6XX_SP_LB_0_DATA = 42
A6XX_SP_LB_1_DATA = 43
A6XX_SP_LB_2_DATA = 44
A6XX_SP_LB_3_DATA = 45
A6XX_SP_LB_4_DATA = 46
A6XX_SP_LB_5_DATA = 47
A6XX_SP_CB_BINDLESS_DATA = 48
A6XX_SP_CB_LEGACY_DATA = 49
A6XX_SP_UAV_DATA = 50
A6XX_SP_INST_TAG = 51
A6XX_SP_CB_BINDLESS_TAG = 52
A6XX_SP_TMO_UMO_TAG = 53
A6XX_SP_SMO_TAG = 54
A6XX_SP_STATE_DATA = 55
A6XX_HLSQ_CHUNK_CVS_RAM = 73
A6XX_HLSQ_CHUNK_CPS_RAM = 74
A6XX_HLSQ_CHUNK_CVS_RAM_TAG = 75
A6XX_HLSQ_CHUNK_CPS_RAM_TAG = 76
A6XX_HLSQ_ICB_CVS_CB_BASE_TAG = 77
A6XX_HLSQ_ICB_CPS_CB_BASE_TAG = 78
A6XX_HLSQ_CVS_MISC_RAM = 80
A6XX_HLSQ_CPS_MISC_RAM = 81
A6XX_HLSQ_INST_RAM = 82
A6XX_HLSQ_GFX_CVS_CONST_RAM = 83
A6XX_HLSQ_GFX_CPS_CONST_RAM = 84
A6XX_HLSQ_CVS_MISC_RAM_TAG = 85
A6XX_HLSQ_CPS_MISC_RAM_TAG = 86
A6XX_HLSQ_INST_RAM_TAG = 87
A6XX_HLSQ_GFX_CVS_CONST_RAM_TAG = 88
A6XX_HLSQ_GFX_CPS_CONST_RAM_TAG = 89
A6XX_HLSQ_PWR_REST_RAM = 90
A6XX_HLSQ_PWR_REST_TAG = 91
A6XX_HLSQ_DATAPATH_META = 96
A6XX_HLSQ_FRONTEND_META = 97
A6XX_HLSQ_INDIRECT_META = 98
A6XX_HLSQ_BACKEND_META = 99
A6XX_SP_LB_6_DATA = 112
A6XX_SP_LB_7_DATA = 113
A6XX_HLSQ_INST_RAM_1 = 115
a6xx_shader_id = ctypes.c_uint32 # enum
# values for enumeration 'a7xx_statetype_id'
a7xx_statetype_id__enumvalues = {
0: 'A7XX_TP0_NCTX_REG',
1: 'A7XX_TP0_CTX0_3D_CVS_REG',
2: 'A7XX_TP0_CTX0_3D_CPS_REG',
3: 'A7XX_TP0_CTX1_3D_CVS_REG',
4: 'A7XX_TP0_CTX1_3D_CPS_REG',
5: 'A7XX_TP0_CTX2_3D_CPS_REG',
6: 'A7XX_TP0_CTX3_3D_CPS_REG',
9: 'A7XX_TP0_TMO_DATA',
10: 'A7XX_TP0_SMO_DATA',
11: 'A7XX_TP0_MIPMAP_BASE_DATA',
32: 'A7XX_SP_NCTX_REG',
33: 'A7XX_SP_CTX0_3D_CVS_REG',
34: 'A7XX_SP_CTX0_3D_CPS_REG',
35: 'A7XX_SP_CTX1_3D_CVS_REG',
36: 'A7XX_SP_CTX1_3D_CPS_REG',
37: 'A7XX_SP_CTX2_3D_CPS_REG',
38: 'A7XX_SP_CTX3_3D_CPS_REG',
39: 'A7XX_SP_INST_DATA',
40: 'A7XX_SP_INST_DATA_1',
41: 'A7XX_SP_LB_0_DATA',
42: 'A7XX_SP_LB_1_DATA',
43: 'A7XX_SP_LB_2_DATA',
44: 'A7XX_SP_LB_3_DATA',
45: 'A7XX_SP_LB_4_DATA',
46: 'A7XX_SP_LB_5_DATA',
47: 'A7XX_SP_LB_6_DATA',
48: 'A7XX_SP_LB_7_DATA',
49: 'A7XX_SP_CB_RAM',
50: 'A7XX_SP_LB_13_DATA',
51: 'A7XX_SP_LB_14_DATA',
52: 'A7XX_SP_INST_TAG',
53: 'A7XX_SP_INST_DATA_2',
54: 'A7XX_SP_TMO_TAG',
55: 'A7XX_SP_SMO_TAG',
56: 'A7XX_SP_STATE_DATA',
57: 'A7XX_SP_HWAVE_RAM',
58: 'A7XX_SP_L0_INST_BUF',
59: 'A7XX_SP_LB_8_DATA',
60: 'A7XX_SP_LB_9_DATA',
61: 'A7XX_SP_LB_10_DATA',
62: 'A7XX_SP_LB_11_DATA',
63: 'A7XX_SP_LB_12_DATA',
64: 'A7XX_HLSQ_DATAPATH_DSTR_META',
67: 'A7XX_HLSQ_L2STC_TAG_RAM',
68: 'A7XX_HLSQ_L2STC_INFO_CMD',
69: 'A7XX_HLSQ_CVS_BE_CTXT_BUF_RAM_TAG',
70: 'A7XX_HLSQ_CPS_BE_CTXT_BUF_RAM_TAG',
71: 'A7XX_HLSQ_GFX_CVS_BE_CTXT_BUF_RAM',
72: 'A7XX_HLSQ_GFX_CPS_BE_CTXT_BUF_RAM',
73: 'A7XX_HLSQ_CHUNK_CVS_RAM',
74: 'A7XX_HLSQ_CHUNK_CPS_RAM',
75: 'A7XX_HLSQ_CHUNK_CVS_RAM_TAG',
76: 'A7XX_HLSQ_CHUNK_CPS_RAM_TAG',
77: 'A7XX_HLSQ_ICB_CVS_CB_BASE_TAG',
78: 'A7XX_HLSQ_ICB_CPS_CB_BASE_TAG',
79: 'A7XX_HLSQ_CVS_MISC_RAM',
80: 'A7XX_HLSQ_CPS_MISC_RAM',
81: 'A7XX_HLSQ_CPS_MISC_RAM_1',
82: 'A7XX_HLSQ_INST_RAM',
83: 'A7XX_HLSQ_GFX_CVS_CONST_RAM',
84: 'A7XX_HLSQ_GFX_CPS_CONST_RAM',
85: 'A7XX_HLSQ_CVS_MISC_RAM_TAG',
86: 'A7XX_HLSQ_CPS_MISC_RAM_TAG',
87: 'A7XX_HLSQ_INST_RAM_TAG',
88: 'A7XX_HLSQ_GFX_CVS_CONST_RAM_TAG',
89: 'A7XX_HLSQ_GFX_CPS_CONST_RAM_TAG',
90: 'A7XX_HLSQ_GFX_LOCAL_MISC_RAM',
91: 'A7XX_HLSQ_GFX_LOCAL_MISC_RAM_TAG',
92: 'A7XX_HLSQ_INST_RAM_1',
93: 'A7XX_HLSQ_STPROC_META',
94: 'A7XX_HLSQ_BV_BE_META',
95: 'A7XX_HLSQ_INST_RAM_2',
96: 'A7XX_HLSQ_DATAPATH_META',
97: 'A7XX_HLSQ_FRONTEND_META',
98: 'A7XX_HLSQ_INDIRECT_META',
99: 'A7XX_HLSQ_BACKEND_META',
}
A7XX_TP0_NCTX_REG = 0
A7XX_TP0_CTX0_3D_CVS_REG = 1
A7XX_TP0_CTX0_3D_CPS_REG = 2
A7XX_TP0_CTX1_3D_CVS_REG = 3
A7XX_TP0_CTX1_3D_CPS_REG = 4
A7XX_TP0_CTX2_3D_CPS_REG = 5
A7XX_TP0_CTX3_3D_CPS_REG = 6
A7XX_TP0_TMO_DATA = 9
A7XX_TP0_SMO_DATA = 10
A7XX_TP0_MIPMAP_BASE_DATA = 11
A7XX_SP_NCTX_REG = 32
A7XX_SP_CTX0_3D_CVS_REG = 33
A7XX_SP_CTX0_3D_CPS_REG = 34
A7XX_SP_CTX1_3D_CVS_REG = 35
A7XX_SP_CTX1_3D_CPS_REG = 36
A7XX_SP_CTX2_3D_CPS_REG = 37
A7XX_SP_CTX3_3D_CPS_REG = 38
A7XX_SP_INST_DATA = 39
A7XX_SP_INST_DATA_1 = 40
A7XX_SP_LB_0_DATA = 41
A7XX_SP_LB_1_DATA = 42
A7XX_SP_LB_2_DATA = 43
A7XX_SP_LB_3_DATA = 44
A7XX_SP_LB_4_DATA = 45
A7XX_SP_LB_5_DATA = 46
A7XX_SP_LB_6_DATA = 47
A7XX_SP_LB_7_DATA = 48
A7XX_SP_CB_RAM = 49
A7XX_SP_LB_13_DATA = 50
A7XX_SP_LB_14_DATA = 51
A7XX_SP_INST_TAG = 52
A7XX_SP_INST_DATA_2 = 53
A7XX_SP_TMO_TAG = 54
A7XX_SP_SMO_TAG = 55
A7XX_SP_STATE_DATA = 56
A7XX_SP_HWAVE_RAM = 57
A7XX_SP_L0_INST_BUF = 58
A7XX_SP_LB_8_DATA = 59
A7XX_SP_LB_9_DATA = 60
A7XX_SP_LB_10_DATA = 61
A7XX_SP_LB_11_DATA = 62
A7XX_SP_LB_12_DATA = 63
A7XX_HLSQ_DATAPATH_DSTR_META = 64
A7XX_HLSQ_L2STC_TAG_RAM = 67
A7XX_HLSQ_L2STC_INFO_CMD = 68
A7XX_HLSQ_CVS_BE_CTXT_BUF_RAM_TAG = 69
A7XX_HLSQ_CPS_BE_CTXT_BUF_RAM_TAG = 70
A7XX_HLSQ_GFX_CVS_BE_CTXT_BUF_RAM = 71
A7XX_HLSQ_GFX_CPS_BE_CTXT_BUF_RAM = 72
A7XX_HLSQ_CHUNK_CVS_RAM = 73
A7XX_HLSQ_CHUNK_CPS_RAM = 74
A7XX_HLSQ_CHUNK_CVS_RAM_TAG = 75
A7XX_HLSQ_CHUNK_CPS_RAM_TAG = 76
A7XX_HLSQ_ICB_CVS_CB_BASE_TAG = 77
A7XX_HLSQ_ICB_CPS_CB_BASE_TAG = 78
A7XX_HLSQ_CVS_MISC_RAM = 79
A7XX_HLSQ_CPS_MISC_RAM = 80
A7XX_HLSQ_CPS_MISC_RAM_1 = 81
A7XX_HLSQ_INST_RAM = 82
A7XX_HLSQ_GFX_CVS_CONST_RAM = 83
A7XX_HLSQ_GFX_CPS_CONST_RAM = 84
A7XX_HLSQ_CVS_MISC_RAM_TAG = 85
A7XX_HLSQ_CPS_MISC_RAM_TAG = 86
A7XX_HLSQ_INST_RAM_TAG = 87
A7XX_HLSQ_GFX_CVS_CONST_RAM_TAG = 88
A7XX_HLSQ_GFX_CPS_CONST_RAM_TAG = 89
A7XX_HLSQ_GFX_LOCAL_MISC_RAM = 90
A7XX_HLSQ_GFX_LOCAL_MISC_RAM_TAG = 91
A7XX_HLSQ_INST_RAM_1 = 92
A7XX_HLSQ_STPROC_META = 93
A7XX_HLSQ_BV_BE_META = 94
A7XX_HLSQ_INST_RAM_2 = 95
A7XX_HLSQ_DATAPATH_META = 96
A7XX_HLSQ_FRONTEND_META = 97
A7XX_HLSQ_INDIRECT_META = 98
A7XX_HLSQ_BACKEND_META = 99
a7xx_statetype_id = ctypes.c_uint32 # enum
# values for enumeration 'a6xx_debugbus_id'
a6xx_debugbus_id__enumvalues = {
1: 'A6XX_DBGBUS_CP',
2: 'A6XX_DBGBUS_RBBM',
3: 'A6XX_DBGBUS_VBIF',
4: 'A6XX_DBGBUS_HLSQ',
5: 'A6XX_DBGBUS_UCHE',
6: 'A6XX_DBGBUS_DPM',
7: 'A6XX_DBGBUS_TESS',
8: 'A6XX_DBGBUS_PC',
9: 'A6XX_DBGBUS_VFDP',
10: 'A6XX_DBGBUS_VPC',
11: 'A6XX_DBGBUS_TSE',
12: 'A6XX_DBGBUS_RAS',
13: 'A6XX_DBGBUS_VSC',
14: 'A6XX_DBGBUS_COM',
16: 'A6XX_DBGBUS_LRZ',
17: 'A6XX_DBGBUS_A2D',
18: 'A6XX_DBGBUS_CCUFCHE',
19: 'A6XX_DBGBUS_GMU_CX',
20: 'A6XX_DBGBUS_RBP',
21: 'A6XX_DBGBUS_DCS',
22: 'A6XX_DBGBUS_DBGC',
23: 'A6XX_DBGBUS_CX',
24: 'A6XX_DBGBUS_GMU_GX',
25: 'A6XX_DBGBUS_TPFCHE',
26: 'A6XX_DBGBUS_GBIF_GX',
29: 'A6XX_DBGBUS_GPC',
30: 'A6XX_DBGBUS_LARC',
31: 'A6XX_DBGBUS_HLSQ_SPTP',
32: 'A6XX_DBGBUS_RB_0',
33: 'A6XX_DBGBUS_RB_1',
34: 'A6XX_DBGBUS_RB_2',
36: 'A6XX_DBGBUS_UCHE_WRAPPER',
40: 'A6XX_DBGBUS_CCU_0',
41: 'A6XX_DBGBUS_CCU_1',
42: 'A6XX_DBGBUS_CCU_2',
56: 'A6XX_DBGBUS_VFD_0',
57: 'A6XX_DBGBUS_VFD_1',
58: 'A6XX_DBGBUS_VFD_2',
59: 'A6XX_DBGBUS_VFD_3',
60: 'A6XX_DBGBUS_VFD_4',
61: 'A6XX_DBGBUS_VFD_5',
64: 'A6XX_DBGBUS_SP_0',
65: 'A6XX_DBGBUS_SP_1',
66: 'A6XX_DBGBUS_SP_2',
72: 'A6XX_DBGBUS_TPL1_0',
73: 'A6XX_DBGBUS_TPL1_1',
74: 'A6XX_DBGBUS_TPL1_2',
75: 'A6XX_DBGBUS_TPL1_3',
76: 'A6XX_DBGBUS_TPL1_4',
77: 'A6XX_DBGBUS_TPL1_5',
88: 'A6XX_DBGBUS_SPTP_0',
89: 'A6XX_DBGBUS_SPTP_1',
90: 'A6XX_DBGBUS_SPTP_2',
91: 'A6XX_DBGBUS_SPTP_3',
92: 'A6XX_DBGBUS_SPTP_4',
93: 'A6XX_DBGBUS_SPTP_5',
}
A6XX_DBGBUS_CP = 1
A6XX_DBGBUS_RBBM = 2
A6XX_DBGBUS_VBIF = 3
A6XX_DBGBUS_HLSQ = 4
A6XX_DBGBUS_UCHE = 5
A6XX_DBGBUS_DPM = 6
A6XX_DBGBUS_TESS = 7
A6XX_DBGBUS_PC = 8
A6XX_DBGBUS_VFDP = 9
A6XX_DBGBUS_VPC = 10
A6XX_DBGBUS_TSE = 11
A6XX_DBGBUS_RAS = 12
A6XX_DBGBUS_VSC = 13
A6XX_DBGBUS_COM = 14
A6XX_DBGBUS_LRZ = 16
A6XX_DBGBUS_A2D = 17
A6XX_DBGBUS_CCUFCHE = 18
A6XX_DBGBUS_GMU_CX = 19
A6XX_DBGBUS_RBP = 20
A6XX_DBGBUS_DCS = 21
A6XX_DBGBUS_DBGC = 22
A6XX_DBGBUS_CX = 23
A6XX_DBGBUS_GMU_GX = 24
A6XX_DBGBUS_TPFCHE = 25
A6XX_DBGBUS_GBIF_GX = 26
A6XX_DBGBUS_GPC = 29
A6XX_DBGBUS_LARC = 30
A6XX_DBGBUS_HLSQ_SPTP = 31
A6XX_DBGBUS_RB_0 = 32
A6XX_DBGBUS_RB_1 = 33
A6XX_DBGBUS_RB_2 = 34
A6XX_DBGBUS_UCHE_WRAPPER = 36
A6XX_DBGBUS_CCU_0 = 40
A6XX_DBGBUS_CCU_1 = 41
A6XX_DBGBUS_CCU_2 = 42
A6XX_DBGBUS_VFD_0 = 56
A6XX_DBGBUS_VFD_1 = 57
A6XX_DBGBUS_VFD_2 = 58
A6XX_DBGBUS_VFD_3 = 59
A6XX_DBGBUS_VFD_4 = 60
A6XX_DBGBUS_VFD_5 = 61
A6XX_DBGBUS_SP_0 = 64
A6XX_DBGBUS_SP_1 = 65
A6XX_DBGBUS_SP_2 = 66
A6XX_DBGBUS_TPL1_0 = 72
A6XX_DBGBUS_TPL1_1 = 73
A6XX_DBGBUS_TPL1_2 = 74
A6XX_DBGBUS_TPL1_3 = 75
A6XX_DBGBUS_TPL1_4 = 76
A6XX_DBGBUS_TPL1_5 = 77
A6XX_DBGBUS_SPTP_0 = 88
A6XX_DBGBUS_SPTP_1 = 89
A6XX_DBGBUS_SPTP_2 = 90
A6XX_DBGBUS_SPTP_3 = 91
A6XX_DBGBUS_SPTP_4 = 92
A6XX_DBGBUS_SPTP_5 = 93
a6xx_debugbus_id = ctypes.c_uint32 # enum
# values for enumeration 'a7xx_state_location'
a7xx_state_location__enumvalues = {
0: 'A7XX_HLSQ_STATE',
1: 'A7XX_HLSQ_DP',
2: 'A7XX_SP_TOP',
3: 'A7XX_USPTP',
4: 'A7XX_HLSQ_DP_STR',
}
A7XX_HLSQ_STATE = 0
A7XX_HLSQ_DP = 1
A7XX_SP_TOP = 2
A7XX_USPTP = 3
A7XX_HLSQ_DP_STR = 4
a7xx_state_location = ctypes.c_uint32 # enum
# values for enumeration 'a7xx_pipe'
a7xx_pipe__enumvalues = {
0: 'A7XX_PIPE_NONE',
1: 'A7XX_PIPE_BR',
2: 'A7XX_PIPE_BV',
3: 'A7XX_PIPE_LPAC',
}
A7XX_PIPE_NONE = 0
A7XX_PIPE_BR = 1
A7XX_PIPE_BV = 2
A7XX_PIPE_LPAC = 3
a7xx_pipe = ctypes.c_uint32 # enum
# values for enumeration 'a7xx_cluster'
a7xx_cluster__enumvalues = {
0: 'A7XX_CLUSTER_NONE',
1: 'A7XX_CLUSTER_FE',
2: 'A7XX_CLUSTER_SP_VS',
3: 'A7XX_CLUSTER_PC_VS',
4: 'A7XX_CLUSTER_GRAS',
5: 'A7XX_CLUSTER_SP_PS',
6: 'A7XX_CLUSTER_VPC_PS',
7: 'A7XX_CLUSTER_PS',
}
A7XX_CLUSTER_NONE = 0
A7XX_CLUSTER_FE = 1
A7XX_CLUSTER_SP_VS = 2
A7XX_CLUSTER_PC_VS = 3
A7XX_CLUSTER_GRAS = 4
A7XX_CLUSTER_SP_PS = 5
A7XX_CLUSTER_VPC_PS = 6
A7XX_CLUSTER_PS = 7
a7xx_cluster = ctypes.c_uint32 # enum
# values for enumeration 'a7xx_debugbus_id'
a7xx_debugbus_id__enumvalues = {
1: 'A7XX_DBGBUS_CP_0_0',
2: 'A7XX_DBGBUS_CP_0_1',
3: 'A7XX_DBGBUS_RBBM',
5: 'A7XX_DBGBUS_GBIF_GX',
6: 'A7XX_DBGBUS_GBIF_CX',
7: 'A7XX_DBGBUS_HLSQ',
9: 'A7XX_DBGBUS_UCHE_0',
10: 'A7XX_DBGBUS_UCHE_1',
13: 'A7XX_DBGBUS_TESS_BR',
14: 'A7XX_DBGBUS_TESS_BV',
17: 'A7XX_DBGBUS_PC_BR',
18: 'A7XX_DBGBUS_PC_BV',
21: 'A7XX_DBGBUS_VFDP_BR',
22: 'A7XX_DBGBUS_VFDP_BV',
25: 'A7XX_DBGBUS_VPC_BR',
26: 'A7XX_DBGBUS_VPC_BV',
29: 'A7XX_DBGBUS_TSE_BR',
30: 'A7XX_DBGBUS_TSE_BV',
33: 'A7XX_DBGBUS_RAS_BR',
34: 'A7XX_DBGBUS_RAS_BV',
37: 'A7XX_DBGBUS_VSC',
39: 'A7XX_DBGBUS_COM_0',
43: 'A7XX_DBGBUS_LRZ_BR',
44: 'A7XX_DBGBUS_LRZ_BV',
47: 'A7XX_DBGBUS_UFC_0',
48: 'A7XX_DBGBUS_UFC_1',
55: 'A7XX_DBGBUS_GMU_GX',
59: 'A7XX_DBGBUS_DBGC',
60: 'A7XX_DBGBUS_CX',
61: 'A7XX_DBGBUS_GMU_CX',
62: 'A7XX_DBGBUS_GPC_BR',
63: 'A7XX_DBGBUS_GPC_BV',
66: 'A7XX_DBGBUS_LARC',
68: 'A7XX_DBGBUS_HLSQ_SPTP',
70: 'A7XX_DBGBUS_RB_0',
71: 'A7XX_DBGBUS_RB_1',
72: 'A7XX_DBGBUS_RB_2',
73: 'A7XX_DBGBUS_RB_3',
74: 'A7XX_DBGBUS_RB_4',
75: 'A7XX_DBGBUS_RB_5',
102: 'A7XX_DBGBUS_UCHE_WRAPPER',
106: 'A7XX_DBGBUS_CCU_0',
107: 'A7XX_DBGBUS_CCU_1',
108: 'A7XX_DBGBUS_CCU_2',
109: 'A7XX_DBGBUS_CCU_3',
110: 'A7XX_DBGBUS_CCU_4',
111: 'A7XX_DBGBUS_CCU_5',
138: 'A7XX_DBGBUS_VFD_BR_0',
139: 'A7XX_DBGBUS_VFD_BR_1',
140: 'A7XX_DBGBUS_VFD_BR_2',
141: 'A7XX_DBGBUS_VFD_BR_3',
142: 'A7XX_DBGBUS_VFD_BR_4',
143: 'A7XX_DBGBUS_VFD_BR_5',
144: 'A7XX_DBGBUS_VFD_BR_6',
145: 'A7XX_DBGBUS_VFD_BR_7',
202: 'A7XX_DBGBUS_VFD_BV_0',
203: 'A7XX_DBGBUS_VFD_BV_1',
204: 'A7XX_DBGBUS_VFD_BV_2',
205: 'A7XX_DBGBUS_VFD_BV_3',
234: 'A7XX_DBGBUS_USP_0',
235: 'A7XX_DBGBUS_USP_1',
236: 'A7XX_DBGBUS_USP_2',
237: 'A7XX_DBGBUS_USP_3',
238: 'A7XX_DBGBUS_USP_4',
239: 'A7XX_DBGBUS_USP_5',
266: 'A7XX_DBGBUS_TP_0',
267: 'A7XX_DBGBUS_TP_1',
268: 'A7XX_DBGBUS_TP_2',
269: 'A7XX_DBGBUS_TP_3',
270: 'A7XX_DBGBUS_TP_4',
271: 'A7XX_DBGBUS_TP_5',
272: 'A7XX_DBGBUS_TP_6',
273: 'A7XX_DBGBUS_TP_7',
274: 'A7XX_DBGBUS_TP_8',
275: 'A7XX_DBGBUS_TP_9',
276: 'A7XX_DBGBUS_TP_10',
277: 'A7XX_DBGBUS_TP_11',
330: 'A7XX_DBGBUS_USPTP_0',
331: 'A7XX_DBGBUS_USPTP_1',
332: 'A7XX_DBGBUS_USPTP_2',
333: 'A7XX_DBGBUS_USPTP_3',
334: 'A7XX_DBGBUS_USPTP_4',
335: 'A7XX_DBGBUS_USPTP_5',
336: 'A7XX_DBGBUS_USPTP_6',
337: 'A7XX_DBGBUS_USPTP_7',
338: 'A7XX_DBGBUS_USPTP_8',
339: 'A7XX_DBGBUS_USPTP_9',
340: 'A7XX_DBGBUS_USPTP_10',
341: 'A7XX_DBGBUS_USPTP_11',
396: 'A7XX_DBGBUS_CCHE_0',
397: 'A7XX_DBGBUS_CCHE_1',
398: 'A7XX_DBGBUS_CCHE_2',
408: 'A7XX_DBGBUS_VPC_DSTR_0',
409: 'A7XX_DBGBUS_VPC_DSTR_1',
410: 'A7XX_DBGBUS_VPC_DSTR_2',
411: 'A7XX_DBGBUS_HLSQ_DP_STR_0',
412: 'A7XX_DBGBUS_HLSQ_DP_STR_1',
413: 'A7XX_DBGBUS_HLSQ_DP_STR_2',
414: 'A7XX_DBGBUS_HLSQ_DP_STR_3',
415: 'A7XX_DBGBUS_HLSQ_DP_STR_4',
416: 'A7XX_DBGBUS_HLSQ_DP_STR_5',
443: 'A7XX_DBGBUS_UFC_DSTR_0',
444: 'A7XX_DBGBUS_UFC_DSTR_1',
445: 'A7XX_DBGBUS_UFC_DSTR_2',
446: 'A7XX_DBGBUS_CGC_SUBCORE',
447: 'A7XX_DBGBUS_CGC_CORE',
}
A7XX_DBGBUS_CP_0_0 = 1
A7XX_DBGBUS_CP_0_1 = 2
A7XX_DBGBUS_RBBM = 3
A7XX_DBGBUS_GBIF_GX = 5
A7XX_DBGBUS_GBIF_CX = 6
A7XX_DBGBUS_HLSQ = 7
A7XX_DBGBUS_UCHE_0 = 9
A7XX_DBGBUS_UCHE_1 = 10
A7XX_DBGBUS_TESS_BR = 13
A7XX_DBGBUS_TESS_BV = 14
A7XX_DBGBUS_PC_BR = 17
A7XX_DBGBUS_PC_BV = 18
A7XX_DBGBUS_VFDP_BR = 21
A7XX_DBGBUS_VFDP_BV = 22
A7XX_DBGBUS_VPC_BR = 25
A7XX_DBGBUS_VPC_BV = 26
A7XX_DBGBUS_TSE_BR = 29
A7XX_DBGBUS_TSE_BV = 30
A7XX_DBGBUS_RAS_BR = 33
A7XX_DBGBUS_RAS_BV = 34
A7XX_DBGBUS_VSC = 37
A7XX_DBGBUS_COM_0 = 39
A7XX_DBGBUS_LRZ_BR = 43
A7XX_DBGBUS_LRZ_BV = 44
A7XX_DBGBUS_UFC_0 = 47
A7XX_DBGBUS_UFC_1 = 48
A7XX_DBGBUS_GMU_GX = 55
A7XX_DBGBUS_DBGC = 59
A7XX_DBGBUS_CX = 60
A7XX_DBGBUS_GMU_CX = 61
A7XX_DBGBUS_GPC_BR = 62
A7XX_DBGBUS_GPC_BV = 63
A7XX_DBGBUS_LARC = 66
A7XX_DBGBUS_HLSQ_SPTP = 68
A7XX_DBGBUS_RB_0 = 70
A7XX_DBGBUS_RB_1 = 71
A7XX_DBGBUS_RB_2 = 72
A7XX_DBGBUS_RB_3 = 73
A7XX_DBGBUS_RB_4 = 74
A7XX_DBGBUS_RB_5 = 75
A7XX_DBGBUS_UCHE_WRAPPER = 102
A7XX_DBGBUS_CCU_0 = 106
A7XX_DBGBUS_CCU_1 = 107
A7XX_DBGBUS_CCU_2 = 108
A7XX_DBGBUS_CCU_3 = 109
A7XX_DBGBUS_CCU_4 = 110
A7XX_DBGBUS_CCU_5 = 111
A7XX_DBGBUS_VFD_BR_0 = 138
A7XX_DBGBUS_VFD_BR_1 = 139
A7XX_DBGBUS_VFD_BR_2 = 140
A7XX_DBGBUS_VFD_BR_3 = 141
A7XX_DBGBUS_VFD_BR_4 = 142
A7XX_DBGBUS_VFD_BR_5 = 143
A7XX_DBGBUS_VFD_BR_6 = 144
A7XX_DBGBUS_VFD_BR_7 = 145
A7XX_DBGBUS_VFD_BV_0 = 202
A7XX_DBGBUS_VFD_BV_1 = 203
A7XX_DBGBUS_VFD_BV_2 = 204
A7XX_DBGBUS_VFD_BV_3 = 205
A7XX_DBGBUS_USP_0 = 234
A7XX_DBGBUS_USP_1 = 235
A7XX_DBGBUS_USP_2 = 236
A7XX_DBGBUS_USP_3 = 237
A7XX_DBGBUS_USP_4 = 238
A7XX_DBGBUS_USP_5 = 239
A7XX_DBGBUS_TP_0 = 266
A7XX_DBGBUS_TP_1 = 267
A7XX_DBGBUS_TP_2 = 268
A7XX_DBGBUS_TP_3 = 269
A7XX_DBGBUS_TP_4 = 270
A7XX_DBGBUS_TP_5 = 271
A7XX_DBGBUS_TP_6 = 272
A7XX_DBGBUS_TP_7 = 273
A7XX_DBGBUS_TP_8 = 274
A7XX_DBGBUS_TP_9 = 275
A7XX_DBGBUS_TP_10 = 276
A7XX_DBGBUS_TP_11 = 277
A7XX_DBGBUS_USPTP_0 = 330
A7XX_DBGBUS_USPTP_1 = 331
A7XX_DBGBUS_USPTP_2 = 332
A7XX_DBGBUS_USPTP_3 = 333
A7XX_DBGBUS_USPTP_4 = 334
A7XX_DBGBUS_USPTP_5 = 335
A7XX_DBGBUS_USPTP_6 = 336
A7XX_DBGBUS_USPTP_7 = 337
A7XX_DBGBUS_USPTP_8 = 338
A7XX_DBGBUS_USPTP_9 = 339
A7XX_DBGBUS_USPTP_10 = 340
A7XX_DBGBUS_USPTP_11 = 341
A7XX_DBGBUS_CCHE_0 = 396
A7XX_DBGBUS_CCHE_1 = 397
A7XX_DBGBUS_CCHE_2 = 398
A7XX_DBGBUS_VPC_DSTR_0 = 408
A7XX_DBGBUS_VPC_DSTR_1 = 409
A7XX_DBGBUS_VPC_DSTR_2 = 410
A7XX_DBGBUS_HLSQ_DP_STR_0 = 411
A7XX_DBGBUS_HLSQ_DP_STR_1 = 412
A7XX_DBGBUS_HLSQ_DP_STR_2 = 413
A7XX_DBGBUS_HLSQ_DP_STR_3 = 414
A7XX_DBGBUS_HLSQ_DP_STR_4 = 415
A7XX_DBGBUS_HLSQ_DP_STR_5 = 416
A7XX_DBGBUS_UFC_DSTR_0 = 443
A7XX_DBGBUS_UFC_DSTR_1 = 444
A7XX_DBGBUS_UFC_DSTR_2 = 445
A7XX_DBGBUS_CGC_SUBCORE = 446
A7XX_DBGBUS_CGC_CORE = 447
a7xx_debugbus_id = ctypes.c_uint32 # enum
# values for enumeration 'a6xx_cp_perfcounter_select'
a6xx_cp_perfcounter_select__enumvalues = {
0: 'PERF_CP_ALWAYS_COUNT',
1: 'PERF_CP_BUSY_GFX_CORE_IDLE',
2: 'PERF_CP_BUSY_CYCLES',
3: 'PERF_CP_NUM_PREEMPTIONS',
4: 'PERF_CP_PREEMPTION_REACTION_DELAY',
5: 'PERF_CP_PREEMPTION_SWITCH_OUT_TIME',
6: 'PERF_CP_PREEMPTION_SWITCH_IN_TIME',
7: 'PERF_CP_DEAD_DRAWS_IN_BIN_RENDER',
8: 'PERF_CP_PREDICATED_DRAWS_KILLED',
9: 'PERF_CP_MODE_SWITCH',
10: 'PERF_CP_ZPASS_DONE',
11: 'PERF_CP_CONTEXT_DONE',
12: 'PERF_CP_CACHE_FLUSH',
13: 'PERF_CP_LONG_PREEMPTIONS',
14: 'PERF_CP_SQE_I_CACHE_STARVE',
15: 'PERF_CP_SQE_IDLE',
16: 'PERF_CP_SQE_PM4_STARVE_RB_IB',
17: 'PERF_CP_SQE_PM4_STARVE_SDS',
18: 'PERF_CP_SQE_MRB_STARVE',
19: 'PERF_CP_SQE_RRB_STARVE',
20: 'PERF_CP_SQE_VSD_STARVE',
21: 'PERF_CP_VSD_DECODE_STARVE',
22: 'PERF_CP_SQE_PIPE_OUT_STALL',
23: 'PERF_CP_SQE_SYNC_STALL',
24: 'PERF_CP_SQE_PM4_WFI_STALL',
25: 'PERF_CP_SQE_SYS_WFI_STALL',
26: 'PERF_CP_SQE_T4_EXEC',
27: 'PERF_CP_SQE_LOAD_STATE_EXEC',
28: 'PERF_CP_SQE_SAVE_SDS_STATE',
29: 'PERF_CP_SQE_DRAW_EXEC',
30: 'PERF_CP_SQE_CTXT_REG_BUNCH_EXEC',
31: 'PERF_CP_SQE_EXEC_PROFILED',
32: 'PERF_CP_MEMORY_POOL_EMPTY',
33: 'PERF_CP_MEMORY_POOL_SYNC_STALL',
34: 'PERF_CP_MEMORY_POOL_ABOVE_THRESH',
35: 'PERF_CP_AHB_WR_STALL_PRE_DRAWS',
36: 'PERF_CP_AHB_STALL_SQE_GMU',
37: 'PERF_CP_AHB_STALL_SQE_WR_OTHER',
38: 'PERF_CP_AHB_STALL_SQE_RD_OTHER',
39: 'PERF_CP_CLUSTER0_EMPTY',
40: 'PERF_CP_CLUSTER1_EMPTY',
41: 'PERF_CP_CLUSTER2_EMPTY',
42: 'PERF_CP_CLUSTER3_EMPTY',
43: 'PERF_CP_CLUSTER4_EMPTY',
44: 'PERF_CP_CLUSTER5_EMPTY',
45: 'PERF_CP_PM4_DATA',
46: 'PERF_CP_PM4_HEADERS',
47: 'PERF_CP_VBIF_READ_BEATS',
48: 'PERF_CP_VBIF_WRITE_BEATS',
49: 'PERF_CP_SQE_INSTR_COUNTER',
}
PERF_CP_ALWAYS_COUNT = 0
PERF_CP_BUSY_GFX_CORE_IDLE = 1
PERF_CP_BUSY_CYCLES = 2
PERF_CP_NUM_PREEMPTIONS = 3
PERF_CP_PREEMPTION_REACTION_DELAY = 4
PERF_CP_PREEMPTION_SWITCH_OUT_TIME = 5
PERF_CP_PREEMPTION_SWITCH_IN_TIME = 6
PERF_CP_DEAD_DRAWS_IN_BIN_RENDER = 7
PERF_CP_PREDICATED_DRAWS_KILLED = 8
PERF_CP_MODE_SWITCH = 9
PERF_CP_ZPASS_DONE = 10
PERF_CP_CONTEXT_DONE = 11
PERF_CP_CACHE_FLUSH = 12
PERF_CP_LONG_PREEMPTIONS = 13
PERF_CP_SQE_I_CACHE_STARVE = 14
PERF_CP_SQE_IDLE = 15
PERF_CP_SQE_PM4_STARVE_RB_IB = 16
PERF_CP_SQE_PM4_STARVE_SDS = 17
PERF_CP_SQE_MRB_STARVE = 18
PERF_CP_SQE_RRB_STARVE = 19
PERF_CP_SQE_VSD_STARVE = 20
PERF_CP_VSD_DECODE_STARVE = 21
PERF_CP_SQE_PIPE_OUT_STALL = 22
PERF_CP_SQE_SYNC_STALL = 23
PERF_CP_SQE_PM4_WFI_STALL = 24
PERF_CP_SQE_SYS_WFI_STALL = 25
PERF_CP_SQE_T4_EXEC = 26
PERF_CP_SQE_LOAD_STATE_EXEC = 27
PERF_CP_SQE_SAVE_SDS_STATE = 28
PERF_CP_SQE_DRAW_EXEC = 29
PERF_CP_SQE_CTXT_REG_BUNCH_EXEC = 30
PERF_CP_SQE_EXEC_PROFILED = 31
PERF_CP_MEMORY_POOL_EMPTY = 32
PERF_CP_MEMORY_POOL_SYNC_STALL = 33
PERF_CP_MEMORY_POOL_ABOVE_THRESH = 34
PERF_CP_AHB_WR_STALL_PRE_DRAWS = 35
PERF_CP_AHB_STALL_SQE_GMU = 36
PERF_CP_AHB_STALL_SQE_WR_OTHER = 37
PERF_CP_AHB_STALL_SQE_RD_OTHER = 38
PERF_CP_CLUSTER0_EMPTY = 39
PERF_CP_CLUSTER1_EMPTY = 40
PERF_CP_CLUSTER2_EMPTY = 41
PERF_CP_CLUSTER3_EMPTY = 42
PERF_CP_CLUSTER4_EMPTY = 43
PERF_CP_CLUSTER5_EMPTY = 44
PERF_CP_PM4_DATA = 45
PERF_CP_PM4_HEADERS = 46
PERF_CP_VBIF_READ_BEATS = 47
PERF_CP_VBIF_WRITE_BEATS = 48
PERF_CP_SQE_INSTR_COUNTER = 49
a6xx_cp_perfcounter_select = ctypes.c_uint32 # enum
# values for enumeration 'a6xx_rbbm_perfcounter_select'
a6xx_rbbm_perfcounter_select__enumvalues = {
0: 'PERF_RBBM_ALWAYS_COUNT',
1: 'PERF_RBBM_ALWAYS_ON',
2: 'PERF_RBBM_TSE_BUSY',
3: 'PERF_RBBM_RAS_BUSY',
4: 'PERF_RBBM_PC_DCALL_BUSY',
5: 'PERF_RBBM_PC_VSD_BUSY',
6: 'PERF_RBBM_STATUS_MASKED',
7: 'PERF_RBBM_COM_BUSY',
8: 'PERF_RBBM_DCOM_BUSY',
9: 'PERF_RBBM_VBIF_BUSY',
10: 'PERF_RBBM_VSC_BUSY',
11: 'PERF_RBBM_TESS_BUSY',
12: 'PERF_RBBM_UCHE_BUSY',
13: 'PERF_RBBM_HLSQ_BUSY',
}
PERF_RBBM_ALWAYS_COUNT = 0
PERF_RBBM_ALWAYS_ON = 1
PERF_RBBM_TSE_BUSY = 2
PERF_RBBM_RAS_BUSY = 3
PERF_RBBM_PC_DCALL_BUSY = 4
PERF_RBBM_PC_VSD_BUSY = 5
PERF_RBBM_STATUS_MASKED = 6
PERF_RBBM_COM_BUSY = 7
PERF_RBBM_DCOM_BUSY = 8
PERF_RBBM_VBIF_BUSY = 9
PERF_RBBM_VSC_BUSY = 10
PERF_RBBM_TESS_BUSY = 11
PERF_RBBM_UCHE_BUSY = 12
PERF_RBBM_HLSQ_BUSY = 13
a6xx_rbbm_perfcounter_select = ctypes.c_uint32 # enum
# values for enumeration 'a6xx_pc_perfcounter_select'
a6xx_pc_perfcounter_select__enumvalues = {
0: 'PERF_PC_BUSY_CYCLES',
1: 'PERF_PC_WORKING_CYCLES',
2: 'PERF_PC_STALL_CYCLES_VFD',
3: 'PERF_PC_STALL_CYCLES_TSE',
4: 'PERF_PC_STALL_CYCLES_VPC',
5: 'PERF_PC_STALL_CYCLES_UCHE',
6: 'PERF_PC_STALL_CYCLES_TESS',
7: 'PERF_PC_STALL_CYCLES_TSE_ONLY',
8: 'PERF_PC_STALL_CYCLES_VPC_ONLY',
9: 'PERF_PC_PASS1_TF_STALL_CYCLES',
10: 'PERF_PC_STARVE_CYCLES_FOR_INDEX',
11: 'PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR',
12: 'PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM',
13: 'PERF_PC_STARVE_CYCLES_FOR_POSITION',
14: 'PERF_PC_STARVE_CYCLES_DI',
15: 'PERF_PC_VIS_STREAMS_LOADED',
16: 'PERF_PC_INSTANCES',
17: 'PERF_PC_VPC_PRIMITIVES',
18: 'PERF_PC_DEAD_PRIM',
19: 'PERF_PC_LIVE_PRIM',
20: 'PERF_PC_VERTEX_HITS',
21: 'PERF_PC_IA_VERTICES',
22: 'PERF_PC_IA_PRIMITIVES',
23: 'PERF_PC_GS_PRIMITIVES',
24: 'PERF_PC_HS_INVOCATIONS',
25: 'PERF_PC_DS_INVOCATIONS',
26: 'PERF_PC_VS_INVOCATIONS',
27: 'PERF_PC_GS_INVOCATIONS',
28: 'PERF_PC_DS_PRIMITIVES',
29: 'PERF_PC_VPC_POS_DATA_TRANSACTION',
30: 'PERF_PC_3D_DRAWCALLS',
31: 'PERF_PC_2D_DRAWCALLS',
32: 'PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS',
33: 'PERF_TESS_BUSY_CYCLES',
34: 'PERF_TESS_WORKING_CYCLES',
35: 'PERF_TESS_STALL_CYCLES_PC',
36: 'PERF_TESS_STARVE_CYCLES_PC',
37: 'PERF_PC_TSE_TRANSACTION',
38: 'PERF_PC_TSE_VERTEX',
39: 'PERF_PC_TESS_PC_UV_TRANS',
40: 'PERF_PC_TESS_PC_UV_PATCHES',
41: 'PERF_PC_TESS_FACTOR_TRANS',
}
PERF_PC_BUSY_CYCLES = 0
PERF_PC_WORKING_CYCLES = 1
PERF_PC_STALL_CYCLES_VFD = 2
PERF_PC_STALL_CYCLES_TSE = 3
PERF_PC_STALL_CYCLES_VPC = 4
PERF_PC_STALL_CYCLES_UCHE = 5
PERF_PC_STALL_CYCLES_TESS = 6
PERF_PC_STALL_CYCLES_TSE_ONLY = 7
PERF_PC_STALL_CYCLES_VPC_ONLY = 8
PERF_PC_PASS1_TF_STALL_CYCLES = 9
PERF_PC_STARVE_CYCLES_FOR_INDEX = 10
PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR = 11
PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM = 12
PERF_PC_STARVE_CYCLES_FOR_POSITION = 13
PERF_PC_STARVE_CYCLES_DI = 14
PERF_PC_VIS_STREAMS_LOADED = 15
PERF_PC_INSTANCES = 16
PERF_PC_VPC_PRIMITIVES = 17
PERF_PC_DEAD_PRIM = 18
PERF_PC_LIVE_PRIM = 19
PERF_PC_VERTEX_HITS = 20
PERF_PC_IA_VERTICES = 21
PERF_PC_IA_PRIMITIVES = 22
PERF_PC_GS_PRIMITIVES = 23
PERF_PC_HS_INVOCATIONS = 24
PERF_PC_DS_INVOCATIONS = 25
PERF_PC_VS_INVOCATIONS = 26
PERF_PC_GS_INVOCATIONS = 27
PERF_PC_DS_PRIMITIVES = 28
PERF_PC_VPC_POS_DATA_TRANSACTION = 29
PERF_PC_3D_DRAWCALLS = 30
PERF_PC_2D_DRAWCALLS = 31
PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS = 32
PERF_TESS_BUSY_CYCLES = 33
PERF_TESS_WORKING_CYCLES = 34
PERF_TESS_STALL_CYCLES_PC = 35
PERF_TESS_STARVE_CYCLES_PC = 36
PERF_PC_TSE_TRANSACTION = 37
PERF_PC_TSE_VERTEX = 38
PERF_PC_TESS_PC_UV_TRANS = 39
PERF_PC_TESS_PC_UV_PATCHES = 40
PERF_PC_TESS_FACTOR_TRANS = 41
a6xx_pc_perfcounter_select = ctypes.c_uint32 # enum
# values for enumeration 'a6xx_vfd_perfcounter_select'
a6xx_vfd_perfcounter_select__enumvalues = {
0: 'PERF_VFD_BUSY_CYCLES',
1: 'PERF_VFD_STALL_CYCLES_UCHE',
2: 'PERF_VFD_STALL_CYCLES_VPC_ALLOC',
3: 'PERF_VFD_STALL_CYCLES_SP_INFO',
4: 'PERF_VFD_STALL_CYCLES_SP_ATTR',
5: 'PERF_VFD_STARVE_CYCLES_UCHE',
6: 'PERF_VFD_RBUFFER_FULL',
7: 'PERF_VFD_ATTR_INFO_FIFO_FULL',
8: 'PERF_VFD_DECODED_ATTRIBUTE_BYTES',
9: 'PERF_VFD_NUM_ATTRIBUTES',
10: 'PERF_VFD_UPPER_SHADER_FIBERS',
11: 'PERF_VFD_LOWER_SHADER_FIBERS',
12: 'PERF_VFD_MODE_0_FIBERS',
13: 'PERF_VFD_MODE_1_FIBERS',
14: 'PERF_VFD_MODE_2_FIBERS',
15: 'PERF_VFD_MODE_3_FIBERS',
16: 'PERF_VFD_MODE_4_FIBERS',
17: 'PERF_VFD_TOTAL_VERTICES',
18: 'PERF_VFDP_STALL_CYCLES_VFD',
19: 'PERF_VFDP_STALL_CYCLES_VFD_INDEX',
20: 'PERF_VFDP_STALL_CYCLES_VFD_PROG',
21: 'PERF_VFDP_STARVE_CYCLES_PC',
22: 'PERF_VFDP_VS_STAGE_WAVES',
}
PERF_VFD_BUSY_CYCLES = 0
PERF_VFD_STALL_CYCLES_UCHE = 1
PERF_VFD_STALL_CYCLES_VPC_ALLOC = 2
PERF_VFD_STALL_CYCLES_SP_INFO = 3
PERF_VFD_STALL_CYCLES_SP_ATTR = 4
PERF_VFD_STARVE_CYCLES_UCHE = 5
PERF_VFD_RBUFFER_FULL = 6
PERF_VFD_ATTR_INFO_FIFO_FULL = 7
PERF_VFD_DECODED_ATTRIBUTE_BYTES = 8
PERF_VFD_NUM_ATTRIBUTES = 9
PERF_VFD_UPPER_SHADER_FIBERS = 10
PERF_VFD_LOWER_SHADER_FIBERS = 11
PERF_VFD_MODE_0_FIBERS = 12
PERF_VFD_MODE_1_FIBERS = 13
PERF_VFD_MODE_2_FIBERS = 14
PERF_VFD_MODE_3_FIBERS = 15
PERF_VFD_MODE_4_FIBERS = 16
PERF_VFD_TOTAL_VERTICES = 17
PERF_VFDP_STALL_CYCLES_VFD = 18
PERF_VFDP_STALL_CYCLES_VFD_INDEX = 19
PERF_VFDP_STALL_CYCLES_VFD_PROG = 20
PERF_VFDP_STARVE_CYCLES_PC = 21
PERF_VFDP_VS_STAGE_WAVES = 22
a6xx_vfd_perfcounter_select = ctypes.c_uint32 # enum
# values for enumeration 'a6xx_hlsq_perfcounter_select'
a6xx_hlsq_perfcounter_select__enumvalues = {
0: 'PERF_HLSQ_BUSY_CYCLES',
1: 'PERF_HLSQ_STALL_CYCLES_UCHE',
2: 'PERF_HLSQ_STALL_CYCLES_SP_STATE',
3: 'PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE',
4: 'PERF_HLSQ_UCHE_LATENCY_CYCLES',
5: 'PERF_HLSQ_UCHE_LATENCY_COUNT',
6: 'PERF_HLSQ_FS_STAGE_1X_WAVES',
7: 'PERF_HLSQ_FS_STAGE_2X_WAVES',
8: 'PERF_HLSQ_QUADS',
9: 'PERF_HLSQ_CS_INVOCATIONS',
10: 'PERF_HLSQ_COMPUTE_DRAWCALLS',
11: 'PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING',
12: 'PERF_HLSQ_DUAL_FS_PROG_ACTIVE',
13: 'PERF_HLSQ_DUAL_VS_PROG_ACTIVE',
14: 'PERF_HLSQ_FS_BATCH_COUNT_ZERO',
15: 'PERF_HLSQ_VS_BATCH_COUNT_ZERO',
16: 'PERF_HLSQ_WAVE_PENDING_NO_QUAD',
17: 'PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE',
18: 'PERF_HLSQ_STALL_CYCLES_VPC',
19: 'PERF_HLSQ_PIXELS',
20: 'PERF_HLSQ_DRAW_MODE_SWITCH_VSFS_SYNC',
}
PERF_HLSQ_BUSY_CYCLES = 0
PERF_HLSQ_STALL_CYCLES_UCHE = 1
PERF_HLSQ_STALL_CYCLES_SP_STATE = 2
PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE = 3
PERF_HLSQ_UCHE_LATENCY_CYCLES = 4
PERF_HLSQ_UCHE_LATENCY_COUNT = 5
PERF_HLSQ_FS_STAGE_1X_WAVES = 6
PERF_HLSQ_FS_STAGE_2X_WAVES = 7
PERF_HLSQ_QUADS = 8
PERF_HLSQ_CS_INVOCATIONS = 9
PERF_HLSQ_COMPUTE_DRAWCALLS = 10
PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING = 11
PERF_HLSQ_DUAL_FS_PROG_ACTIVE = 12
PERF_HLSQ_DUAL_VS_PROG_ACTIVE = 13
PERF_HLSQ_FS_BATCH_COUNT_ZERO = 14
PERF_HLSQ_VS_BATCH_COUNT_ZERO = 15
PERF_HLSQ_WAVE_PENDING_NO_QUAD = 16
PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE = 17
PERF_HLSQ_STALL_CYCLES_VPC = 18
PERF_HLSQ_PIXELS = 19
PERF_HLSQ_DRAW_MODE_SWITCH_VSFS_SYNC = 20
a6xx_hlsq_perfcounter_select = ctypes.c_uint32 # enum
# values for enumeration 'a6xx_vpc_perfcounter_select'
a6xx_vpc_perfcounter_select__enumvalues = {
0: 'PERF_VPC_BUSY_CYCLES',
1: 'PERF_VPC_WORKING_CYCLES',
2: 'PERF_VPC_STALL_CYCLES_UCHE',
3: 'PERF_VPC_STALL_CYCLES_VFD_WACK',
4: 'PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC',
5: 'PERF_VPC_STALL_CYCLES_PC',
6: 'PERF_VPC_STALL_CYCLES_SP_LM',
7: 'PERF_VPC_STARVE_CYCLES_SP',
8: 'PERF_VPC_STARVE_CYCLES_LRZ',
9: 'PERF_VPC_PC_PRIMITIVES',
10: 'PERF_VPC_SP_COMPONENTS',
11: 'PERF_VPC_STALL_CYCLES_VPCRAM_POS',
12: 'PERF_VPC_LRZ_ASSIGN_PRIMITIVES',
13: 'PERF_VPC_RB_VISIBLE_PRIMITIVES',
14: 'PERF_VPC_LM_TRANSACTION',
15: 'PERF_VPC_STREAMOUT_TRANSACTION',
16: 'PERF_VPC_VS_BUSY_CYCLES',
17: 'PERF_VPC_PS_BUSY_CYCLES',
18: 'PERF_VPC_VS_WORKING_CYCLES',
19: 'PERF_VPC_PS_WORKING_CYCLES',
20: 'PERF_VPC_STARVE_CYCLES_RB',
21: 'PERF_VPC_NUM_VPCRAM_READ_POS',
22: 'PERF_VPC_WIT_FULL_CYCLES',
23: 'PERF_VPC_VPCRAM_FULL_CYCLES',
24: 'PERF_VPC_LM_FULL_WAIT_FOR_INTP_END',
25: 'PERF_VPC_NUM_VPCRAM_WRITE',
26: 'PERF_VPC_NUM_VPCRAM_READ_SO',
27: 'PERF_VPC_NUM_ATTR_REQ_LM',
}
PERF_VPC_BUSY_CYCLES = 0
PERF_VPC_WORKING_CYCLES = 1
PERF_VPC_STALL_CYCLES_UCHE = 2
PERF_VPC_STALL_CYCLES_VFD_WACK = 3
PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC = 4
PERF_VPC_STALL_CYCLES_PC = 5
PERF_VPC_STALL_CYCLES_SP_LM = 6
PERF_VPC_STARVE_CYCLES_SP = 7
PERF_VPC_STARVE_CYCLES_LRZ = 8
PERF_VPC_PC_PRIMITIVES = 9
PERF_VPC_SP_COMPONENTS = 10
PERF_VPC_STALL_CYCLES_VPCRAM_POS = 11
PERF_VPC_LRZ_ASSIGN_PRIMITIVES = 12
PERF_VPC_RB_VISIBLE_PRIMITIVES = 13
PERF_VPC_LM_TRANSACTION = 14
PERF_VPC_STREAMOUT_TRANSACTION = 15
PERF_VPC_VS_BUSY_CYCLES = 16
PERF_VPC_PS_BUSY_CYCLES = 17
PERF_VPC_VS_WORKING_CYCLES = 18
PERF_VPC_PS_WORKING_CYCLES = 19
PERF_VPC_STARVE_CYCLES_RB = 20
PERF_VPC_NUM_VPCRAM_READ_POS = 21
PERF_VPC_WIT_FULL_CYCLES = 22
PERF_VPC_VPCRAM_FULL_CYCLES = 23
PERF_VPC_LM_FULL_WAIT_FOR_INTP_END = 24
PERF_VPC_NUM_VPCRAM_WRITE = 25
PERF_VPC_NUM_VPCRAM_READ_SO = 26
PERF_VPC_NUM_ATTR_REQ_LM = 27
a6xx_vpc_perfcounter_select = ctypes.c_uint32 # enum
# values for enumeration 'a6xx_tse_perfcounter_select'
a6xx_tse_perfcounter_select__enumvalues = {
0: 'PERF_TSE_BUSY_CYCLES',
1: 'PERF_TSE_CLIPPING_CYCLES',
2: 'PERF_TSE_STALL_CYCLES_RAS',
3: 'PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE',
4: 'PERF_TSE_STALL_CYCLES_LRZ_ZPLANE',
5: 'PERF_TSE_STARVE_CYCLES_PC',
6: 'PERF_TSE_INPUT_PRIM',
7: 'PERF_TSE_INPUT_NULL_PRIM',
8: 'PERF_TSE_TRIVAL_REJ_PRIM',
9: 'PERF_TSE_CLIPPED_PRIM',
10: 'PERF_TSE_ZERO_AREA_PRIM',
11: 'PERF_TSE_FACENESS_CULLED_PRIM',
12: 'PERF_TSE_ZERO_PIXEL_PRIM',
13: 'PERF_TSE_OUTPUT_NULL_PRIM',
14: 'PERF_TSE_OUTPUT_VISIBLE_PRIM',
15: 'PERF_TSE_CINVOCATION',
16: 'PERF_TSE_CPRIMITIVES',
17: 'PERF_TSE_2D_INPUT_PRIM',
18: 'PERF_TSE_2D_ALIVE_CYCLES',
19: 'PERF_TSE_CLIP_PLANES',
}
PERF_TSE_BUSY_CYCLES = 0
PERF_TSE_CLIPPING_CYCLES = 1
PERF_TSE_STALL_CYCLES_RAS = 2
PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE = 3
PERF_TSE_STALL_CYCLES_LRZ_ZPLANE = 4
PERF_TSE_STARVE_CYCLES_PC = 5
PERF_TSE_INPUT_PRIM = 6
PERF_TSE_INPUT_NULL_PRIM = 7
PERF_TSE_TRIVAL_REJ_PRIM = 8
PERF_TSE_CLIPPED_PRIM = 9
PERF_TSE_ZERO_AREA_PRIM = 10
PERF_TSE_FACENESS_CULLED_PRIM = 11
PERF_TSE_ZERO_PIXEL_PRIM = 12
PERF_TSE_OUTPUT_NULL_PRIM = 13
PERF_TSE_OUTPUT_VISIBLE_PRIM = 14
PERF_TSE_CINVOCATION = 15
PERF_TSE_CPRIMITIVES = 16
PERF_TSE_2D_INPUT_PRIM = 17
PERF_TSE_2D_ALIVE_CYCLES = 18
PERF_TSE_CLIP_PLANES = 19
a6xx_tse_perfcounter_select = ctypes.c_uint32 # enum
# values for enumeration 'a6xx_ras_perfcounter_select'
a6xx_ras_perfcounter_select__enumvalues = {
0: 'PERF_RAS_BUSY_CYCLES',
1: 'PERF_RAS_SUPERTILE_ACTIVE_CYCLES',
2: 'PERF_RAS_STALL_CYCLES_LRZ',
3: 'PERF_RAS_STARVE_CYCLES_TSE',
4: 'PERF_RAS_SUPER_TILES',
5: 'PERF_RAS_8X4_TILES',
6: 'PERF_RAS_MASKGEN_ACTIVE',
7: 'PERF_RAS_FULLY_COVERED_SUPER_TILES',
8: 'PERF_RAS_FULLY_COVERED_8X4_TILES',
9: 'PERF_RAS_PRIM_KILLED_INVISILBE',
10: 'PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES',
11: 'PERF_RAS_LRZ_INTF_WORKING_CYCLES',
12: 'PERF_RAS_BLOCKS',
}
PERF_RAS_BUSY_CYCLES = 0
PERF_RAS_SUPERTILE_ACTIVE_CYCLES = 1
PERF_RAS_STALL_CYCLES_LRZ = 2
PERF_RAS_STARVE_CYCLES_TSE = 3
PERF_RAS_SUPER_TILES = 4
PERF_RAS_8X4_TILES = 5
PERF_RAS_MASKGEN_ACTIVE = 6
PERF_RAS_FULLY_COVERED_SUPER_TILES = 7
PERF_RAS_FULLY_COVERED_8X4_TILES = 8
PERF_RAS_PRIM_KILLED_INVISILBE = 9
PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES = 10
PERF_RAS_LRZ_INTF_WORKING_CYCLES = 11
PERF_RAS_BLOCKS = 12
a6xx_ras_perfcounter_select = ctypes.c_uint32 # enum
# values for enumeration 'a6xx_uche_perfcounter_select'
a6xx_uche_perfcounter_select__enumvalues = {
0: 'PERF_UCHE_BUSY_CYCLES',
1: 'PERF_UCHE_STALL_CYCLES_ARBITER',
2: 'PERF_UCHE_VBIF_LATENCY_CYCLES',
3: 'PERF_UCHE_VBIF_LATENCY_SAMPLES',
4: 'PERF_UCHE_VBIF_READ_BEATS_TP',
5: 'PERF_UCHE_VBIF_READ_BEATS_VFD',
6: 'PERF_UCHE_VBIF_READ_BEATS_HLSQ',
7: 'PERF_UCHE_VBIF_READ_BEATS_LRZ',
8: 'PERF_UCHE_VBIF_READ_BEATS_SP',
9: 'PERF_UCHE_READ_REQUESTS_TP',
10: 'PERF_UCHE_READ_REQUESTS_VFD',
11: 'PERF_UCHE_READ_REQUESTS_HLSQ',
12: 'PERF_UCHE_READ_REQUESTS_LRZ',
13: 'PERF_UCHE_READ_REQUESTS_SP',
14: 'PERF_UCHE_WRITE_REQUESTS_LRZ',
15: 'PERF_UCHE_WRITE_REQUESTS_SP',
16: 'PERF_UCHE_WRITE_REQUESTS_VPC',
17: 'PERF_UCHE_WRITE_REQUESTS_VSC',
18: 'PERF_UCHE_EVICTS',
19: 'PERF_UCHE_BANK_REQ0',
20: 'PERF_UCHE_BANK_REQ1',
21: 'PERF_UCHE_BANK_REQ2',
22: 'PERF_UCHE_BANK_REQ3',
23: 'PERF_UCHE_BANK_REQ4',
24: 'PERF_UCHE_BANK_REQ5',
25: 'PERF_UCHE_BANK_REQ6',
26: 'PERF_UCHE_BANK_REQ7',
27: 'PERF_UCHE_VBIF_READ_BEATS_CH0',
28: 'PERF_UCHE_VBIF_READ_BEATS_CH1',
29: 'PERF_UCHE_GMEM_READ_BEATS',
30: 'PERF_UCHE_TPH_REF_FULL',
31: 'PERF_UCHE_TPH_VICTIM_FULL',
32: 'PERF_UCHE_TPH_EXT_FULL',
33: 'PERF_UCHE_VBIF_STALL_WRITE_DATA',
34: 'PERF_UCHE_DCMP_LATENCY_SAMPLES',
35: 'PERF_UCHE_DCMP_LATENCY_CYCLES',
36: 'PERF_UCHE_VBIF_READ_BEATS_PC',
37: 'PERF_UCHE_READ_REQUESTS_PC',
38: 'PERF_UCHE_RAM_READ_REQ',
39: 'PERF_UCHE_RAM_WRITE_REQ',
}
PERF_UCHE_BUSY_CYCLES = 0
PERF_UCHE_STALL_CYCLES_ARBITER = 1
PERF_UCHE_VBIF_LATENCY_CYCLES = 2
PERF_UCHE_VBIF_LATENCY_SAMPLES = 3
PERF_UCHE_VBIF_READ_BEATS_TP = 4
PERF_UCHE_VBIF_READ_BEATS_VFD = 5
PERF_UCHE_VBIF_READ_BEATS_HLSQ = 6
PERF_UCHE_VBIF_READ_BEATS_LRZ = 7
PERF_UCHE_VBIF_READ_BEATS_SP = 8
PERF_UCHE_READ_REQUESTS_TP = 9
PERF_UCHE_READ_REQUESTS_VFD = 10
PERF_UCHE_READ_REQUESTS_HLSQ = 11
PERF_UCHE_READ_REQUESTS_LRZ = 12
PERF_UCHE_READ_REQUESTS_SP = 13
PERF_UCHE_WRITE_REQUESTS_LRZ = 14
PERF_UCHE_WRITE_REQUESTS_SP = 15
PERF_UCHE_WRITE_REQUESTS_VPC = 16
PERF_UCHE_WRITE_REQUESTS_VSC = 17
PERF_UCHE_EVICTS = 18
PERF_UCHE_BANK_REQ0 = 19
PERF_UCHE_BANK_REQ1 = 20
PERF_UCHE_BANK_REQ2 = 21
PERF_UCHE_BANK_REQ3 = 22
PERF_UCHE_BANK_REQ4 = 23
PERF_UCHE_BANK_REQ5 = 24
PERF_UCHE_BANK_REQ6 = 25
PERF_UCHE_BANK_REQ7 = 26
PERF_UCHE_VBIF_READ_BEATS_CH0 = 27
PERF_UCHE_VBIF_READ_BEATS_CH1 = 28
PERF_UCHE_GMEM_READ_BEATS = 29
PERF_UCHE_TPH_REF_FULL = 30
PERF_UCHE_TPH_VICTIM_FULL = 31
PERF_UCHE_TPH_EXT_FULL = 32
PERF_UCHE_VBIF_STALL_WRITE_DATA = 33
PERF_UCHE_DCMP_LATENCY_SAMPLES = 34
PERF_UCHE_DCMP_LATENCY_CYCLES = 35
PERF_UCHE_VBIF_READ_BEATS_PC = 36
PERF_UCHE_READ_REQUESTS_PC = 37
PERF_UCHE_RAM_READ_REQ = 38
PERF_UCHE_RAM_WRITE_REQ = 39
a6xx_uche_perfcounter_select = ctypes.c_uint32 # enum
# values for enumeration 'a6xx_tp_perfcounter_select'
a6xx_tp_perfcounter_select__enumvalues = {
0: 'PERF_TP_BUSY_CYCLES',
1: 'PERF_TP_STALL_CYCLES_UCHE',
2: 'PERF_TP_LATENCY_CYCLES',
3: 'PERF_TP_LATENCY_TRANS',
4: 'PERF_TP_FLAG_CACHE_REQUEST_SAMPLES',
5: 'PERF_TP_FLAG_CACHE_REQUEST_LATENCY',
6: 'PERF_TP_L1_CACHELINE_REQUESTS',
7: 'PERF_TP_L1_CACHELINE_MISSES',
8: 'PERF_TP_SP_TP_TRANS',
9: 'PERF_TP_TP_SP_TRANS',
10: 'PERF_TP_OUTPUT_PIXELS',
11: 'PERF_TP_FILTER_WORKLOAD_16BIT',
12: 'PERF_TP_FILTER_WORKLOAD_32BIT',
13: 'PERF_TP_QUADS_RECEIVED',
14: 'PERF_TP_QUADS_OFFSET',
15: 'PERF_TP_QUADS_SHADOW',
16: 'PERF_TP_QUADS_ARRAY',
17: 'PERF_TP_QUADS_GRADIENT',
18: 'PERF_TP_QUADS_1D',
19: 'PERF_TP_QUADS_2D',
20: 'PERF_TP_QUADS_BUFFER',
21: 'PERF_TP_QUADS_3D',
22: 'PERF_TP_QUADS_CUBE',
23: 'PERF_TP_DIVERGENT_QUADS_RECEIVED',
24: 'PERF_TP_PRT_NON_RESIDENT_EVENTS',
25: 'PERF_TP_OUTPUT_PIXELS_POINT',
26: 'PERF_TP_OUTPUT_PIXELS_BILINEAR',
27: 'PERF_TP_OUTPUT_PIXELS_MIP',
28: 'PERF_TP_OUTPUT_PIXELS_ANISO',
29: 'PERF_TP_OUTPUT_PIXELS_ZERO_LOD',
30: 'PERF_TP_FLAG_CACHE_REQUESTS',
31: 'PERF_TP_FLAG_CACHE_MISSES',
32: 'PERF_TP_L1_5_L2_REQUESTS',
33: 'PERF_TP_2D_OUTPUT_PIXELS',
34: 'PERF_TP_2D_OUTPUT_PIXELS_POINT',
35: 'PERF_TP_2D_OUTPUT_PIXELS_BILINEAR',
36: 'PERF_TP_2D_FILTER_WORKLOAD_16BIT',
37: 'PERF_TP_2D_FILTER_WORKLOAD_32BIT',
38: 'PERF_TP_TPA2TPC_TRANS',
39: 'PERF_TP_L1_MISSES_ASTC_1TILE',
40: 'PERF_TP_L1_MISSES_ASTC_2TILE',
41: 'PERF_TP_L1_MISSES_ASTC_4TILE',
42: 'PERF_TP_L1_5_L2_COMPRESS_REQS',
43: 'PERF_TP_L1_5_L2_COMPRESS_MISS',
44: 'PERF_TP_L1_BANK_CONFLICT',
45: 'PERF_TP_L1_5_MISS_LATENCY_CYCLES',
46: 'PERF_TP_L1_5_MISS_LATENCY_TRANS',
47: 'PERF_TP_QUADS_CONSTANT_MULTIPLIED',
48: 'PERF_TP_FRONTEND_WORKING_CYCLES',
49: 'PERF_TP_L1_TAG_WORKING_CYCLES',
50: 'PERF_TP_L1_DATA_WRITE_WORKING_CYCLES',
51: 'PERF_TP_PRE_L1_DECOM_WORKING_CYCLES',
52: 'PERF_TP_BACKEND_WORKING_CYCLES',
53: 'PERF_TP_FLAG_CACHE_WORKING_CYCLES',
54: 'PERF_TP_L1_5_CACHE_WORKING_CYCLES',
55: 'PERF_TP_STARVE_CYCLES_SP',
56: 'PERF_TP_STARVE_CYCLES_UCHE',
}
PERF_TP_BUSY_CYCLES = 0
PERF_TP_STALL_CYCLES_UCHE = 1
PERF_TP_LATENCY_CYCLES = 2
PERF_TP_LATENCY_TRANS = 3
PERF_TP_FLAG_CACHE_REQUEST_SAMPLES = 4
PERF_TP_FLAG_CACHE_REQUEST_LATENCY = 5
PERF_TP_L1_CACHELINE_REQUESTS = 6
PERF_TP_L1_CACHELINE_MISSES = 7
PERF_TP_SP_TP_TRANS = 8
PERF_TP_TP_SP_TRANS = 9
PERF_TP_OUTPUT_PIXELS = 10
PERF_TP_FILTER_WORKLOAD_16BIT = 11
PERF_TP_FILTER_WORKLOAD_32BIT = 12
PERF_TP_QUADS_RECEIVED = 13
PERF_TP_QUADS_OFFSET = 14
PERF_TP_QUADS_SHADOW = 15
PERF_TP_QUADS_ARRAY = 16
PERF_TP_QUADS_GRADIENT = 17
PERF_TP_QUADS_1D = 18
PERF_TP_QUADS_2D = 19
PERF_TP_QUADS_BUFFER = 20
PERF_TP_QUADS_3D = 21
PERF_TP_QUADS_CUBE = 22
PERF_TP_DIVERGENT_QUADS_RECEIVED = 23
PERF_TP_PRT_NON_RESIDENT_EVENTS = 24
PERF_TP_OUTPUT_PIXELS_POINT = 25
PERF_TP_OUTPUT_PIXELS_BILINEAR = 26
PERF_TP_OUTPUT_PIXELS_MIP = 27
PERF_TP_OUTPUT_PIXELS_ANISO = 28
PERF_TP_OUTPUT_PIXELS_ZERO_LOD = 29
PERF_TP_FLAG_CACHE_REQUESTS = 30
PERF_TP_FLAG_CACHE_MISSES = 31
PERF_TP_L1_5_L2_REQUESTS = 32
PERF_TP_2D_OUTPUT_PIXELS = 33
PERF_TP_2D_OUTPUT_PIXELS_POINT = 34
PERF_TP_2D_OUTPUT_PIXELS_BILINEAR = 35
PERF_TP_2D_FILTER_WORKLOAD_16BIT = 36
PERF_TP_2D_FILTER_WORKLOAD_32BIT = 37
PERF_TP_TPA2TPC_TRANS = 38
PERF_TP_L1_MISSES_ASTC_1TILE = 39
PERF_TP_L1_MISSES_ASTC_2TILE = 40
PERF_TP_L1_MISSES_ASTC_4TILE = 41
PERF_TP_L1_5_L2_COMPRESS_REQS = 42
PERF_TP_L1_5_L2_COMPRESS_MISS = 43
PERF_TP_L1_BANK_CONFLICT = 44
PERF_TP_L1_5_MISS_LATENCY_CYCLES = 45
PERF_TP_L1_5_MISS_LATENCY_TRANS = 46
PERF_TP_QUADS_CONSTANT_MULTIPLIED = 47
PERF_TP_FRONTEND_WORKING_CYCLES = 48
PERF_TP_L1_TAG_WORKING_CYCLES = 49
PERF_TP_L1_DATA_WRITE_WORKING_CYCLES = 50
PERF_TP_PRE_L1_DECOM_WORKING_CYCLES = 51
PERF_TP_BACKEND_WORKING_CYCLES = 52
PERF_TP_FLAG_CACHE_WORKING_CYCLES = 53
PERF_TP_L1_5_CACHE_WORKING_CYCLES = 54
PERF_TP_STARVE_CYCLES_SP = 55
PERF_TP_STARVE_CYCLES_UCHE = 56
a6xx_tp_perfcounter_select = ctypes.c_uint32 # enum
# values for enumeration 'a6xx_sp_perfcounter_select'
a6xx_sp_perfcounter_select__enumvalues = {
0: 'PERF_SP_BUSY_CYCLES',
1: 'PERF_SP_ALU_WORKING_CYCLES',
2: 'PERF_SP_EFU_WORKING_CYCLES',
3: 'PERF_SP_STALL_CYCLES_VPC',
4: 'PERF_SP_STALL_CYCLES_TP',
5: 'PERF_SP_STALL_CYCLES_UCHE',
6: 'PERF_SP_STALL_CYCLES_RB',
7: 'PERF_SP_NON_EXECUTION_CYCLES',
8: 'PERF_SP_WAVE_CONTEXTS',
9: 'PERF_SP_WAVE_CONTEXT_CYCLES',
10: 'PERF_SP_FS_STAGE_WAVE_CYCLES',
11: 'PERF_SP_FS_STAGE_WAVE_SAMPLES',
12: 'PERF_SP_VS_STAGE_WAVE_CYCLES',
13: 'PERF_SP_VS_STAGE_WAVE_SAMPLES',
14: 'PERF_SP_FS_STAGE_DURATION_CYCLES',
15: 'PERF_SP_VS_STAGE_DURATION_CYCLES',
16: 'PERF_SP_WAVE_CTRL_CYCLES',
17: 'PERF_SP_WAVE_LOAD_CYCLES',
18: 'PERF_SP_WAVE_EMIT_CYCLES',
19: 'PERF_SP_WAVE_NOP_CYCLES',
20: 'PERF_SP_WAVE_WAIT_CYCLES',
21: 'PERF_SP_WAVE_FETCH_CYCLES',
22: 'PERF_SP_WAVE_IDLE_CYCLES',
23: 'PERF_SP_WAVE_END_CYCLES',
24: 'PERF_SP_WAVE_LONG_SYNC_CYCLES',
25: 'PERF_SP_WAVE_SHORT_SYNC_CYCLES',
26: 'PERF_SP_WAVE_JOIN_CYCLES',
27: 'PERF_SP_LM_LOAD_INSTRUCTIONS',
28: 'PERF_SP_LM_STORE_INSTRUCTIONS',
29: 'PERF_SP_LM_ATOMICS',
30: 'PERF_SP_GM_LOAD_INSTRUCTIONS',
31: 'PERF_SP_GM_STORE_INSTRUCTIONS',
32: 'PERF_SP_GM_ATOMICS',
33: 'PERF_SP_VS_STAGE_TEX_INSTRUCTIONS',
34: 'PERF_SP_VS_STAGE_EFU_INSTRUCTIONS',
35: 'PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS',
36: 'PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS',
37: 'PERF_SP_FS_STAGE_TEX_INSTRUCTIONS',
38: 'PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS',
39: 'PERF_SP_FS_STAGE_EFU_INSTRUCTIONS',
40: 'PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS',
41: 'PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS',
42: 'PERF_SP_FS_STAGE_BARY_INSTRUCTIONS',
43: 'PERF_SP_VS_INSTRUCTIONS',
44: 'PERF_SP_FS_INSTRUCTIONS',
45: 'PERF_SP_ADDR_LOCK_COUNT',
46: 'PERF_SP_UCHE_READ_TRANS',
47: 'PERF_SP_UCHE_WRITE_TRANS',
48: 'PERF_SP_EXPORT_VPC_TRANS',
49: 'PERF_SP_EXPORT_RB_TRANS',
50: 'PERF_SP_PIXELS_KILLED',
51: 'PERF_SP_ICL1_REQUESTS',
52: 'PERF_SP_ICL1_MISSES',
53: 'PERF_SP_HS_INSTRUCTIONS',
54: 'PERF_SP_DS_INSTRUCTIONS',
55: 'PERF_SP_GS_INSTRUCTIONS',
56: 'PERF_SP_CS_INSTRUCTIONS',
57: 'PERF_SP_GPR_READ',
58: 'PERF_SP_GPR_WRITE',
59: 'PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS',
60: 'PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS',
61: 'PERF_SP_LM_BANK_CONFLICTS',
62: 'PERF_SP_TEX_CONTROL_WORKING_CYCLES',
63: 'PERF_SP_LOAD_CONTROL_WORKING_CYCLES',
64: 'PERF_SP_FLOW_CONTROL_WORKING_CYCLES',
65: 'PERF_SP_LM_WORKING_CYCLES',
66: 'PERF_SP_DISPATCHER_WORKING_CYCLES',
67: 'PERF_SP_SEQUENCER_WORKING_CYCLES',
68: 'PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP',
69: 'PERF_SP_STARVE_CYCLES_HLSQ',
70: 'PERF_SP_NON_EXECUTION_LS_CYCLES',
71: 'PERF_SP_WORKING_EU',
72: 'PERF_SP_ANY_EU_WORKING',
73: 'PERF_SP_WORKING_EU_FS_STAGE',
74: 'PERF_SP_ANY_EU_WORKING_FS_STAGE',
75: 'PERF_SP_WORKING_EU_VS_STAGE',
76: 'PERF_SP_ANY_EU_WORKING_VS_STAGE',
77: 'PERF_SP_WORKING_EU_CS_STAGE',
78: 'PERF_SP_ANY_EU_WORKING_CS_STAGE',
79: 'PERF_SP_GPR_READ_PREFETCH',
80: 'PERF_SP_GPR_READ_CONFLICT',
81: 'PERF_SP_GPR_WRITE_CONFLICT',
82: 'PERF_SP_GM_LOAD_LATENCY_CYCLES',
83: 'PERF_SP_GM_LOAD_LATENCY_SAMPLES',
84: 'PERF_SP_EXECUTABLE_WAVES',
}
PERF_SP_BUSY_CYCLES = 0
PERF_SP_ALU_WORKING_CYCLES = 1
PERF_SP_EFU_WORKING_CYCLES = 2
PERF_SP_STALL_CYCLES_VPC = 3
PERF_SP_STALL_CYCLES_TP = 4
PERF_SP_STALL_CYCLES_UCHE = 5
PERF_SP_STALL_CYCLES_RB = 6
PERF_SP_NON_EXECUTION_CYCLES = 7
PERF_SP_WAVE_CONTEXTS = 8
PERF_SP_WAVE_CONTEXT_CYCLES = 9
PERF_SP_FS_STAGE_WAVE_CYCLES = 10
PERF_SP_FS_STAGE_WAVE_SAMPLES = 11
PERF_SP_VS_STAGE_WAVE_CYCLES = 12
PERF_SP_VS_STAGE_WAVE_SAMPLES = 13
PERF_SP_FS_STAGE_DURATION_CYCLES = 14
PERF_SP_VS_STAGE_DURATION_CYCLES = 15
PERF_SP_WAVE_CTRL_CYCLES = 16
PERF_SP_WAVE_LOAD_CYCLES = 17
PERF_SP_WAVE_EMIT_CYCLES = 18
PERF_SP_WAVE_NOP_CYCLES = 19
PERF_SP_WAVE_WAIT_CYCLES = 20
PERF_SP_WAVE_FETCH_CYCLES = 21
PERF_SP_WAVE_IDLE_CYCLES = 22
PERF_SP_WAVE_END_CYCLES = 23
PERF_SP_WAVE_LONG_SYNC_CYCLES = 24
PERF_SP_WAVE_SHORT_SYNC_CYCLES = 25
PERF_SP_WAVE_JOIN_CYCLES = 26
PERF_SP_LM_LOAD_INSTRUCTIONS = 27
PERF_SP_LM_STORE_INSTRUCTIONS = 28
PERF_SP_LM_ATOMICS = 29
PERF_SP_GM_LOAD_INSTRUCTIONS = 30
PERF_SP_GM_STORE_INSTRUCTIONS = 31
PERF_SP_GM_ATOMICS = 32
PERF_SP_VS_STAGE_TEX_INSTRUCTIONS = 33
PERF_SP_VS_STAGE_EFU_INSTRUCTIONS = 34
PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS = 35
PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS = 36
PERF_SP_FS_STAGE_TEX_INSTRUCTIONS = 37
PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS = 38
PERF_SP_FS_STAGE_EFU_INSTRUCTIONS = 39
PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS = 40
PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS = 41
PERF_SP_FS_STAGE_BARY_INSTRUCTIONS = 42
PERF_SP_VS_INSTRUCTIONS = 43
PERF_SP_FS_INSTRUCTIONS = 44
PERF_SP_ADDR_LOCK_COUNT = 45
PERF_SP_UCHE_READ_TRANS = 46
PERF_SP_UCHE_WRITE_TRANS = 47
PERF_SP_EXPORT_VPC_TRANS = 48
PERF_SP_EXPORT_RB_TRANS = 49
PERF_SP_PIXELS_KILLED = 50
PERF_SP_ICL1_REQUESTS = 51
PERF_SP_ICL1_MISSES = 52
PERF_SP_HS_INSTRUCTIONS = 53
PERF_SP_DS_INSTRUCTIONS = 54
PERF_SP_GS_INSTRUCTIONS = 55
PERF_SP_CS_INSTRUCTIONS = 56
PERF_SP_GPR_READ = 57
PERF_SP_GPR_WRITE = 58
PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS = 59
PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS = 60
PERF_SP_LM_BANK_CONFLICTS = 61
PERF_SP_TEX_CONTROL_WORKING_CYCLES = 62
PERF_SP_LOAD_CONTROL_WORKING_CYCLES = 63
PERF_SP_FLOW_CONTROL_WORKING_CYCLES = 64
PERF_SP_LM_WORKING_CYCLES = 65
PERF_SP_DISPATCHER_WORKING_CYCLES = 66
PERF_SP_SEQUENCER_WORKING_CYCLES = 67
PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP = 68
PERF_SP_STARVE_CYCLES_HLSQ = 69
PERF_SP_NON_EXECUTION_LS_CYCLES = 70
PERF_SP_WORKING_EU = 71
PERF_SP_ANY_EU_WORKING = 72
PERF_SP_WORKING_EU_FS_STAGE = 73
PERF_SP_ANY_EU_WORKING_FS_STAGE = 74
PERF_SP_WORKING_EU_VS_STAGE = 75
PERF_SP_ANY_EU_WORKING_VS_STAGE = 76
PERF_SP_WORKING_EU_CS_STAGE = 77
PERF_SP_ANY_EU_WORKING_CS_STAGE = 78
PERF_SP_GPR_READ_PREFETCH = 79
PERF_SP_GPR_READ_CONFLICT = 80
PERF_SP_GPR_WRITE_CONFLICT = 81
PERF_SP_GM_LOAD_LATENCY_CYCLES = 82
PERF_SP_GM_LOAD_LATENCY_SAMPLES = 83
PERF_SP_EXECUTABLE_WAVES = 84
a6xx_sp_perfcounter_select = ctypes.c_uint32 # enum
# values for enumeration 'a6xx_rb_perfcounter_select'
a6xx_rb_perfcounter_select__enumvalues = {
0: 'PERF_RB_BUSY_CYCLES',
1: 'PERF_RB_STALL_CYCLES_HLSQ',
2: 'PERF_RB_STALL_CYCLES_FIFO0_FULL',
3: 'PERF_RB_STALL_CYCLES_FIFO1_FULL',
4: 'PERF_RB_STALL_CYCLES_FIFO2_FULL',
5: 'PERF_RB_STARVE_CYCLES_SP',
6: 'PERF_RB_STARVE_CYCLES_LRZ_TILE',
7: 'PERF_RB_STARVE_CYCLES_CCU',
8: 'PERF_RB_STARVE_CYCLES_Z_PLANE',
9: 'PERF_RB_STARVE_CYCLES_BARY_PLANE',
10: 'PERF_RB_Z_WORKLOAD',
11: 'PERF_RB_HLSQ_ACTIVE',
12: 'PERF_RB_Z_READ',
13: 'PERF_RB_Z_WRITE',
14: 'PERF_RB_C_READ',
15: 'PERF_RB_C_WRITE',
16: 'PERF_RB_TOTAL_PASS',
17: 'PERF_RB_Z_PASS',
18: 'PERF_RB_Z_FAIL',
19: 'PERF_RB_S_FAIL',
20: 'PERF_RB_BLENDED_FXP_COMPONENTS',
21: 'PERF_RB_BLENDED_FP16_COMPONENTS',
22: 'PERF_RB_PS_INVOCATIONS',
23: 'PERF_RB_2D_ALIVE_CYCLES',
24: 'PERF_RB_2D_STALL_CYCLES_A2D',
25: 'PERF_RB_2D_STARVE_CYCLES_SRC',
26: 'PERF_RB_2D_STARVE_CYCLES_SP',
27: 'PERF_RB_2D_STARVE_CYCLES_DST',
28: 'PERF_RB_2D_VALID_PIXELS',
29: 'PERF_RB_3D_PIXELS',
30: 'PERF_RB_BLENDER_WORKING_CYCLES',
31: 'PERF_RB_ZPROC_WORKING_CYCLES',
32: 'PERF_RB_CPROC_WORKING_CYCLES',
33: 'PERF_RB_SAMPLER_WORKING_CYCLES',
34: 'PERF_RB_STALL_CYCLES_CCU_COLOR_READ',
35: 'PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE',
36: 'PERF_RB_STALL_CYCLES_CCU_DEPTH_READ',
37: 'PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE',
38: 'PERF_RB_STALL_CYCLES_VPC',
39: 'PERF_RB_2D_INPUT_TRANS',
40: 'PERF_RB_2D_OUTPUT_RB_DST_TRANS',
41: 'PERF_RB_2D_OUTPUT_RB_SRC_TRANS',
42: 'PERF_RB_BLENDED_FP32_COMPONENTS',
43: 'PERF_RB_COLOR_PIX_TILES',
44: 'PERF_RB_STALL_CYCLES_CCU',
45: 'PERF_RB_EARLY_Z_ARB3_GRANT',
46: 'PERF_RB_LATE_Z_ARB3_GRANT',
47: 'PERF_RB_EARLY_Z_SKIP_GRANT',
}
PERF_RB_BUSY_CYCLES = 0
PERF_RB_STALL_CYCLES_HLSQ = 1
PERF_RB_STALL_CYCLES_FIFO0_FULL = 2
PERF_RB_STALL_CYCLES_FIFO1_FULL = 3
PERF_RB_STALL_CYCLES_FIFO2_FULL = 4
PERF_RB_STARVE_CYCLES_SP = 5
PERF_RB_STARVE_CYCLES_LRZ_TILE = 6
PERF_RB_STARVE_CYCLES_CCU = 7
PERF_RB_STARVE_CYCLES_Z_PLANE = 8
PERF_RB_STARVE_CYCLES_BARY_PLANE = 9
PERF_RB_Z_WORKLOAD = 10
PERF_RB_HLSQ_ACTIVE = 11
PERF_RB_Z_READ = 12
PERF_RB_Z_WRITE = 13
PERF_RB_C_READ = 14
PERF_RB_C_WRITE = 15
PERF_RB_TOTAL_PASS = 16
PERF_RB_Z_PASS = 17
PERF_RB_Z_FAIL = 18
PERF_RB_S_FAIL = 19
PERF_RB_BLENDED_FXP_COMPONENTS = 20
PERF_RB_BLENDED_FP16_COMPONENTS = 21
PERF_RB_PS_INVOCATIONS = 22
PERF_RB_2D_ALIVE_CYCLES = 23
PERF_RB_2D_STALL_CYCLES_A2D = 24
PERF_RB_2D_STARVE_CYCLES_SRC = 25
PERF_RB_2D_STARVE_CYCLES_SP = 26
PERF_RB_2D_STARVE_CYCLES_DST = 27
PERF_RB_2D_VALID_PIXELS = 28
PERF_RB_3D_PIXELS = 29
PERF_RB_BLENDER_WORKING_CYCLES = 30
PERF_RB_ZPROC_WORKING_CYCLES = 31
PERF_RB_CPROC_WORKING_CYCLES = 32
PERF_RB_SAMPLER_WORKING_CYCLES = 33
PERF_RB_STALL_CYCLES_CCU_COLOR_READ = 34
PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE = 35
PERF_RB_STALL_CYCLES_CCU_DEPTH_READ = 36
PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE = 37
PERF_RB_STALL_CYCLES_VPC = 38
PERF_RB_2D_INPUT_TRANS = 39
PERF_RB_2D_OUTPUT_RB_DST_TRANS = 40
PERF_RB_2D_OUTPUT_RB_SRC_TRANS = 41
PERF_RB_BLENDED_FP32_COMPONENTS = 42
PERF_RB_COLOR_PIX_TILES = 43
PERF_RB_STALL_CYCLES_CCU = 44
PERF_RB_EARLY_Z_ARB3_GRANT = 45
PERF_RB_LATE_Z_ARB3_GRANT = 46
PERF_RB_EARLY_Z_SKIP_GRANT = 47
a6xx_rb_perfcounter_select = ctypes.c_uint32 # enum
# values for enumeration 'a6xx_vsc_perfcounter_select'
a6xx_vsc_perfcounter_select__enumvalues = {
0: 'PERF_VSC_BUSY_CYCLES',
1: 'PERF_VSC_WORKING_CYCLES',
2: 'PERF_VSC_STALL_CYCLES_UCHE',
3: 'PERF_VSC_EOT_NUM',
4: 'PERF_VSC_INPUT_TILES',
}
PERF_VSC_BUSY_CYCLES = 0
PERF_VSC_WORKING_CYCLES = 1
PERF_VSC_STALL_CYCLES_UCHE = 2
PERF_VSC_EOT_NUM = 3
PERF_VSC_INPUT_TILES = 4
a6xx_vsc_perfcounter_select = ctypes.c_uint32 # enum
# values for enumeration 'a6xx_ccu_perfcounter_select'
a6xx_ccu_perfcounter_select__enumvalues = {
0: 'PERF_CCU_BUSY_CYCLES',
1: 'PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN',
2: 'PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN',
3: 'PERF_CCU_STARVE_CYCLES_FLAG_RETURN',
4: 'PERF_CCU_DEPTH_BLOCKS',
5: 'PERF_CCU_COLOR_BLOCKS',
6: 'PERF_CCU_DEPTH_BLOCK_HIT',
7: 'PERF_CCU_COLOR_BLOCK_HIT',
8: 'PERF_CCU_PARTIAL_BLOCK_READ',
9: 'PERF_CCU_GMEM_READ',
10: 'PERF_CCU_GMEM_WRITE',
11: 'PERF_CCU_DEPTH_READ_FLAG0_COUNT',
12: 'PERF_CCU_DEPTH_READ_FLAG1_COUNT',
13: 'PERF_CCU_DEPTH_READ_FLAG2_COUNT',
14: 'PERF_CCU_DEPTH_READ_FLAG3_COUNT',
15: 'PERF_CCU_DEPTH_READ_FLAG4_COUNT',
16: 'PERF_CCU_DEPTH_READ_FLAG5_COUNT',
17: 'PERF_CCU_DEPTH_READ_FLAG6_COUNT',
18: 'PERF_CCU_DEPTH_READ_FLAG8_COUNT',
19: 'PERF_CCU_COLOR_READ_FLAG0_COUNT',
20: 'PERF_CCU_COLOR_READ_FLAG1_COUNT',
21: 'PERF_CCU_COLOR_READ_FLAG2_COUNT',
22: 'PERF_CCU_COLOR_READ_FLAG3_COUNT',
23: 'PERF_CCU_COLOR_READ_FLAG4_COUNT',
24: 'PERF_CCU_COLOR_READ_FLAG5_COUNT',
25: 'PERF_CCU_COLOR_READ_FLAG6_COUNT',
26: 'PERF_CCU_COLOR_READ_FLAG8_COUNT',
27: 'PERF_CCU_2D_RD_REQ',
28: 'PERF_CCU_2D_WR_REQ',
}
PERF_CCU_BUSY_CYCLES = 0
PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN = 1
PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN = 2
PERF_CCU_STARVE_CYCLES_FLAG_RETURN = 3
PERF_CCU_DEPTH_BLOCKS = 4
PERF_CCU_COLOR_BLOCKS = 5
PERF_CCU_DEPTH_BLOCK_HIT = 6
PERF_CCU_COLOR_BLOCK_HIT = 7
PERF_CCU_PARTIAL_BLOCK_READ = 8
PERF_CCU_GMEM_READ = 9
PERF_CCU_GMEM_WRITE = 10
PERF_CCU_DEPTH_READ_FLAG0_COUNT = 11
PERF_CCU_DEPTH_READ_FLAG1_COUNT = 12
PERF_CCU_DEPTH_READ_FLAG2_COUNT = 13
PERF_CCU_DEPTH_READ_FLAG3_COUNT = 14
PERF_CCU_DEPTH_READ_FLAG4_COUNT = 15
PERF_CCU_DEPTH_READ_FLAG5_COUNT = 16
PERF_CCU_DEPTH_READ_FLAG6_COUNT = 17
PERF_CCU_DEPTH_READ_FLAG8_COUNT = 18
PERF_CCU_COLOR_READ_FLAG0_COUNT = 19
PERF_CCU_COLOR_READ_FLAG1_COUNT = 20
PERF_CCU_COLOR_READ_FLAG2_COUNT = 21
PERF_CCU_COLOR_READ_FLAG3_COUNT = 22
PERF_CCU_COLOR_READ_FLAG4_COUNT = 23
PERF_CCU_COLOR_READ_FLAG5_COUNT = 24
PERF_CCU_COLOR_READ_FLAG6_COUNT = 25
PERF_CCU_COLOR_READ_FLAG8_COUNT = 26
PERF_CCU_2D_RD_REQ = 27
PERF_CCU_2D_WR_REQ = 28
a6xx_ccu_perfcounter_select = ctypes.c_uint32 # enum
# values for enumeration 'a6xx_lrz_perfcounter_select'
a6xx_lrz_perfcounter_select__enumvalues = {
0: 'PERF_LRZ_BUSY_CYCLES',
1: 'PERF_LRZ_STARVE_CYCLES_RAS',
2: 'PERF_LRZ_STALL_CYCLES_RB',
3: 'PERF_LRZ_STALL_CYCLES_VSC',
4: 'PERF_LRZ_STALL_CYCLES_VPC',
5: 'PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH',
6: 'PERF_LRZ_STALL_CYCLES_UCHE',
7: 'PERF_LRZ_LRZ_READ',
8: 'PERF_LRZ_LRZ_WRITE',
9: 'PERF_LRZ_READ_LATENCY',
10: 'PERF_LRZ_MERGE_CACHE_UPDATING',
11: 'PERF_LRZ_PRIM_KILLED_BY_MASKGEN',
12: 'PERF_LRZ_PRIM_KILLED_BY_LRZ',
13: 'PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ',
14: 'PERF_LRZ_FULL_8X8_TILES',
15: 'PERF_LRZ_PARTIAL_8X8_TILES',
16: 'PERF_LRZ_TILE_KILLED',
17: 'PERF_LRZ_TOTAL_PIXEL',
18: 'PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ',
19: 'PERF_LRZ_FULLY_COVERED_TILES',
20: 'PERF_LRZ_PARTIAL_COVERED_TILES',
21: 'PERF_LRZ_FEEDBACK_ACCEPT',
22: 'PERF_LRZ_FEEDBACK_DISCARD',
23: 'PERF_LRZ_FEEDBACK_STALL',
24: 'PERF_LRZ_STALL_CYCLES_RB_ZPLANE',
25: 'PERF_LRZ_STALL_CYCLES_RB_BPLANE',
26: 'PERF_LRZ_STALL_CYCLES_VC',
27: 'PERF_LRZ_RAS_MASK_TRANS',
}
PERF_LRZ_BUSY_CYCLES = 0
PERF_LRZ_STARVE_CYCLES_RAS = 1
PERF_LRZ_STALL_CYCLES_RB = 2
PERF_LRZ_STALL_CYCLES_VSC = 3
PERF_LRZ_STALL_CYCLES_VPC = 4
PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH = 5
PERF_LRZ_STALL_CYCLES_UCHE = 6
PERF_LRZ_LRZ_READ = 7
PERF_LRZ_LRZ_WRITE = 8
PERF_LRZ_READ_LATENCY = 9
PERF_LRZ_MERGE_CACHE_UPDATING = 10
PERF_LRZ_PRIM_KILLED_BY_MASKGEN = 11
PERF_LRZ_PRIM_KILLED_BY_LRZ = 12
PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ = 13
PERF_LRZ_FULL_8X8_TILES = 14
PERF_LRZ_PARTIAL_8X8_TILES = 15
PERF_LRZ_TILE_KILLED = 16
PERF_LRZ_TOTAL_PIXEL = 17
PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ = 18
PERF_LRZ_FULLY_COVERED_TILES = 19
PERF_LRZ_PARTIAL_COVERED_TILES = 20
PERF_LRZ_FEEDBACK_ACCEPT = 21
PERF_LRZ_FEEDBACK_DISCARD = 22
PERF_LRZ_FEEDBACK_STALL = 23
PERF_LRZ_STALL_CYCLES_RB_ZPLANE = 24
PERF_LRZ_STALL_CYCLES_RB_BPLANE = 25
PERF_LRZ_STALL_CYCLES_VC = 26
PERF_LRZ_RAS_MASK_TRANS = 27
a6xx_lrz_perfcounter_select = ctypes.c_uint32 # enum
# values for enumeration 'a6xx_cmp_perfcounter_select'
a6xx_cmp_perfcounter_select__enumvalues = {
0: 'PERF_CMPDECMP_STALL_CYCLES_ARB',
1: 'PERF_CMPDECMP_VBIF_LATENCY_CYCLES',
2: 'PERF_CMPDECMP_VBIF_LATENCY_SAMPLES',
3: 'PERF_CMPDECMP_VBIF_READ_DATA_CCU',
4: 'PERF_CMPDECMP_VBIF_WRITE_DATA_CCU',
5: 'PERF_CMPDECMP_VBIF_READ_REQUEST',
6: 'PERF_CMPDECMP_VBIF_WRITE_REQUEST',
7: 'PERF_CMPDECMP_VBIF_READ_DATA',
8: 'PERF_CMPDECMP_VBIF_WRITE_DATA',
9: 'PERF_CMPDECMP_FLAG_FETCH_CYCLES',
10: 'PERF_CMPDECMP_FLAG_FETCH_SAMPLES',
11: 'PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT',
12: 'PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT',
13: 'PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT',
14: 'PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT',
15: 'PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT',
16: 'PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT',
17: 'PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT',
18: 'PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT',
19: 'PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT',
20: 'PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT',
21: 'PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT',
22: 'PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT',
23: 'PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT',
24: 'PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT',
25: 'PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ',
26: 'PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR',
27: 'PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN',
28: 'PERF_CMPDECMP_2D_RD_DATA',
29: 'PERF_CMPDECMP_2D_WR_DATA',
30: 'PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0',
31: 'PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1',
32: 'PERF_CMPDECMP_2D_OUTPUT_TRANS',
33: 'PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE',
34: 'PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT',
35: 'PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT',
36: 'PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT',
37: 'PERF_CMPDECMP_2D_BUSY_CYCLES',
38: 'PERF_CMPDECMP_2D_REORDER_STARVE_CYCLES',
39: 'PERF_CMPDECMP_2D_PIXELS',
}
PERF_CMPDECMP_STALL_CYCLES_ARB = 0
PERF_CMPDECMP_VBIF_LATENCY_CYCLES = 1
PERF_CMPDECMP_VBIF_LATENCY_SAMPLES = 2
PERF_CMPDECMP_VBIF_READ_DATA_CCU = 3
PERF_CMPDECMP_VBIF_WRITE_DATA_CCU = 4
PERF_CMPDECMP_VBIF_READ_REQUEST = 5
PERF_CMPDECMP_VBIF_WRITE_REQUEST = 6
PERF_CMPDECMP_VBIF_READ_DATA = 7
PERF_CMPDECMP_VBIF_WRITE_DATA = 8
PERF_CMPDECMP_FLAG_FETCH_CYCLES = 9
PERF_CMPDECMP_FLAG_FETCH_SAMPLES = 10
PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT = 11
PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT = 12
PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT = 13
PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT = 14
PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT = 15
PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT = 16
PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT = 17
PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT = 18
PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT = 19
PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT = 20
PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT = 21
PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT = 22
PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT = 23
PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT = 24
PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ = 25
PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR = 26
PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN = 27
PERF_CMPDECMP_2D_RD_DATA = 28
PERF_CMPDECMP_2D_WR_DATA = 29
PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0 = 30
PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1 = 31
PERF_CMPDECMP_2D_OUTPUT_TRANS = 32
PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE = 33
PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT = 34
PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT = 35
PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT = 36
PERF_CMPDECMP_2D_BUSY_CYCLES = 37
PERF_CMPDECMP_2D_REORDER_STARVE_CYCLES = 38
PERF_CMPDECMP_2D_PIXELS = 39
a6xx_cmp_perfcounter_select = ctypes.c_uint32 # enum
# values for enumeration 'a6xx_2d_ifmt'
a6xx_2d_ifmt__enumvalues = {
16: 'R2D_UNORM8',
7: 'R2D_INT32',
6: 'R2D_INT16',
5: 'R2D_INT8',
4: 'R2D_FLOAT32',
3: 'R2D_FLOAT16',
1: 'R2D_UNORM8_SRGB',
0: 'R2D_RAW',
}
R2D_UNORM8 = 16
R2D_INT32 = 7
R2D_INT16 = 6
R2D_INT8 = 5
R2D_FLOAT32 = 4
R2D_FLOAT16 = 3
R2D_UNORM8_SRGB = 1
R2D_RAW = 0
a6xx_2d_ifmt = ctypes.c_uint32 # enum
# values for enumeration 'a6xx_ztest_mode'
a6xx_ztest_mode__enumvalues = {
0: 'A6XX_EARLY_Z',
1: 'A6XX_LATE_Z',
2: 'A6XX_EARLY_LRZ_LATE_Z',
3: 'A6XX_INVALID_ZTEST',
}
A6XX_EARLY_Z = 0
A6XX_LATE_Z = 1
A6XX_EARLY_LRZ_LATE_Z = 2
A6XX_INVALID_ZTEST = 3
a6xx_ztest_mode = ctypes.c_uint32 # enum
# values for enumeration 'a6xx_tess_spacing'
a6xx_tess_spacing__enumvalues = {
0: 'TESS_EQUAL',
2: 'TESS_FRACTIONAL_ODD',
3: 'TESS_FRACTIONAL_EVEN',
}
TESS_EQUAL = 0
TESS_FRACTIONAL_ODD = 2
TESS_FRACTIONAL_EVEN = 3
a6xx_tess_spacing = ctypes.c_uint32 # enum
# values for enumeration 'a6xx_tess_output'
a6xx_tess_output__enumvalues = {
0: 'TESS_POINTS',
1: 'TESS_LINES',
2: 'TESS_CW_TRIS',
3: 'TESS_CCW_TRIS',
}
TESS_POINTS = 0
TESS_LINES = 1
TESS_CW_TRIS = 2
TESS_CCW_TRIS = 3
a6xx_tess_output = ctypes.c_uint32 # enum
# values for enumeration 'a7xx_cp_perfcounter_select'
a7xx_cp_perfcounter_select__enumvalues = {
0: 'A7XX_PERF_CP_NEVER_COUNT',
1: 'A7XX_PERF_CP_ALWAYS_COUNT',
2: 'A7XX_PERF_CP_BUSY_GFX_CORE_IDLE',
3: 'A7XX_PERF_CP_BUSY_CYCLES',
4: 'A7XX_PERF_CP_NUM_PREEMPTIONS',
5: 'A7XX_PERF_CP_PREEMPTION_REACTION_DELAY',
6: 'A7XX_PERF_CP_PREEMPTION_SWITCH_OUT_TIME',
7: 'A7XX_PERF_CP_PREEMPTION_SWITCH_IN_TIME',
8: 'A7XX_PERF_CP_DEAD_DRAWS_IN_BIN_RENDER',
9: 'A7XX_PERF_CP_PREDICATED_DRAWS_KILLED',
10: 'A7XX_PERF_CP_MODE_SWITCH',
11: 'A7XX_PERF_CP_ZPASS_DONE',
12: 'A7XX_PERF_CP_CONTEXT_DONE',
13: 'A7XX_PERF_CP_CACHE_FLUSH',
14: 'A7XX_PERF_CP_LONG_PREEMPTIONS',
15: 'A7XX_PERF_CP_SQE_I_CACHE_STARVE',
16: 'A7XX_PERF_CP_SQE_IDLE',
17: 'A7XX_PERF_CP_SQE_PM4_STARVE_RB',
18: 'A7XX_PERF_CP_SQE_PM4_STARVE_IB1',
19: 'A7XX_PERF_CP_SQE_PM4_STARVE_IB2',
20: 'A7XX_PERF_CP_SQE_PM4_STARVE_IB3',
21: 'A7XX_PERF_CP_SQE_PM4_STARVE_FSDT',
22: 'A7XX_PERF_CP_SQE_PM4_STARVE_SDS',
23: 'A7XX_PERF_CP_SQE_MRB_STARVE',
24: 'A7XX_PERF_CP_SQE_RRB_STARVE',
25: 'A7XX_PERF_CP_SQE_VSD_STARVE',
26: 'A7XX_PERF_CP_VSD_DECODE_STARVE',
27: 'A7XX_PERF_CP_SQE_PIPE_OUT_STALL',
28: 'A7XX_PERF_CP_SQE_SYNC_STALL',
29: 'A7XX_PERF_CP_SQE_PM4_WFI_STALL',
30: 'A7XX_PERF_CP_SQE_SYS_WFI_STALL',
31: 'A7XX_PERF_CP_WAIT_ON_OTHER_PIPE',
32: 'A7XX_PERF_CP_OUTPUT_BLOCKED',
33: 'A7XX_PERF_CP_SQE_T4_EXEC',
34: 'A7XX_PERF_CP_SQE_LOAD_STATE_EXEC',
35: 'A7XX_PERF_CP_SQE_SAVE_SDS_STATE',
36: 'A7XX_PERF_CP_SQE_DRAW_EXEC',
37: 'A7XX_PERF_CP_SQE_CTXT_REG_BUNCH_EXEC',
38: 'A7XX_PERF_CP_SQE_EXEC_PROFILED',
39: 'A7XX_PERF_CP_MEMORY_POOL_EMPTY',
40: 'A7XX_PERF_CP_MEMORY_POOL_SYNC_STALL',
41: 'A7XX_PERF_CP_MEMORY_POOL_ABOVE_THRESH',
42: 'A7XX_PERF_CP_MEMORY_POOL_BELOW_THRESH',
43: 'A7XX_PERF_CP_AHB_WR_STALL_PRE_DRAWS',
44: 'A7XX_PERF_CP_AHB_STALL_SQE_GMU',
45: 'A7XX_PERF_CP_AHB_STALL_SQE_WR_OTHER',
46: 'A7XX_PERF_CP_AHB_STALL_SQE_RD_OTHER',
47: 'A7XX_PERF_CP_CLUSTER_FE_U_EMPTY',
48: 'A7XX_PERF_CP_CLUSTER_FE_S_EMPTY',
49: 'A7XX_PERF_CP_CLUSTER_SP_VS_EMPTY',
50: 'A7XX_PERF_CP_CLUSTER_VPC_US_EMPTY',
51: 'A7XX_PERF_CP_CLUSTER_VPC_VS_EMPTY',
52: 'A7XX_PERF_CP_CLUSTER_GRAS_EMPTY',
53: 'A7XX_PERF_CP_CLUSTER_SP_PS_EMPTY',
54: 'A7XX_PERF_CP_CLUSTER_VPC_PS_EMPTY',
55: 'A7XX_PERF_CP_CLUSTER_PS_EMPTY',
56: 'A7XX_PERF_CP_PM4_DATA',
57: 'A7XX_PERF_CP_PM4_HEADERS',
58: 'A7XX_PERF_CP_VBIF_READ_BEATS',
59: 'A7XX_PERF_CP_VBIF_WRITE_BEATS',
60: 'A7XX_PERF_CP_SQE_INSTR_COUNTER',
61: 'A7XX_PERF_CP_CLUSTER_FE_US_FULL',
62: 'A7XX_PERF_CP_CLUSTER_FE_S_FULL',
63: 'A7XX_PERF_CP_CLUSTER_SP_VS_FULL',
64: 'A7XX_PERF_CP_CLUSTER_VPC_US_FULL',
65: 'A7XX_PERF_CP_CLUSTER_VPC_VS_FULL',
66: 'A7XX_PERF_CP_CLUSTER_GRAS_FULL',
67: 'A7XX_PERF_CP_CLUSTER_SP_PS_FULL',
68: 'A7XX_PERF_CP_CLUSTER_VPC_PS_FULL',
69: 'A7XX_PERF_CP_CLUSTER_PS_FULL',
70: 'A7XX_PERF_CP_ICACHE_MISSES',
71: 'A7XX_PERF_CP_ICACHE_HITS',
72: 'A7XX_PERF_CP_ICACHE_STALL',
73: 'A7XX_PERF_CP_DCACHE_MISSES',
74: 'A7XX_PERF_CP_DCACHE_HITS',
75: 'A7XX_PERF_CP_DCACHE_STALLS',
76: 'A7XX_PERF_CP_AQE_SQE_STALL',
77: 'A7XX_PERF_CP_SQE_AQE_STARVE',
78: 'A7XX_PERF_CP_ISR_CYCLES',
79: 'A7XX_PERF_CP_SQE_MD8_STALL_CYCLES',
80: 'A7XX_PERF_CP_SQE_MESH_EXEC_CYCLES',
81: 'A7XX_PERF_CP_AQE_NUM_AS_CHUNKS',
82: 'A7XX_PERF_CP_AQE_NUM_MS_CHUNKS',
83: 'A7XX_PERF_CP_S_SKEW_BUFFER_FULL',
84: 'A7XX_PERF_CP_S_SKEW_BUFFER_ABOVE_THRESH',
}
A7XX_PERF_CP_NEVER_COUNT = 0
A7XX_PERF_CP_ALWAYS_COUNT = 1
A7XX_PERF_CP_BUSY_GFX_CORE_IDLE = 2
A7XX_PERF_CP_BUSY_CYCLES = 3
A7XX_PERF_CP_NUM_PREEMPTIONS = 4
A7XX_PERF_CP_PREEMPTION_REACTION_DELAY = 5
A7XX_PERF_CP_PREEMPTION_SWITCH_OUT_TIME = 6
A7XX_PERF_CP_PREEMPTION_SWITCH_IN_TIME = 7
A7XX_PERF_CP_DEAD_DRAWS_IN_BIN_RENDER = 8
A7XX_PERF_CP_PREDICATED_DRAWS_KILLED = 9
A7XX_PERF_CP_MODE_SWITCH = 10
A7XX_PERF_CP_ZPASS_DONE = 11
A7XX_PERF_CP_CONTEXT_DONE = 12
A7XX_PERF_CP_CACHE_FLUSH = 13
A7XX_PERF_CP_LONG_PREEMPTIONS = 14
A7XX_PERF_CP_SQE_I_CACHE_STARVE = 15
A7XX_PERF_CP_SQE_IDLE = 16
A7XX_PERF_CP_SQE_PM4_STARVE_RB = 17
A7XX_PERF_CP_SQE_PM4_STARVE_IB1 = 18
A7XX_PERF_CP_SQE_PM4_STARVE_IB2 = 19
A7XX_PERF_CP_SQE_PM4_STARVE_IB3 = 20
A7XX_PERF_CP_SQE_PM4_STARVE_FSDT = 21
A7XX_PERF_CP_SQE_PM4_STARVE_SDS = 22
A7XX_PERF_CP_SQE_MRB_STARVE = 23
A7XX_PERF_CP_SQE_RRB_STARVE = 24
A7XX_PERF_CP_SQE_VSD_STARVE = 25
A7XX_PERF_CP_VSD_DECODE_STARVE = 26
A7XX_PERF_CP_SQE_PIPE_OUT_STALL = 27
A7XX_PERF_CP_SQE_SYNC_STALL = 28
A7XX_PERF_CP_SQE_PM4_WFI_STALL = 29
A7XX_PERF_CP_SQE_SYS_WFI_STALL = 30
A7XX_PERF_CP_WAIT_ON_OTHER_PIPE = 31
A7XX_PERF_CP_OUTPUT_BLOCKED = 32
A7XX_PERF_CP_SQE_T4_EXEC = 33
A7XX_PERF_CP_SQE_LOAD_STATE_EXEC = 34
A7XX_PERF_CP_SQE_SAVE_SDS_STATE = 35
A7XX_PERF_CP_SQE_DRAW_EXEC = 36
A7XX_PERF_CP_SQE_CTXT_REG_BUNCH_EXEC = 37
A7XX_PERF_CP_SQE_EXEC_PROFILED = 38
A7XX_PERF_CP_MEMORY_POOL_EMPTY = 39
A7XX_PERF_CP_MEMORY_POOL_SYNC_STALL = 40
A7XX_PERF_CP_MEMORY_POOL_ABOVE_THRESH = 41
A7XX_PERF_CP_MEMORY_POOL_BELOW_THRESH = 42
A7XX_PERF_CP_AHB_WR_STALL_PRE_DRAWS = 43
A7XX_PERF_CP_AHB_STALL_SQE_GMU = 44
A7XX_PERF_CP_AHB_STALL_SQE_WR_OTHER = 45
A7XX_PERF_CP_AHB_STALL_SQE_RD_OTHER = 46
A7XX_PERF_CP_CLUSTER_FE_U_EMPTY = 47
A7XX_PERF_CP_CLUSTER_FE_S_EMPTY = 48
A7XX_PERF_CP_CLUSTER_SP_VS_EMPTY = 49
A7XX_PERF_CP_CLUSTER_VPC_US_EMPTY = 50
A7XX_PERF_CP_CLUSTER_VPC_VS_EMPTY = 51
A7XX_PERF_CP_CLUSTER_GRAS_EMPTY = 52
A7XX_PERF_CP_CLUSTER_SP_PS_EMPTY = 53
A7XX_PERF_CP_CLUSTER_VPC_PS_EMPTY = 54
A7XX_PERF_CP_CLUSTER_PS_EMPTY = 55
A7XX_PERF_CP_PM4_DATA = 56
A7XX_PERF_CP_PM4_HEADERS = 57
A7XX_PERF_CP_VBIF_READ_BEATS = 58
A7XX_PERF_CP_VBIF_WRITE_BEATS = 59
A7XX_PERF_CP_SQE_INSTR_COUNTER = 60
A7XX_PERF_CP_CLUSTER_FE_US_FULL = 61
A7XX_PERF_CP_CLUSTER_FE_S_FULL = 62
A7XX_PERF_CP_CLUSTER_SP_VS_FULL = 63
A7XX_PERF_CP_CLUSTER_VPC_US_FULL = 64
A7XX_PERF_CP_CLUSTER_VPC_VS_FULL = 65
A7XX_PERF_CP_CLUSTER_GRAS_FULL = 66
A7XX_PERF_CP_CLUSTER_SP_PS_FULL = 67
A7XX_PERF_CP_CLUSTER_VPC_PS_FULL = 68
A7XX_PERF_CP_CLUSTER_PS_FULL = 69
A7XX_PERF_CP_ICACHE_MISSES = 70
A7XX_PERF_CP_ICACHE_HITS = 71
A7XX_PERF_CP_ICACHE_STALL = 72
A7XX_PERF_CP_DCACHE_MISSES = 73
A7XX_PERF_CP_DCACHE_HITS = 74
A7XX_PERF_CP_DCACHE_STALLS = 75
A7XX_PERF_CP_AQE_SQE_STALL = 76
A7XX_PERF_CP_SQE_AQE_STARVE = 77
A7XX_PERF_CP_ISR_CYCLES = 78
A7XX_PERF_CP_SQE_MD8_STALL_CYCLES = 79
A7XX_PERF_CP_SQE_MESH_EXEC_CYCLES = 80
A7XX_PERF_CP_AQE_NUM_AS_CHUNKS = 81
A7XX_PERF_CP_AQE_NUM_MS_CHUNKS = 82
A7XX_PERF_CP_S_SKEW_BUFFER_FULL = 83
A7XX_PERF_CP_S_SKEW_BUFFER_ABOVE_THRESH = 84
a7xx_cp_perfcounter_select = ctypes.c_uint32 # enum
# values for enumeration 'a7xx_rbbm_perfcounter_select'
a7xx_rbbm_perfcounter_select__enumvalues = {
0: 'A7XX_PERF_RBBM_NEVER_COUNT',
1: 'A7XX_PERF_RBBM_US_ALWAYS_COUNT',
2: 'A7XX_PERF_RBBM_US_ALWAYS_ON',
3: 'A7XX_PERF_RBBM_US_STATUS_MASKED',
4: 'A7XX_PERF_RBBM_US_PC_BUSY',
5: 'A7XX_PERF_RBBM_US_COM_BUSY',
6: 'A7XX_PERF_RBBM_US_DCOM_BUSY',
7: 'A7XX_PERF_RBBM_US_VBIF_BUSY',
8: 'A7XX_PERF_RBBM_US_VSC_BUSY',
9: 'A7XX_PERF_RBBM_US_UCHE_BUSY',
10: 'A7XX_PERF_RBBM_US_HLSQ_BUSY',
11: 'A7XX_PERF_RBBM_S_HLSQ_BUSY',
12: 'A7XX_PERF_RBBM_S_PC_BUSY',
13: 'A7XX_PERF_RBBM_S_TESS_BUSY',
14: 'A7XX_PERF_RBBM_S_TSEFE_BUSY',
15: 'A7XX_PERF_RBBM_S_TSEBE_BUSY',
16: 'A7XX_PERF_RBBM_S_RAS_BUSY',
}
A7XX_PERF_RBBM_NEVER_COUNT = 0
A7XX_PERF_RBBM_US_ALWAYS_COUNT = 1
A7XX_PERF_RBBM_US_ALWAYS_ON = 2
A7XX_PERF_RBBM_US_STATUS_MASKED = 3
A7XX_PERF_RBBM_US_PC_BUSY = 4
A7XX_PERF_RBBM_US_COM_BUSY = 5
A7XX_PERF_RBBM_US_DCOM_BUSY = 6
A7XX_PERF_RBBM_US_VBIF_BUSY = 7
A7XX_PERF_RBBM_US_VSC_BUSY = 8
A7XX_PERF_RBBM_US_UCHE_BUSY = 9
A7XX_PERF_RBBM_US_HLSQ_BUSY = 10
A7XX_PERF_RBBM_S_HLSQ_BUSY = 11
A7XX_PERF_RBBM_S_PC_BUSY = 12
A7XX_PERF_RBBM_S_TESS_BUSY = 13
A7XX_PERF_RBBM_S_TSEFE_BUSY = 14
A7XX_PERF_RBBM_S_TSEBE_BUSY = 15
A7XX_PERF_RBBM_S_RAS_BUSY = 16
a7xx_rbbm_perfcounter_select = ctypes.c_uint32 # enum
# values for enumeration 'a7xx_pc_perfcounter_select'
a7xx_pc_perfcounter_select__enumvalues = {
0: 'A7XX_PERF_PC_NEVER_COUNT',
1: 'A7XX_PERF_PC_US_BUSY_CYCLES',
2: 'A7XX_PERF_PC_US_WORKING_CYCLES',
3: 'A7XX_PERF_PC_US_UCHE_OUTSTANDING_TRANS',
4: 'A7XX_PERF_PC_US_PASS1_TF_STALL_CYCLES',
5: 'A7XX_PERF_PC_US_STARVE_CYCLES_FOR_INDEX',
6: 'A7XX_PERF_PC_US_STARVE_CYCLES_FOR_TF',
7: 'A7XX_PERF_PC_US_STARVE_CYCLES_FOR_VIZ_STREAM',
8: 'A7XX_PERF_PC_US_STARVE_CYCLES_DI',
9: 'A7XX_PERF_PC_US_VIS_STREAMS_LOADED',
10: 'A7XX_PERF_PC_US_INSTANCES',
11: 'A7XX_PERF_PC_US_DEAD_PRIM',
12: 'A7XX_PERF_PC_US_SLICE_LIVE_PRIM',
13: 'A7XX_PERF_PC_US_3D_DRAWCALLS',
14: 'A7XX_PERF_PC_US_2D_DRAWCALLS',
15: 'A7XX_PERF_PC_US_NON_DRAWCALL_GLOBAL_EVENTS',
16: 'A7XX_PERF_PC_US_MESH_DRAWS',
17: 'A7XX_PERF_PC_US_MESH_DEAD_DRAWS',
18: 'A7XX_PERF_PC_US_MESH_MVIS_EN_DRAWS',
19: 'A7XX_PERF_PC_US_MESH_DEAD_PRIM',
20: 'A7XX_PERF_PC_US_MESH_LIVE_PRIM',
21: 'A7XX_PERF_PC_US_MESH_PA_EN_PRIM',
22: 'A7XX_PERF_PC_US_STARVE_CYCLES_FOR_MVIS_STREAM',
23: 'A7XX_PERF_PC_US_STARVE_CYCLES_PREDRAW',
24: 'A7XX_PERF_PC_US_STALL_CYCLES_COMPUTE_GFX',
25: 'A7XX_PERF_PC_US_STALL_CYCLES_GFX_COMPUTE',
26: 'A7XX_PERF_PC_US_PREDRAW_STALLS',
27: 'A7XX_PERF_PC_US_DP0_INPUT_STALLS',
28: 'A7XX_PERF_PC_US_DP1_INPUT_STALLS',
29: 'A7XX_PERF_PC_US_BR_STALLS_BV_WORKLOAD',
30: 'A7XX_PERF_PC_US_BV_STALLS_BR_WORKLOAD',
31: 'A7XX_PERF_PC_US_PASSPAIR_STALL',
32: 'A7XX_PERF_PC_US_STALL_CYCLES_UCHE0',
33: 'A7XX_PERF_PC_US_STALL_CYCLES_UCHE1',
34: 'A7XX_PERF_PC_US_UCHE_0_TRANS',
35: 'A7XX_PERF_PC_US_UCHE_1_TRANS',
36: 'A7XX_PERF_PC_US_BV_STALLED_BY_ATTR',
37: 'A7XX_PERF_PC_US_BV_STARVED_BY_RARB',
38: 'A7XX_PERF_PC_US_VPC_PRIM_COUNT_STALLS_BR',
39: 'A7XX_PERF_PC_US_VPC_PRIM_COUNT_STALLS_BV',
40: 'A7XX_PERF_PC_US_BV_STALLED_BY_UCHE_FEEDBACK',
41: 'A7XX_PERF_PC_US_VSD_RARB_DVIZ_FULL',
42: 'A7XX_PERF_PC_US_VSD_RARB_PVIZ_FULL',
43: 'A7XX_PERF_PC_US_VSD_RARB_TVIZ_FULL',
44: 'A7XX_PERF_PC_US_DP0_RARB_FULL',
45: 'A7XX_PERF_PC_US_DP1_RARB_FULL',
46: 'A7XX_PERF_PC_US_DP0_LIVE_PRIM',
47: 'A7XX_PERF_PC_US_DP1_LIVE_PRIM',
48: 'A7XX_PERF_PC_US_BV2BR_SWITCH',
49: 'A7XX_PERF_PC_US_BR2BV_SWITCH',
50: 'A7XX_PERF_PC_US_STALL_CYCLES_PC_S',
51: 'A7XX_PERF_PC_RESERVED_51',
52: 'A7XX_PERF_PC_RESERVED_52',
53: 'A7XX_PERF_PC_RESERVED_53',
54: 'A7XX_PERF_PC_RESERVED_54',
55: 'A7XX_PERF_PC_RESERVED_55',
56: 'A7XX_PERF_PC_RESERVED_56',
57: 'A7XX_PERF_PC_RESERVED_57',
58: 'A7XX_PERF_PC_RESERVED_58',
59: 'A7XX_PERF_PC_RESERVED_59',
60: 'A7XX_PERF_PC_S_BUSY_CYCLES',
61: 'A7XX_PERF_PC_S_WORKING_CYCLES',
62: 'A7XX_PERF_PC_S_STALL_CYCLES_VFD',
63: 'A7XX_PERF_PC_S_STALL_CYCLES_VPC_FE',
64: 'A7XX_PERF_PC_S_STALL_CYCLES_TESS',
65: 'A7XX_PERF_PC_S_STALL_CYCLES_VFD_ONLY',
66: 'A7XX_PERF_PC_S_STALL_CYCLES_VPC_ONLY',
67: 'A7XX_PERF_PC_S_VPC_PRIMITIVES',
68: 'A7XX_PERF_PC_S_VERTEX_HITS',
69: 'A7XX_PERF_PC_S_IA_VERTICES',
70: 'A7XX_PERF_PC_S_IA_PRIMITIVES',
71: 'A7XX_PERF_PC_S_HS_INVOCATIONS',
72: 'A7XX_PERF_PC_S_DS_INVOCATIONS',
73: 'A7XX_PERF_PC_S_VS_INVOCATIONS',
74: 'A7XX_PERF_PC_S_GS_INVOCATIONS',
75: 'A7XX_PERF_PC_S_DS_PRIMITIVES',
76: 'A7XX_PERF_PC_S_TESS_BUSY_CYCLES',
77: 'A7XX_PERF_PC_S_TESS_WORKING_CYCLES',
78: 'A7XX_PERF_PC_S_TESS_STALL_CYCLES_PC',
79: 'A7XX_PERF_PC_S_TESS_STARVE_CYCLES_PC',
80: 'A7XX_PERF_PC_S_TESS_SETUP_ACTIVE',
81: 'A7XX_PERF_PC_S_TESS_PID_ACTIVE',
82: 'A7XX_PERF_PC_S_TESS_PRIM_GEN_ACTIVE',
83: 'A7XX_PERF_PC_S_TESS_FACTOR_TRANS',
84: 'A7XX_PERF_PC_S_TESS_PC_UV_TRANS',
85: 'A7XX_PERF_PC_S_TESS_PC_UV_PATCHES',
86: 'A7XX_PERF_PC_S_MESH_VS_WAVES',
}
A7XX_PERF_PC_NEVER_COUNT = 0
A7XX_PERF_PC_US_BUSY_CYCLES = 1
A7XX_PERF_PC_US_WORKING_CYCLES = 2
A7XX_PERF_PC_US_UCHE_OUTSTANDING_TRANS = 3
A7XX_PERF_PC_US_PASS1_TF_STALL_CYCLES = 4
A7XX_PERF_PC_US_STARVE_CYCLES_FOR_INDEX = 5
A7XX_PERF_PC_US_STARVE_CYCLES_FOR_TF = 6
A7XX_PERF_PC_US_STARVE_CYCLES_FOR_VIZ_STREAM = 7
A7XX_PERF_PC_US_STARVE_CYCLES_DI = 8
A7XX_PERF_PC_US_VIS_STREAMS_LOADED = 9
A7XX_PERF_PC_US_INSTANCES = 10
A7XX_PERF_PC_US_DEAD_PRIM = 11
A7XX_PERF_PC_US_SLICE_LIVE_PRIM = 12
A7XX_PERF_PC_US_3D_DRAWCALLS = 13
A7XX_PERF_PC_US_2D_DRAWCALLS = 14
A7XX_PERF_PC_US_NON_DRAWCALL_GLOBAL_EVENTS = 15
A7XX_PERF_PC_US_MESH_DRAWS = 16
A7XX_PERF_PC_US_MESH_DEAD_DRAWS = 17
A7XX_PERF_PC_US_MESH_MVIS_EN_DRAWS = 18
A7XX_PERF_PC_US_MESH_DEAD_PRIM = 19
A7XX_PERF_PC_US_MESH_LIVE_PRIM = 20
A7XX_PERF_PC_US_MESH_PA_EN_PRIM = 21
A7XX_PERF_PC_US_STARVE_CYCLES_FOR_MVIS_STREAM = 22
A7XX_PERF_PC_US_STARVE_CYCLES_PREDRAW = 23
A7XX_PERF_PC_US_STALL_CYCLES_COMPUTE_GFX = 24
A7XX_PERF_PC_US_STALL_CYCLES_GFX_COMPUTE = 25
A7XX_PERF_PC_US_PREDRAW_STALLS = 26
A7XX_PERF_PC_US_DP0_INPUT_STALLS = 27
A7XX_PERF_PC_US_DP1_INPUT_STALLS = 28
A7XX_PERF_PC_US_BR_STALLS_BV_WORKLOAD = 29
A7XX_PERF_PC_US_BV_STALLS_BR_WORKLOAD = 30
A7XX_PERF_PC_US_PASSPAIR_STALL = 31
A7XX_PERF_PC_US_STALL_CYCLES_UCHE0 = 32
A7XX_PERF_PC_US_STALL_CYCLES_UCHE1 = 33
A7XX_PERF_PC_US_UCHE_0_TRANS = 34
A7XX_PERF_PC_US_UCHE_1_TRANS = 35
A7XX_PERF_PC_US_BV_STALLED_BY_ATTR = 36
A7XX_PERF_PC_US_BV_STARVED_BY_RARB = 37
A7XX_PERF_PC_US_VPC_PRIM_COUNT_STALLS_BR = 38
A7XX_PERF_PC_US_VPC_PRIM_COUNT_STALLS_BV = 39
A7XX_PERF_PC_US_BV_STALLED_BY_UCHE_FEEDBACK = 40
A7XX_PERF_PC_US_VSD_RARB_DVIZ_FULL = 41
A7XX_PERF_PC_US_VSD_RARB_PVIZ_FULL = 42
A7XX_PERF_PC_US_VSD_RARB_TVIZ_FULL = 43
A7XX_PERF_PC_US_DP0_RARB_FULL = 44
A7XX_PERF_PC_US_DP1_RARB_FULL = 45
A7XX_PERF_PC_US_DP0_LIVE_PRIM = 46
A7XX_PERF_PC_US_DP1_LIVE_PRIM = 47
A7XX_PERF_PC_US_BV2BR_SWITCH = 48
A7XX_PERF_PC_US_BR2BV_SWITCH = 49
A7XX_PERF_PC_US_STALL_CYCLES_PC_S = 50
A7XX_PERF_PC_RESERVED_51 = 51
A7XX_PERF_PC_RESERVED_52 = 52
A7XX_PERF_PC_RESERVED_53 = 53
A7XX_PERF_PC_RESERVED_54 = 54
A7XX_PERF_PC_RESERVED_55 = 55
A7XX_PERF_PC_RESERVED_56 = 56
A7XX_PERF_PC_RESERVED_57 = 57
A7XX_PERF_PC_RESERVED_58 = 58
A7XX_PERF_PC_RESERVED_59 = 59
A7XX_PERF_PC_S_BUSY_CYCLES = 60
A7XX_PERF_PC_S_WORKING_CYCLES = 61
A7XX_PERF_PC_S_STALL_CYCLES_VFD = 62
A7XX_PERF_PC_S_STALL_CYCLES_VPC_FE = 63
A7XX_PERF_PC_S_STALL_CYCLES_TESS = 64
A7XX_PERF_PC_S_STALL_CYCLES_VFD_ONLY = 65
A7XX_PERF_PC_S_STALL_CYCLES_VPC_ONLY = 66
A7XX_PERF_PC_S_VPC_PRIMITIVES = 67
A7XX_PERF_PC_S_VERTEX_HITS = 68
A7XX_PERF_PC_S_IA_VERTICES = 69
A7XX_PERF_PC_S_IA_PRIMITIVES = 70
A7XX_PERF_PC_S_HS_INVOCATIONS = 71
A7XX_PERF_PC_S_DS_INVOCATIONS = 72
A7XX_PERF_PC_S_VS_INVOCATIONS = 73
A7XX_PERF_PC_S_GS_INVOCATIONS = 74
A7XX_PERF_PC_S_DS_PRIMITIVES = 75
A7XX_PERF_PC_S_TESS_BUSY_CYCLES = 76
A7XX_PERF_PC_S_TESS_WORKING_CYCLES = 77
A7XX_PERF_PC_S_TESS_STALL_CYCLES_PC = 78
A7XX_PERF_PC_S_TESS_STARVE_CYCLES_PC = 79
A7XX_PERF_PC_S_TESS_SETUP_ACTIVE = 80
A7XX_PERF_PC_S_TESS_PID_ACTIVE = 81
A7XX_PERF_PC_S_TESS_PRIM_GEN_ACTIVE = 82
A7XX_PERF_PC_S_TESS_FACTOR_TRANS = 83
A7XX_PERF_PC_S_TESS_PC_UV_TRANS = 84
A7XX_PERF_PC_S_TESS_PC_UV_PATCHES = 85
A7XX_PERF_PC_S_MESH_VS_WAVES = 86
a7xx_pc_perfcounter_select = ctypes.c_uint32 # enum
# values for enumeration 'a7xx_vfd_perfcounter_select'
a7xx_vfd_perfcounter_select__enumvalues = {
0: 'A7XX_PERF_VFD_NEVER_COUNT',
1: 'A7XX_PERF_VFD_BUSY_CYCLES',
2: 'A7XX_PERF_VFD_STALL_CYCLES_UCHE',
3: 'A7XX_PERF_VFD_STALL_CYCLES_VPC_ALLOC',
4: 'A7XX_PERF_VFD_STALL_CYCLES_SP_INFO',
5: 'A7XX_PERF_VFD_STALL_CYCLES_SP_ATTR',
6: 'A7XX_PERF_VFD_STARVE_CYCLES_UCHE',
7: 'A7XX_PERF_VFD_RBUFFER_FULL',
8: 'A7XX_PERF_VFD_ATTR_INFO_FIFO_FULL',
9: 'A7XX_PERF_VFD_DECODED_ATTRIBUTE_BYTES',
10: 'A7XX_PERF_VFD_NUM_ATTRIBUTES',
11: 'A7XX_PERF_VFD_UPPER_SHADER_FIBERS',
12: 'A7XX_PERF_VFD_LOWER_SHADER_FIBERS',
13: 'A7XX_PERF_VFD_MODE_0_FIBERS',
14: 'A7XX_PERF_VFD_MODE_1_FIBERS',
15: 'A7XX_PERF_VFD_MODE_2_FIBERS',
16: 'A7XX_PERF_VFD_MODE_3_FIBERS',
17: 'A7XX_PERF_VFD_MODE_4_FIBERS',
18: 'A7XX_PERF_VFD_TOTAL_VERTICES',
19: 'A7XX_PERF_VFDP_STALL_CYCLES_VFD',
20: 'A7XX_PERF_VFDP_STALL_CYCLES_VFD_INDEX',
21: 'A7XX_PERF_VFDP_STALL_CYCLES_VFD_PROG',
22: 'A7XX_PERF_VFDP_STARVE_CYCLES_PC',
23: 'A7XX_PERF_VFDP_VS_STAGE_WAVES',
24: 'A7XX_PERF_VFD_STALL_CYCLES_PRG_END_FE',
25: 'A7XX_PERF_VFD_STALL_CYCLES_CBSYNC',
}
A7XX_PERF_VFD_NEVER_COUNT = 0
A7XX_PERF_VFD_BUSY_CYCLES = 1
A7XX_PERF_VFD_STALL_CYCLES_UCHE = 2
A7XX_PERF_VFD_STALL_CYCLES_VPC_ALLOC = 3
A7XX_PERF_VFD_STALL_CYCLES_SP_INFO = 4
A7XX_PERF_VFD_STALL_CYCLES_SP_ATTR = 5
A7XX_PERF_VFD_STARVE_CYCLES_UCHE = 6
A7XX_PERF_VFD_RBUFFER_FULL = 7
A7XX_PERF_VFD_ATTR_INFO_FIFO_FULL = 8
A7XX_PERF_VFD_DECODED_ATTRIBUTE_BYTES = 9
A7XX_PERF_VFD_NUM_ATTRIBUTES = 10
A7XX_PERF_VFD_UPPER_SHADER_FIBERS = 11
A7XX_PERF_VFD_LOWER_SHADER_FIBERS = 12
A7XX_PERF_VFD_MODE_0_FIBERS = 13
A7XX_PERF_VFD_MODE_1_FIBERS = 14
A7XX_PERF_VFD_MODE_2_FIBERS = 15
A7XX_PERF_VFD_MODE_3_FIBERS = 16
A7XX_PERF_VFD_MODE_4_FIBERS = 17
A7XX_PERF_VFD_TOTAL_VERTICES = 18
A7XX_PERF_VFDP_STALL_CYCLES_VFD = 19
A7XX_PERF_VFDP_STALL_CYCLES_VFD_INDEX = 20
A7XX_PERF_VFDP_STALL_CYCLES_VFD_PROG = 21
A7XX_PERF_VFDP_STARVE_CYCLES_PC = 22
A7XX_PERF_VFDP_VS_STAGE_WAVES = 23
A7XX_PERF_VFD_STALL_CYCLES_PRG_END_FE = 24
A7XX_PERF_VFD_STALL_CYCLES_CBSYNC = 25
a7xx_vfd_perfcounter_select = ctypes.c_uint32 # enum
# values for enumeration 'a7xx_hlsq_perfcounter_select'
a7xx_hlsq_perfcounter_select__enumvalues = {
0: 'A7XX_PERF_HLSQ_NEVER_COUNT',
1: 'A7XX_PERF_HLSQ_BUSY_CYCLES',
2: 'A7XX_PERF_HLSQ_STALL_CYCLES_SP_STATE',
3: 'A7XX_PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE',
4: 'A7XX_PERF_HLSQ_UCHE_LATENCY_CYCLES',
5: 'A7XX_PERF_HLSQ_UCHE_LATENCY_COUNT',
6: 'A7XX_PERF_HLSQ_STALL_CYCLES_UCHE',
7: 'A7XX_PERF_HLSQ_RESERVED_7',
8: 'A7XX_PERF_HLSQ_RESERVED_8',
9: 'A7XX_PERF_HLSQ_RESERVED_9',
10: 'A7XX_PERF_HLSQ_COMPUTE_DRAWCALLS',
11: 'A7XX_PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING',
12: 'A7XX_PERF_HLSQ_DUAL_FS_PROG_ACTIVE',
13: 'A7XX_PERF_HLSQ_DUAL_VS_PROG_ACTIVE',
14: 'A7XX_PERF_HLSQ_FS_BATCH_COUNT_ZERO',
15: 'A7XX_PERF_HLSQ_VS_BATCH_COUNT_ZERO',
16: 'A7XX_PERF_HLSQ_WAVE_PENDING_NO_QUAD',
17: 'A7XX_PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE',
18: 'A7XX_PERF_HLSQ_STALL_CYCLES_VPC_BE',
19: 'A7XX_PERF_HLSQ_RESERVED_19',
20: 'A7XX_PERF_HLSQ_RESERVED_20',
21: 'A7XX_PERF_HLSQ_VSBR_STALL_CYCLES',
22: 'A7XX_PERF_HLSQ_FS_STALL_CYCLES',
23: 'A7XX_PERF_HLSQ_LPAC_STALL_CYCLES',
24: 'A7XX_PERF_HLSQ_BV_STALL_CYCLES',
25: 'A7XX_PERF_HLSQ_VSBR_DEREF_CYCLES',
26: 'A7XX_PERF_HLSQ_FS_DEREF_CYCLES',
27: 'A7XX_PERF_HLSQ_LPAC_DEREF_CYCLES',
28: 'A7XX_PERF_HLSQ_BV_DEREF_CYCLES',
29: 'A7XX_PERF_HLSQ_VSBR_S2W_CYCLES',
30: 'A7XX_PERF_HLSQ_FS_S2W_CYCLES',
31: 'A7XX_PERF_HLSQ_LPAC_S2W_CYCLES',
32: 'A7XX_PERF_HLSQ_BV_S2W_CYCLES',
33: 'A7XX_PERF_HLSQ_VSBR_WAIT_FS_S2W',
34: 'A7XX_PERF_HLSQ_FS_WAIT_VS_S2W',
35: 'A7XX_PERF_HLSQ_LPAC_WAIT_VS_S2W',
36: 'A7XX_PERF_HLSQ_BV_WAIT_FS_S2W',
37: 'A7XX_PERF_HLSQ_RESERVED_37',
38: 'A7XX_PERF_HLSQ_FS_WAIT_SAME_VS_S2W',
39: 'A7XX_PERF_HLSQ_FS_STARVING_SP',
40: 'A7XX_PERF_HLSQ_VS_DATA_WAIT_PROGRAMMING',
41: 'A7XX_PERF_HLSQ_BV_DATA_WAIT_PROGRAMMING',
42: 'A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXTS_VS',
43: 'A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_VS',
44: 'A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXTS_FS',
45: 'A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_FS',
46: 'A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXTS_BV',
47: 'A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_BV',
48: 'A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXTS_LPAC',
49: 'A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_LPAC',
50: 'A7XX_PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_VS',
51: 'A7XX_PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_FS',
52: 'A7XX_PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_BV',
53: 'A7XX_PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_LPAC',
54: 'A7XX_PERF_HLSQ_SPTROC_STCHE_MISS_INC_VS',
55: 'A7XX_PERF_HLSQ_SPTROC_STCHE_MISS_INC_FS',
56: 'A7XX_PERF_HLSQ_SPTROC_STCHE_MISS_INC_BV',
57: 'A7XX_PERF_HLSQ_SPTROC_STCHE_MISS_INC_LPAC',
58: 'A7XX_PERF_HLSQ_VSBR_S2W_CYCLES_SP',
59: 'A7XX_PERF_HLSQ_FS_S2W_CYCLES_SP',
60: 'A7XX_PERF_HLSQ_LPAC_S2W_CYCLES_SP',
61: 'A7XX_PERF_HLSQ_BV_S2W_CYCLES_SP',
62: 'A7XX_PERF_HLSQ_L2STC_REQ_HLSQ',
63: 'A7XX_PERF_HLSQ_L2STC_REQ_HLSQ_HIT',
64: 'A7XX_PERF_HLSQ_L2STC_REQ_SP',
65: 'A7XX_PERF_HLSQ_L2STC_REQ_SP_HIT',
66: 'A7XX_PERF_HLSQ_L2STC_REQ_INS_HLSQ',
67: 'A7XX_PERF_HLSQ_L2STC_REQ_INS_HLSQ_HIT',
68: 'A7XX_PERF_HLSQ_L2STC_REQ_INS_SP',
69: 'A7XX_PERF_HLSQ_L2STC_REQ_INS_SP_HIT',
70: 'A7XX_PERF_HLSQ_L2STC_REQ_UCHE',
71: 'A7XX_PERF_HLSQ_L2STC_LATENCY_CYCLES',
72: 'A7XX_PERF_HLSQ_L2STC_LATENCY_COUNT',
73: 'A7XX_PERF_HLSQ_L2STC_STALL_SP_MISS_REQ',
74: 'A7XX_PERF_HLSQ_L2STC_BANK0_REPLACEMENT',
75: 'A7XX_PERF_HLSQ_L2STC_BANK1_REPLACEMENT',
76: 'A7XX_PERF_HLSQ_L2STC_BANK2_REPLACEMENT',
77: 'A7XX_PERF_HLSQ_L2STC_BANK3_REPLACEMENT',
78: 'A7XX_PERF_HLSQ_S2W_STALL_BY_MISS_RETURN',
79: 'A7XX_PERF_HLSQ_MISS_RETURN_STALL_BY_S2W',
80: 'A7XX_PERF_HLSQ_STPROC_L0_STALL_INS_RD',
81: 'A7XX_PERF_HLSQ_STPROC_L0_INS_MISS',
82: 'A7XX_PERF_HLSQ_STPROC_L0_INS_HIT',
83: 'A7XX_PERF_HLSQ_STPROC_L0_INS_LATENCY_COUNT',
84: 'A7XX_PERF_HLSQ_STPROC_L0_INS_LATENCY_CYCLE',
85: 'A7XX_PERF_HLSQ_STPROC_DPS_RUN_COUNT',
86: 'A7XX_PERF_HLSQ_STPROC_DPS_RUN_CYCLE',
87: 'A7XX_PERF_HLSQ_VSDP_BR_QUERY_REQ',
88: 'A7XX_PERF_HLSQ_VSDP_BV_QUERY_REQ',
89: 'A7XX_PERF_HLSQ_VSDP_BR_QUERY_REQ_WHEN_BV_PENDING',
90: 'A7XX_PERF_HLSQ_VSDP_BR_QUERY_BUSY',
91: 'A7XX_PERF_HLSQ_VSDP_BV_QUERY_BUSY',
92: 'A7XX_PERF_HLSQ_VSDP_BR_QUERY_FAIL',
93: 'A7XX_PERF_HLSQ_VSDP_BV_QUERY_FAIL',
94: 'A7XX_PERF_HLSQ_VS_CTXT_BUF_FULL_BLOCK_CPI',
95: 'A7XX_PERF_HLSQ_FS_CTXT_BUF_FULL_BLOCK_CPI',
96: 'A7XX_PERF_HLSQ_BV_CTXT_BUF_FULL_BLOCK_CPI',
97: 'A7XX_PERF_HLSQ_VS_CONST_BUF_FULL_BLOCK_CPI',
98: 'A7XX_PERF_HLSQ_FS_CONST_BUF_FULL_BLOCK_CPI',
99: 'A7XX_PERF_HLSQ_BV_CONST_BUF_FULL_BLOCK_CPI',
100: 'A7XX_PERF_HLSQ_VS_INS_BUF_FULL_BLOCK_CPI',
101: 'A7XX_PERF_HLSQ_FS_INS_BUF_FULL_BLOCK_CPI',
102: 'A7XX_PERF_HLSQ_BV_INS_BUF_FULL_BLOCK_CPI',
103: 'A7XX_PERF_HLSQ_VS_DES_BUF_FULL_BLOCK_CPI',
104: 'A7XX_PERF_HLSQ_FS_DES_BUF_FULL_BLOCK_CPI',
105: 'A7XX_PERF_HLSQ_BV_DES_BUF_FULL_BLOCK_CPI',
106: 'A7XX_PERF_HLSQ_PRIMITIVE_COUNT',
107: 'A7XX_PERF_HLSQ_LPAC2BV_SWITCH_CNT',
108: 'A7XX_PERF_HLSQ_BV2LPAC_SWITCH_CNT',
109: 'A7XX_PERF_HLSQ_LPAC2BV_SWITCH_CYC',
110: 'A7XX_PERF_HLSQ_BV2LPAC_SWITCH_CYC',
111: 'A7XX_PERF_HLSQ_VSDP_BV2BR_SWITCH_CYC',
}
A7XX_PERF_HLSQ_NEVER_COUNT = 0
A7XX_PERF_HLSQ_BUSY_CYCLES = 1
A7XX_PERF_HLSQ_STALL_CYCLES_SP_STATE = 2
A7XX_PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE = 3
A7XX_PERF_HLSQ_UCHE_LATENCY_CYCLES = 4
A7XX_PERF_HLSQ_UCHE_LATENCY_COUNT = 5
A7XX_PERF_HLSQ_STALL_CYCLES_UCHE = 6
A7XX_PERF_HLSQ_RESERVED_7 = 7
A7XX_PERF_HLSQ_RESERVED_8 = 8
A7XX_PERF_HLSQ_RESERVED_9 = 9
A7XX_PERF_HLSQ_COMPUTE_DRAWCALLS = 10
A7XX_PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING = 11
A7XX_PERF_HLSQ_DUAL_FS_PROG_ACTIVE = 12
A7XX_PERF_HLSQ_DUAL_VS_PROG_ACTIVE = 13
A7XX_PERF_HLSQ_FS_BATCH_COUNT_ZERO = 14
A7XX_PERF_HLSQ_VS_BATCH_COUNT_ZERO = 15
A7XX_PERF_HLSQ_WAVE_PENDING_NO_QUAD = 16
A7XX_PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE = 17
A7XX_PERF_HLSQ_STALL_CYCLES_VPC_BE = 18
A7XX_PERF_HLSQ_RESERVED_19 = 19
A7XX_PERF_HLSQ_RESERVED_20 = 20
A7XX_PERF_HLSQ_VSBR_STALL_CYCLES = 21
A7XX_PERF_HLSQ_FS_STALL_CYCLES = 22
A7XX_PERF_HLSQ_LPAC_STALL_CYCLES = 23
A7XX_PERF_HLSQ_BV_STALL_CYCLES = 24
A7XX_PERF_HLSQ_VSBR_DEREF_CYCLES = 25
A7XX_PERF_HLSQ_FS_DEREF_CYCLES = 26
A7XX_PERF_HLSQ_LPAC_DEREF_CYCLES = 27
A7XX_PERF_HLSQ_BV_DEREF_CYCLES = 28
A7XX_PERF_HLSQ_VSBR_S2W_CYCLES = 29
A7XX_PERF_HLSQ_FS_S2W_CYCLES = 30
A7XX_PERF_HLSQ_LPAC_S2W_CYCLES = 31
A7XX_PERF_HLSQ_BV_S2W_CYCLES = 32
A7XX_PERF_HLSQ_VSBR_WAIT_FS_S2W = 33
A7XX_PERF_HLSQ_FS_WAIT_VS_S2W = 34
A7XX_PERF_HLSQ_LPAC_WAIT_VS_S2W = 35
A7XX_PERF_HLSQ_BV_WAIT_FS_S2W = 36
A7XX_PERF_HLSQ_RESERVED_37 = 37
A7XX_PERF_HLSQ_FS_WAIT_SAME_VS_S2W = 38
A7XX_PERF_HLSQ_FS_STARVING_SP = 39
A7XX_PERF_HLSQ_VS_DATA_WAIT_PROGRAMMING = 40
A7XX_PERF_HLSQ_BV_DATA_WAIT_PROGRAMMING = 41
A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXTS_VS = 42
A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_VS = 43
A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXTS_FS = 44
A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_FS = 45
A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXTS_BV = 46
A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_BV = 47
A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXTS_LPAC = 48
A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_LPAC = 49
A7XX_PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_VS = 50
A7XX_PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_FS = 51
A7XX_PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_BV = 52
A7XX_PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_LPAC = 53
A7XX_PERF_HLSQ_SPTROC_STCHE_MISS_INC_VS = 54
A7XX_PERF_HLSQ_SPTROC_STCHE_MISS_INC_FS = 55
A7XX_PERF_HLSQ_SPTROC_STCHE_MISS_INC_BV = 56
A7XX_PERF_HLSQ_SPTROC_STCHE_MISS_INC_LPAC = 57
A7XX_PERF_HLSQ_VSBR_S2W_CYCLES_SP = 58
A7XX_PERF_HLSQ_FS_S2W_CYCLES_SP = 59
A7XX_PERF_HLSQ_LPAC_S2W_CYCLES_SP = 60
A7XX_PERF_HLSQ_BV_S2W_CYCLES_SP = 61
A7XX_PERF_HLSQ_L2STC_REQ_HLSQ = 62
A7XX_PERF_HLSQ_L2STC_REQ_HLSQ_HIT = 63
A7XX_PERF_HLSQ_L2STC_REQ_SP = 64
A7XX_PERF_HLSQ_L2STC_REQ_SP_HIT = 65
A7XX_PERF_HLSQ_L2STC_REQ_INS_HLSQ = 66
A7XX_PERF_HLSQ_L2STC_REQ_INS_HLSQ_HIT = 67
A7XX_PERF_HLSQ_L2STC_REQ_INS_SP = 68
A7XX_PERF_HLSQ_L2STC_REQ_INS_SP_HIT = 69
A7XX_PERF_HLSQ_L2STC_REQ_UCHE = 70
A7XX_PERF_HLSQ_L2STC_LATENCY_CYCLES = 71
A7XX_PERF_HLSQ_L2STC_LATENCY_COUNT = 72
A7XX_PERF_HLSQ_L2STC_STALL_SP_MISS_REQ = 73
A7XX_PERF_HLSQ_L2STC_BANK0_REPLACEMENT = 74
A7XX_PERF_HLSQ_L2STC_BANK1_REPLACEMENT = 75
A7XX_PERF_HLSQ_L2STC_BANK2_REPLACEMENT = 76
A7XX_PERF_HLSQ_L2STC_BANK3_REPLACEMENT = 77
A7XX_PERF_HLSQ_S2W_STALL_BY_MISS_RETURN = 78
A7XX_PERF_HLSQ_MISS_RETURN_STALL_BY_S2W = 79
A7XX_PERF_HLSQ_STPROC_L0_STALL_INS_RD = 80
A7XX_PERF_HLSQ_STPROC_L0_INS_MISS = 81
A7XX_PERF_HLSQ_STPROC_L0_INS_HIT = 82
A7XX_PERF_HLSQ_STPROC_L0_INS_LATENCY_COUNT = 83
A7XX_PERF_HLSQ_STPROC_L0_INS_LATENCY_CYCLE = 84
A7XX_PERF_HLSQ_STPROC_DPS_RUN_COUNT = 85
A7XX_PERF_HLSQ_STPROC_DPS_RUN_CYCLE = 86
A7XX_PERF_HLSQ_VSDP_BR_QUERY_REQ = 87
A7XX_PERF_HLSQ_VSDP_BV_QUERY_REQ = 88
A7XX_PERF_HLSQ_VSDP_BR_QUERY_REQ_WHEN_BV_PENDING = 89
A7XX_PERF_HLSQ_VSDP_BR_QUERY_BUSY = 90
A7XX_PERF_HLSQ_VSDP_BV_QUERY_BUSY = 91
A7XX_PERF_HLSQ_VSDP_BR_QUERY_FAIL = 92
A7XX_PERF_HLSQ_VSDP_BV_QUERY_FAIL = 93
A7XX_PERF_HLSQ_VS_CTXT_BUF_FULL_BLOCK_CPI = 94
A7XX_PERF_HLSQ_FS_CTXT_BUF_FULL_BLOCK_CPI = 95
A7XX_PERF_HLSQ_BV_CTXT_BUF_FULL_BLOCK_CPI = 96
A7XX_PERF_HLSQ_VS_CONST_BUF_FULL_BLOCK_CPI = 97
A7XX_PERF_HLSQ_FS_CONST_BUF_FULL_BLOCK_CPI = 98
A7XX_PERF_HLSQ_BV_CONST_BUF_FULL_BLOCK_CPI = 99
A7XX_PERF_HLSQ_VS_INS_BUF_FULL_BLOCK_CPI = 100
A7XX_PERF_HLSQ_FS_INS_BUF_FULL_BLOCK_CPI = 101
A7XX_PERF_HLSQ_BV_INS_BUF_FULL_BLOCK_CPI = 102
A7XX_PERF_HLSQ_VS_DES_BUF_FULL_BLOCK_CPI = 103
A7XX_PERF_HLSQ_FS_DES_BUF_FULL_BLOCK_CPI = 104
A7XX_PERF_HLSQ_BV_DES_BUF_FULL_BLOCK_CPI = 105
A7XX_PERF_HLSQ_PRIMITIVE_COUNT = 106
A7XX_PERF_HLSQ_LPAC2BV_SWITCH_CNT = 107
A7XX_PERF_HLSQ_BV2LPAC_SWITCH_CNT = 108
A7XX_PERF_HLSQ_LPAC2BV_SWITCH_CYC = 109
A7XX_PERF_HLSQ_BV2LPAC_SWITCH_CYC = 110
A7XX_PERF_HLSQ_VSDP_BV2BR_SWITCH_CYC = 111
a7xx_hlsq_perfcounter_select = ctypes.c_uint32 # enum
# values for enumeration 'a7xx_vpc_perfcounter_select'
a7xx_vpc_perfcounter_select__enumvalues = {
0: 'A7XX_PERF_VPC_NEVER_COUNT',
1: 'A7XX_PERF_VPC_FE_BUSY_CYCLES',
2: 'A7XX_PERF_VPC_FE_WORKING_CYCLES',
3: 'A7XX_PERF_VPC_FE_STALL_CYCLES_VFD_WACK',
4: 'A7XX_PERF_VPC_FE_STARVE_CYCLES_SP',
5: 'A7XX_PERF_VPC_FE_PC_PRIMITIVES',
6: 'A7XX_PERF_VPC_FE_SP_COMPONENTS',
7: 'A7XX_PERF_VPC_FE_STALL_CYCLES_VPCRAM_POS',
8: 'A7XX_PERF_VPC_FE_VS_BUSY_CYCLES',
9: 'A7XX_PERF_VPC_FE_VS_WORKING_CYCLES',
10: 'A7XX_PERF_VPC_FE_NUM_VPCRAM_READ_POS',
11: 'A7XX_PERF_VPC_FE_WIT_FULL_CYCLES',
12: 'A7XX_PERF_VPC_FE_VPCRAM_FULL_CYCLES',
13: 'A7XX_PERF_VPC_FE_NUM_VPCRAM_WRITE',
14: 'A7XX_PERF_VPC_FE_STALL_CYCLES_TSE_FE',
15: 'A7XX_PERF_VPC_FE_STALL_CYCLES_VPC_US',
16: 'A7XX_PERF_VPC_FE_TSE_FE_PRIMITIVES',
17: 'A7XX_PERF_VPC_FE_GS_PRIMITIVES',
18: 'A7XX_PERF_VPC_FE_TSE_FE_TRANSACTIONS',
19: 'A7XX_PERF_VPC_FE_STALL_CYCLES_CCU',
20: 'A7XX_PERF_VPC_FE_NUM_WM_HIT',
21: 'A7XX_PERF_VPC_FE_STALL_DQ_WACK',
22: 'A7XX_PERF_VPC_FE_STALL_CYCLES_PRG_END_FE',
23: 'A7XX_PERF_VPC_FE_STALL_CYCLES_PRG_END_VPCVS',
24: 'A7XX_PERF_VPC_FE_POSRAM_FULL_CYCLES',
25: 'A7XX_PERF_VPC_FE_GMEM_NOP_FULL_CYCLES',
26: 'A7XX_PERF_VPC_FE_GMEM_POS_FULL_CYCLES',
27: 'A7XX_PERF_VPC_FE_BOTTLENECK',
28: 'A7XX_PERF_VPC_US_BUSY_CYCLES',
29: 'A7XX_PERF_VPC_US_WORKING_CYCLES',
30: 'A7XX_PERF_VPC_US_STARVE_CYCLES_TSE_FE',
31: 'A7XX_PERF_VPC_US_PTUS_FULL',
32: 'A7XX_PERF_VPC_US_COMP_INVIS_PRIM_COUNT',
33: 'A7XX_PERF_VPC_US_STALL_CYCLES_VSC',
34: 'A7XX_PERF_VPC_US_STALL_CYCLES_VPC_BE',
35: 'A7XX_PERF_VPC_US_STALL_CYCLES_UCHE',
36: 'A7XX_PERF_VPC_US_STREAMOUT_TRANSACTION',
37: 'A7XX_PERF_VPC_US_NUM_GMEM_READ_SO',
38: 'A7XX_PERF_VPC_US_STARVE_CYCLES_UCHE_RD',
39: 'A7XX_PERF_VPC_US_STALL_CYCLES_PRG_END_VPCUS',
40: 'A7XX_PERF_VPC_US_STARVE_CYCLES_REORDER',
41: 'A7XX_PERF_VPC_US_BOTTLENECK',
42: 'A7XX_PERF_VPC_RESERVED_42',
43: 'A7XX_PERF_VPC_RESERVED_43',
44: 'A7XX_PERF_VPC_RESERVED_44',
45: 'A7XX_PERF_VPC_BE_BUSY_CYCLES',
46: 'A7XX_PERF_VPC_BE_WORKING_CYCLES',
47: 'A7XX_PERF_VPC_BE_STALL_CYCLES_TSE_BE',
48: 'A7XX_PERF_VPC_BE_TSE_BE_PRIMITIVES',
49: 'A7XX_PERF_VPC_BE_TSE_BE_TRANSACTIONS',
50: 'A7XX_PERF_VPC_BE_STARVE_CYCLES_LRZ',
51: 'A7XX_PERF_VPC_BE_LRZ_ASSIGN_PRIMITIVES',
52: 'A7XX_PERF_VPC_BE_RB_VISIBLE_PRIMITIVES',
53: 'A7XX_PERF_VPC_BE_STARVE_CYCLES_RB',
54: 'A7XX_PERF_VPC_BE_STALL_CYCLES_HLSQ_PRIM_ALLOC',
55: 'A7XX_PERF_VPC_BE_STALL_CYCLES_SP_LM',
56: 'A7XX_PERF_VPC_BE_NUM_PA_REQ',
57: 'A7XX_PERF_VPC_BE_NUM_LM_REQ_HIT',
58: 'A7XX_PERF_VPC_BE_NUM_ATTR_REQ_LM',
59: 'A7XX_PERF_VPC_BE_LM_TRANSACTION',
60: 'A7XX_PERF_VPC_BE_PS_BUSY_CYCLES',
61: 'A7XX_PERF_VPC_BE_PS_WORKING_CYCLES',
62: 'A7XX_PERF_VPC_BE_STALL_CYCLES_CCHE',
63: 'A7XX_PERF_VPC_BE_STARVE_CYCLES_CCHE',
64: 'A7XX_PERF_VPC_BE_LM_FULL_WAIT_FOR_INTP_END',
65: 'A7XX_PERF_VPC_BE_CCHE_REQBUF_FULL',
66: 'A7XX_PERF_VPC_BE_CCHE_NUM_POS_REQ',
67: 'A7XX_PERF_VPC_BE_STALL_CYCLES_LM_ACK',
68: 'A7XX_PERF_VPC_BE_STALL_CYCLES_PRG_END_VPCPS',
69: 'A7XX_PERF_VPC_BE_POS_OVERFETCH_ATTR',
70: 'A7XX_PERF_VPC_BE_BOTTLENECK',
}
A7XX_PERF_VPC_NEVER_COUNT = 0
A7XX_PERF_VPC_FE_BUSY_CYCLES = 1
A7XX_PERF_VPC_FE_WORKING_CYCLES = 2
A7XX_PERF_VPC_FE_STALL_CYCLES_VFD_WACK = 3
A7XX_PERF_VPC_FE_STARVE_CYCLES_SP = 4
A7XX_PERF_VPC_FE_PC_PRIMITIVES = 5
A7XX_PERF_VPC_FE_SP_COMPONENTS = 6
A7XX_PERF_VPC_FE_STALL_CYCLES_VPCRAM_POS = 7
A7XX_PERF_VPC_FE_VS_BUSY_CYCLES = 8
A7XX_PERF_VPC_FE_VS_WORKING_CYCLES = 9
A7XX_PERF_VPC_FE_NUM_VPCRAM_READ_POS = 10
A7XX_PERF_VPC_FE_WIT_FULL_CYCLES = 11
A7XX_PERF_VPC_FE_VPCRAM_FULL_CYCLES = 12
A7XX_PERF_VPC_FE_NUM_VPCRAM_WRITE = 13
A7XX_PERF_VPC_FE_STALL_CYCLES_TSE_FE = 14
A7XX_PERF_VPC_FE_STALL_CYCLES_VPC_US = 15
A7XX_PERF_VPC_FE_TSE_FE_PRIMITIVES = 16
A7XX_PERF_VPC_FE_GS_PRIMITIVES = 17
A7XX_PERF_VPC_FE_TSE_FE_TRANSACTIONS = 18
A7XX_PERF_VPC_FE_STALL_CYCLES_CCU = 19
A7XX_PERF_VPC_FE_NUM_WM_HIT = 20
A7XX_PERF_VPC_FE_STALL_DQ_WACK = 21
A7XX_PERF_VPC_FE_STALL_CYCLES_PRG_END_FE = 22
A7XX_PERF_VPC_FE_STALL_CYCLES_PRG_END_VPCVS = 23
A7XX_PERF_VPC_FE_POSRAM_FULL_CYCLES = 24
A7XX_PERF_VPC_FE_GMEM_NOP_FULL_CYCLES = 25
A7XX_PERF_VPC_FE_GMEM_POS_FULL_CYCLES = 26
A7XX_PERF_VPC_FE_BOTTLENECK = 27
A7XX_PERF_VPC_US_BUSY_CYCLES = 28
A7XX_PERF_VPC_US_WORKING_CYCLES = 29
A7XX_PERF_VPC_US_STARVE_CYCLES_TSE_FE = 30
A7XX_PERF_VPC_US_PTUS_FULL = 31
A7XX_PERF_VPC_US_COMP_INVIS_PRIM_COUNT = 32
A7XX_PERF_VPC_US_STALL_CYCLES_VSC = 33
A7XX_PERF_VPC_US_STALL_CYCLES_VPC_BE = 34
A7XX_PERF_VPC_US_STALL_CYCLES_UCHE = 35
A7XX_PERF_VPC_US_STREAMOUT_TRANSACTION = 36
A7XX_PERF_VPC_US_NUM_GMEM_READ_SO = 37
A7XX_PERF_VPC_US_STARVE_CYCLES_UCHE_RD = 38
A7XX_PERF_VPC_US_STALL_CYCLES_PRG_END_VPCUS = 39
A7XX_PERF_VPC_US_STARVE_CYCLES_REORDER = 40
A7XX_PERF_VPC_US_BOTTLENECK = 41
A7XX_PERF_VPC_RESERVED_42 = 42
A7XX_PERF_VPC_RESERVED_43 = 43
A7XX_PERF_VPC_RESERVED_44 = 44
A7XX_PERF_VPC_BE_BUSY_CYCLES = 45
A7XX_PERF_VPC_BE_WORKING_CYCLES = 46
A7XX_PERF_VPC_BE_STALL_CYCLES_TSE_BE = 47
A7XX_PERF_VPC_BE_TSE_BE_PRIMITIVES = 48
A7XX_PERF_VPC_BE_TSE_BE_TRANSACTIONS = 49
A7XX_PERF_VPC_BE_STARVE_CYCLES_LRZ = 50
A7XX_PERF_VPC_BE_LRZ_ASSIGN_PRIMITIVES = 51
A7XX_PERF_VPC_BE_RB_VISIBLE_PRIMITIVES = 52
A7XX_PERF_VPC_BE_STARVE_CYCLES_RB = 53
A7XX_PERF_VPC_BE_STALL_CYCLES_HLSQ_PRIM_ALLOC = 54
A7XX_PERF_VPC_BE_STALL_CYCLES_SP_LM = 55
A7XX_PERF_VPC_BE_NUM_PA_REQ = 56
A7XX_PERF_VPC_BE_NUM_LM_REQ_HIT = 57
A7XX_PERF_VPC_BE_NUM_ATTR_REQ_LM = 58
A7XX_PERF_VPC_BE_LM_TRANSACTION = 59
A7XX_PERF_VPC_BE_PS_BUSY_CYCLES = 60
A7XX_PERF_VPC_BE_PS_WORKING_CYCLES = 61
A7XX_PERF_VPC_BE_STALL_CYCLES_CCHE = 62
A7XX_PERF_VPC_BE_STARVE_CYCLES_CCHE = 63
A7XX_PERF_VPC_BE_LM_FULL_WAIT_FOR_INTP_END = 64
A7XX_PERF_VPC_BE_CCHE_REQBUF_FULL = 65
A7XX_PERF_VPC_BE_CCHE_NUM_POS_REQ = 66
A7XX_PERF_VPC_BE_STALL_CYCLES_LM_ACK = 67
A7XX_PERF_VPC_BE_STALL_CYCLES_PRG_END_VPCPS = 68
A7XX_PERF_VPC_BE_POS_OVERFETCH_ATTR = 69
A7XX_PERF_VPC_BE_BOTTLENECK = 70
a7xx_vpc_perfcounter_select = ctypes.c_uint32 # enum
# values for enumeration 'a7xx_tse_perfcounter_select'
a7xx_tse_perfcounter_select__enumvalues = {
0: 'A7XX_PERF_TSE_NEVER_COUNT',
1: 'A7XX_PERF_TSE_BE_BUSY_CYCLES',
2: 'A7XX_PERF_TSE_BE_CLIPPING_CYCLES',
3: 'A7XX_PERF_TSE_BE_STALL_CYCLES_RAS',
4: 'A7XX_PERF_TSE_BE_STALL_CYCLES_LRZ_BARYPLANE',
5: 'A7XX_PERF_TSE_BE_STALL_CYCLES_LRZ_ZPLANE',
6: 'A7XX_PERF_TSE_BE_STARVE_CYCLES_PC',
7: 'A7XX_PERF_TSE_BE_INPUT_PRIM',
8: 'A7XX_PERF_TSE_BE_INPUT_NULL_PRIM',
9: 'A7XX_PERF_TSE_BE_TRIVAL_REJ_PRIM',
10: 'A7XX_PERF_TSE_BE_CLIPPED_PRIM',
11: 'A7XX_PERF_TSE_BE_ZERO_AREA_PRIM',
12: 'A7XX_PERF_TSE_BE_FACENESS_CULLED_PRIM',
13: 'A7XX_PERF_TSE_BE_ZERO_PIXEL_PRIM',
14: 'A7XX_PERF_TSE_BE_OUTPUT_NULL_PRIM',
15: 'A7XX_PERF_TSE_BE_OUTPUT_VISIBLE_PRIM',
16: 'A7XX_PERF_TSE_BE_CINVOCATION',
17: 'A7XX_PERF_TSE_BE_CPRIMITIVES',
18: 'A7XX_PERF_TSE_BE_2D_INPUT_PRIM',
19: 'A7XX_PERF_TSE_BE_2D_ALIVE_CYCLES',
20: 'A7XX_PERF_TSE_BE_CLIP_PLANES',
21: 'A7XX_PERF_TSE_BE_EMPTY_BBOX_KILLED_PRIM',
22: 'A7XX_PERF_TSE_BE_ST1_VP_PARAMS_CACHE_MISS',
23: 'A7XX_PERF_TSE_BE_ST2_VPORT_VP_PARAMS_CACHE_MISS',
24: 'A7XX_PERF_TSE_BE_ST2_SCISSOR_VP_PARAMS_CACHE_MISS',
25: 'A7XX_PERF_TSE_BE_ILLEGAL_BOUNDING_BOX_PRIM',
26: 'A7XX_PERF_TSE_BE_VP_OUT_IS_NAN',
27: 'A7XX_PERF_TSE_BE_EXCLUDED_PRIM',
28: 'A7XX_PERF_TSE_BE_EARLY_CULL_CLIPPED_PRIM',
29: 'A7XX_PERF_TSE_BE_BR_STALLS_DUETO_BV_CLIP',
30: 'A7XX_PERF_TSE_BE_BR_STALLS_DUETO_BV_POLY',
31: 'A7XX_PERF_TSE_BE_BV_STALLS_DUETO_BR_CLIP',
32: 'A7XX_PERF_TSE_BE_BV_STALLS_DUETO_BR_POLY',
33: 'A7XX_PERF_TSE_BE_BV_STALLS_DUETO_BR',
34: 'A7XX_PERF_TSE_FE_BUSY_CYCLES',
35: 'A7XX_PERF_TSE_FE_STALL_CYCLES_VPC_US',
36: 'A7XX_PERF_TSE_FE_STARVE_CYCLES_PC',
37: 'A7XX_PERF_TSE_FE_INPUT_PRIM',
38: 'A7XX_PERF_TSE_FE_INPUT_NULL_PRIM',
39: 'A7XX_PERF_TSE_FE_TRIVAL_REJ_PRIM',
40: 'A7XX_PERF_TSE_FE_ZERO_AREA_PRIM',
41: 'A7XX_PERF_TSE_FE_FACENESS_CULLED_PRIM',
42: 'A7XX_PERF_TSE_FE_ZERO_PIXEL_PRIM',
43: 'A7XX_PERF_TSE_FE_OUTPUT_NULL_PRIM',
44: 'A7XX_PERF_TSE_FE_OUTPUT_VISIBLE_PRIM',
45: 'A7XX_PERF_TSE_FE_CINVOCATION',
46: 'A7XX_PERF_TSE_FE_CPRIMITIVES',
47: 'A7XX_PERF_TSE_FE_CLIP_PLANES',
48: 'A7XX_PERF_TSE_FE_EMPTY_BBOX_KILLED_PRIM',
49: 'A7XX_PERF_TSE_FE_ST1_VP_PARAMS_CACHE_MISS',
50: 'A7XX_PERF_TSE_FE_ST2_VPORT_VP_PARAMS_CACHE_MISS',
51: 'A7XX_PERF_TSE_FE_ST2_SCISSOR_VP_PARAMS_CACHE_MISS',
52: 'A7XX_PERF_TSE_FE_ILLEGAL_BOUNDING_BOX_PRIM',
53: 'A7XX_PERF_TSE_FE_VP_OUT_IS_NAN',
54: 'A7XX_PERF_TSE_FE_EXCLUDED_PRIM',
55: 'A7XX_PERF_TSE_FE_EARLY_CULL_CLIPPED_PRIM',
56: 'A7XX_PERF_TSE_FE_BR_STALLS_DUETO_BV_CLIP',
57: 'A7XX_PERF_TSE_FE_BR_STALLS_DUETO_BV_POLY',
58: 'A7XX_PERF_TSE_FE_BV_STALLS_DUETO_BR_CLIP',
59: 'A7XX_PERF_TSE_FE_BV_STALLS_DUETO_BR_POLY',
60: 'A7XX_PERF_TSE_FE_BV_STALLS_DUETO_BR',
61: 'A7XX_PERF_TSE_BE_STALL_CYCLES_LRZ_PRIM',
}
A7XX_PERF_TSE_NEVER_COUNT = 0
A7XX_PERF_TSE_BE_BUSY_CYCLES = 1
A7XX_PERF_TSE_BE_CLIPPING_CYCLES = 2
A7XX_PERF_TSE_BE_STALL_CYCLES_RAS = 3
A7XX_PERF_TSE_BE_STALL_CYCLES_LRZ_BARYPLANE = 4
A7XX_PERF_TSE_BE_STALL_CYCLES_LRZ_ZPLANE = 5
A7XX_PERF_TSE_BE_STARVE_CYCLES_PC = 6
A7XX_PERF_TSE_BE_INPUT_PRIM = 7
A7XX_PERF_TSE_BE_INPUT_NULL_PRIM = 8
A7XX_PERF_TSE_BE_TRIVAL_REJ_PRIM = 9
A7XX_PERF_TSE_BE_CLIPPED_PRIM = 10
A7XX_PERF_TSE_BE_ZERO_AREA_PRIM = 11
A7XX_PERF_TSE_BE_FACENESS_CULLED_PRIM = 12
A7XX_PERF_TSE_BE_ZERO_PIXEL_PRIM = 13
A7XX_PERF_TSE_BE_OUTPUT_NULL_PRIM = 14
A7XX_PERF_TSE_BE_OUTPUT_VISIBLE_PRIM = 15
A7XX_PERF_TSE_BE_CINVOCATION = 16
A7XX_PERF_TSE_BE_CPRIMITIVES = 17
A7XX_PERF_TSE_BE_2D_INPUT_PRIM = 18
A7XX_PERF_TSE_BE_2D_ALIVE_CYCLES = 19
A7XX_PERF_TSE_BE_CLIP_PLANES = 20
A7XX_PERF_TSE_BE_EMPTY_BBOX_KILLED_PRIM = 21
A7XX_PERF_TSE_BE_ST1_VP_PARAMS_CACHE_MISS = 22
A7XX_PERF_TSE_BE_ST2_VPORT_VP_PARAMS_CACHE_MISS = 23
A7XX_PERF_TSE_BE_ST2_SCISSOR_VP_PARAMS_CACHE_MISS = 24
A7XX_PERF_TSE_BE_ILLEGAL_BOUNDING_BOX_PRIM = 25
A7XX_PERF_TSE_BE_VP_OUT_IS_NAN = 26
A7XX_PERF_TSE_BE_EXCLUDED_PRIM = 27
A7XX_PERF_TSE_BE_EARLY_CULL_CLIPPED_PRIM = 28
A7XX_PERF_TSE_BE_BR_STALLS_DUETO_BV_CLIP = 29
A7XX_PERF_TSE_BE_BR_STALLS_DUETO_BV_POLY = 30
A7XX_PERF_TSE_BE_BV_STALLS_DUETO_BR_CLIP = 31
A7XX_PERF_TSE_BE_BV_STALLS_DUETO_BR_POLY = 32
A7XX_PERF_TSE_BE_BV_STALLS_DUETO_BR = 33
A7XX_PERF_TSE_FE_BUSY_CYCLES = 34
A7XX_PERF_TSE_FE_STALL_CYCLES_VPC_US = 35
A7XX_PERF_TSE_FE_STARVE_CYCLES_PC = 36
A7XX_PERF_TSE_FE_INPUT_PRIM = 37
A7XX_PERF_TSE_FE_INPUT_NULL_PRIM = 38
A7XX_PERF_TSE_FE_TRIVAL_REJ_PRIM = 39
A7XX_PERF_TSE_FE_ZERO_AREA_PRIM = 40
A7XX_PERF_TSE_FE_FACENESS_CULLED_PRIM = 41
A7XX_PERF_TSE_FE_ZERO_PIXEL_PRIM = 42
A7XX_PERF_TSE_FE_OUTPUT_NULL_PRIM = 43
A7XX_PERF_TSE_FE_OUTPUT_VISIBLE_PRIM = 44
A7XX_PERF_TSE_FE_CINVOCATION = 45
A7XX_PERF_TSE_FE_CPRIMITIVES = 46
A7XX_PERF_TSE_FE_CLIP_PLANES = 47
A7XX_PERF_TSE_FE_EMPTY_BBOX_KILLED_PRIM = 48
A7XX_PERF_TSE_FE_ST1_VP_PARAMS_CACHE_MISS = 49
A7XX_PERF_TSE_FE_ST2_VPORT_VP_PARAMS_CACHE_MISS = 50
A7XX_PERF_TSE_FE_ST2_SCISSOR_VP_PARAMS_CACHE_MISS = 51
A7XX_PERF_TSE_FE_ILLEGAL_BOUNDING_BOX_PRIM = 52
A7XX_PERF_TSE_FE_VP_OUT_IS_NAN = 53
A7XX_PERF_TSE_FE_EXCLUDED_PRIM = 54
A7XX_PERF_TSE_FE_EARLY_CULL_CLIPPED_PRIM = 55
A7XX_PERF_TSE_FE_BR_STALLS_DUETO_BV_CLIP = 56
A7XX_PERF_TSE_FE_BR_STALLS_DUETO_BV_POLY = 57
A7XX_PERF_TSE_FE_BV_STALLS_DUETO_BR_CLIP = 58
A7XX_PERF_TSE_FE_BV_STALLS_DUETO_BR_POLY = 59
A7XX_PERF_TSE_FE_BV_STALLS_DUETO_BR = 60
A7XX_PERF_TSE_BE_STALL_CYCLES_LRZ_PRIM = 61
a7xx_tse_perfcounter_select = ctypes.c_uint32 # enum
# values for enumeration 'a7xx_ras_perfcounter_select'
a7xx_ras_perfcounter_select__enumvalues = {
0: 'A7XX_PERF_RAS_NEVER_COUNT',
1: 'A7XX_PERF_RAS_BUSY_CYCLES',
2: 'A7XX_PERF_RAS_SUPERTILE_ACTIVE_CYCLES',
3: 'A7XX_PERF_RAS_STALL_CYCLES_LRZ',
4: 'A7XX_PERF_RAS_STARVE_CYCLES_TSE',
5: 'A7XX_PERF_RAS_SUPER_TILES',
6: 'A7XX_PERF_RAS_8X4_TILES',
7: 'A7XX_PERF_RAS_MASKGEN_ACTIVE',
8: 'A7XX_PERF_RAS_FULLY_COVERED_SUPER_TILES',
9: 'A7XX_PERF_RAS_FULLY_COVERED_8X4_TILES',
10: 'A7XX_PERF_RAS_PRIM_KILLED_INVISILBE',
11: 'A7XX_PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES',
12: 'A7XX_PERF_RAS_LRZ_INTF_WORKING_CYCLES',
13: 'A7XX_PERF_RAS_BLOCKS',
14: 'A7XX_PERF_RAS_FALSE_PARTIAL_STILE',
15: 'A7XX_PERF_RAS_SLICE_BLOCK_NONEMTPY',
16: 'A7XX_PERF_RAS_SLICE_BLOCK_EMPTY',
17: 'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_0_WORKING_CC_L2',
18: 'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_1_WORKING_CC_L2',
19: 'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_2_WORKING_CC_L2',
20: 'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_3_WORKING_CC_L2',
21: 'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_4_WORKING_CC_L2',
22: 'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_5_WORKING_CC_L2',
23: 'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_6_WORKING_CC_L2',
24: 'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_7_WORKING_CC_L2',
25: 'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_8_WORKING_CC_L2',
26: 'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_9_WORKING_CC_L2',
27: 'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_10_WORKING_CC_L2',
28: 'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_11_WORKING_CC_L2',
29: 'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_12_WORKING_CC_L2',
30: 'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_13_WORKING_CC_L2',
31: 'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_14_WORKING_CC_L2',
32: 'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_15_WORKING_CC_L2',
}
A7XX_PERF_RAS_NEVER_COUNT = 0
A7XX_PERF_RAS_BUSY_CYCLES = 1
A7XX_PERF_RAS_SUPERTILE_ACTIVE_CYCLES = 2
A7XX_PERF_RAS_STALL_CYCLES_LRZ = 3
A7XX_PERF_RAS_STARVE_CYCLES_TSE = 4
A7XX_PERF_RAS_SUPER_TILES = 5
A7XX_PERF_RAS_8X4_TILES = 6
A7XX_PERF_RAS_MASKGEN_ACTIVE = 7
A7XX_PERF_RAS_FULLY_COVERED_SUPER_TILES = 8
A7XX_PERF_RAS_FULLY_COVERED_8X4_TILES = 9
A7XX_PERF_RAS_PRIM_KILLED_INVISILBE = 10
A7XX_PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES = 11
A7XX_PERF_RAS_LRZ_INTF_WORKING_CYCLES = 12
A7XX_PERF_RAS_BLOCKS = 13
A7XX_PERF_RAS_FALSE_PARTIAL_STILE = 14
A7XX_PERF_RAS_SLICE_BLOCK_NONEMTPY = 15
A7XX_PERF_RAS_SLICE_BLOCK_EMPTY = 16
A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_0_WORKING_CC_L2 = 17
A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_1_WORKING_CC_L2 = 18
A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_2_WORKING_CC_L2 = 19
A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_3_WORKING_CC_L2 = 20
A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_4_WORKING_CC_L2 = 21
A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_5_WORKING_CC_L2 = 22
A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_6_WORKING_CC_L2 = 23
A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_7_WORKING_CC_L2 = 24
A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_8_WORKING_CC_L2 = 25
A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_9_WORKING_CC_L2 = 26
A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_10_WORKING_CC_L2 = 27
A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_11_WORKING_CC_L2 = 28
A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_12_WORKING_CC_L2 = 29
A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_13_WORKING_CC_L2 = 30
A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_14_WORKING_CC_L2 = 31
A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_15_WORKING_CC_L2 = 32
a7xx_ras_perfcounter_select = ctypes.c_uint32 # enum
# values for enumeration 'a7xx_uche_perfcounter_select'
a7xx_uche_perfcounter_select__enumvalues = {
0: 'A7XX_PERF_UCHE_NEVER_COUNT',
1: 'A7XX_PERF_UCHE_BUSY_CYCLES',
2: 'A7XX_PERF_UCHE_STALL_CYCLES_ARBITER',
3: 'A7XX_PERF_UCHE_VBIF_STALL_WRITE_DATA',
4: 'A7XX_PERF_UCHE_STARVED_CYCLES_VBIF_DECMP',
5: 'A7XX_PERF_UCHE_STALL_CYCLES_DECMP',
6: 'A7XX_PERF_UCHE_ARBITER_STALL_CYCLES_VBIF',
7: 'A7XX_PERF_UCHE_VBIF_LATENCY_CYCLES',
8: 'A7XX_PERF_UCHE_VBIF_LATENCY_SAMPLES',
9: 'A7XX_PERF_UCHE_DCMP_LATENCY_SAMPLES',
10: 'A7XX_PERF_UCHE_DCMP_LATENCY_CYCLES',
11: 'A7XX_PERF_UCHE_READ_REQUESTS_SP',
12: 'A7XX_PERF_UCHE_READ_REQUESTS_TP',
13: 'A7XX_PERF_UCHE_READ_REQUESTS_TP_UBWC',
14: 'A7XX_PERF_UCHE_READ_REQUESTS_TP_GBIF',
15: 'A7XX_PERF_UCHE_READ_REQUESTS_TP_GMEM',
16: 'A7XX_PERF_UCHE_READ_REQUESTS_VFD',
17: 'A7XX_PERF_UCHE_READ_REQUESTS_VPC',
18: 'A7XX_PERF_UCHE_READ_REQUESTS_HLSQ',
19: 'A7XX_PERF_UCHE_READ_REQUESTS_LRZ',
20: 'A7XX_PERF_UCHE_READ_REQUESTS_PC',
21: 'A7XX_PERF_UCHE_WRITE_REQUESTS_SP',
22: 'A7XX_PERF_UCHE_WRITE_REQUESTS_LRZ',
23: 'A7XX_PERF_UCHE_WRITE_REQUESTS_VPC',
24: 'A7XX_PERF_UCHE_WRITE_REQUESTS_VSC',
25: 'A7XX_PERF_UCHE_VBIF_READ_BEATS_SP',
26: 'A7XX_PERF_UCHE_VBIF_READ_BEATS_TP',
27: 'A7XX_PERF_UCHE_VBIF_READ_BEATS_VFD',
28: 'A7XX_PERF_UCHE_VBIF_READ_BEATS_VPC',
29: 'A7XX_PERF_UCHE_VBIF_READ_BEATS_HLSQ',
30: 'A7XX_PERF_UCHE_VBIF_READ_BEATS_LRZ',
31: 'A7XX_PERF_UCHE_VBIF_READ_BEATS_PC',
32: 'A7XX_PERF_UCHE_VBIF_READ_BEATS_CH0',
33: 'A7XX_PERF_UCHE_VBIF_READ_BEATS_CH1',
34: 'A7XX_PERF_UCHE_VBIF_WRITE_BEATS_CH0',
35: 'A7XX_PERF_UCHE_VBIF_WRITE_BEATS_CH1',
36: 'A7XX_PERF_UCHE_GMEM_READ_BEATS',
37: 'A7XX_PERF_UCHE_GMEM_WRITE_BEATS',
38: 'A7XX_PERF_UCHE_UBWC_READ_BEATS',
39: 'A7XX_PERF_UCHE_UBWC_WRITE_BEATS',
40: 'A7XX_PERF_UCHE_EVICTS',
41: 'A7XX_PERF_UCHE_BANK_REQ0',
42: 'A7XX_PERF_UCHE_BANK_REQ1',
43: 'A7XX_PERF_UCHE_BANK_REQ2',
44: 'A7XX_PERF_UCHE_BANK_REQ3',
45: 'A7XX_PERF_UCHE_BANK_REQ4',
46: 'A7XX_PERF_UCHE_BANK_REQ5',
47: 'A7XX_PERF_UCHE_BANK_REQ6',
48: 'A7XX_PERF_UCHE_BANK_REQ7',
49: 'A7XX_PERF_UCHE_TPH_REF_FULL',
50: 'A7XX_PERF_UCHE_TPH_VICTIM_FULL',
51: 'A7XX_PERF_UCHE_TPH_EXT_FULL',
52: 'A7XX_PERF_UCHE_RAM_READ_REQ',
53: 'A7XX_PERF_UCHE_RAM_WRITE_REQ',
54: 'A7XX_PERF_UCHE_LONG_LINE_ALL_EVICTS',
55: 'A7XX_PERF_UCHE_LONG_LINE_PARTIAL_EVICTS',
56: 'A7XX_PERF_UCHE_TPH_CONFLICT_CL_CCHE',
57: 'A7XX_PERF_UCHE_TPH_CONFLICT_CL_OTHER',
58: 'A7XX_PERF_UCHE_DBANK_CONFLICT_CL_CCHE',
59: 'A7XX_PERF_UCHE_DBANK_CONFLICT_CL_OTHER_CLIENTS',
60: 'A7XX_PERF_UCHE_CCHE_TPH_QUEUE_FULL',
61: 'A7XX_PERF_UCHE_CCHE_DPH_IO_QUEUE_FULL',
62: 'A7XX_PERF_UCHE_CCHE_DPH_CMDPOOL_FULL',
63: 'A7XX_PERF_UCHE_EVICTS_SP',
64: 'A7XX_PERF_UCHE_EVICTS_LRZ',
65: 'A7XX_PERF_UCHE_READ_REQUESTS_VPCUS',
66: 'A7XX_PERF_UCHE_READ_REQUESTS_VFD_BYPASS_BV',
67: 'A7XX_PERF_UCHE_READ_REQUESTS_VFD_BYPASS_BR',
68: 'A7XX_PERF_BYPC_FULL',
69: 'A7XX_PERF_BYPC_FULL_CCHE_STALL',
70: 'A7XX_PERF_BYPC_VHUB_STALL',
71: 'A7XX_PERF_BYPD_FULL',
72: 'A7XX_PERF_BYPD_FULL_GBIF_STALL',
73: 'A7XX_PERF_VHUB_PTABLE_FULL',
74: 'A7XX_PERF_DHUB_PTABLE_FULL',
75: 'A7XX_PERF_UCHE_RESERVED_75',
76: 'A7XX_PERF_UCHE_RESERVED_76',
77: 'A7XX_PERF_UCHE_RESERVED_77',
78: 'A7XX_PERF_UCHE_RESERVED_78',
79: 'A7XX_PERF_UCHE_RESERVED_79',
80: 'A7XX_PERF_UCHE_RESERVED_80',
81: 'A7XX_PERF_UCHE_RESERVED_81',
82: 'A7XX_PERF_UCHE_RESERVED_82',
83: 'A7XX_PERF_UCHE_RESERVED_83',
84: 'A7XX_PERF_UCHE_RESERVED_84',
85: 'A7XX_PERF_UCHE_RESERVED_85',
86: 'A7XX_PERF_UCHE_RESERVED_86',
87: 'A7XX_PERF_UCHE_RESERVED_87',
88: 'A7XX_PERF_UCHE_RESERVED_88',
89: 'A7XX_PERF_UCHE_RESERVED_89',
90: 'A7XX_PERF_UCHE_RESERVED_90',
91: 'A7XX_PERF_UCHE_RESERVED_91',
92: 'A7XX_PERF_UCHE_RESERVED_92',
93: 'A7XX_PERF_UCHE_RESERVED_93',
94: 'A7XX_PERF_UCHE_RESERVED_94',
95: 'A7XX_PERF_UCHE_RESERVED_95',
96: 'A7XX_PERF_UCHE_RESERVED_96',
97: 'A7XX_PERF_UCHE_RESERVED_97',
98: 'A7XX_PERF_UCHE_RESERVED_98',
99: 'A7XX_PERF_UCHE_RESERVED_99',
100: 'A7XX_PERF_UCHE_RESERVED_100',
101: 'A7XX_PERF_UCHE_RESERVED_101',
102: 'A7XX_PERF_UCHE_RESERVED_102',
103: 'A7XX_PERF_UCHE_RESERVED_103',
104: 'A7XX_PERF_UCHE_RESERVED_104',
105: 'A7XX_PERF_UCHE_RESERVED_105',
106: 'A7XX_PERF_UCHE_RESERVED_106',
107: 'A7XX_PERF_UCHE_RESERVED_107',
108: 'A7XX_PERF_UCHE_RESERVED_108',
109: 'A7XX_PERF_UCHE_RESERVED_109',
110: 'A7XX_PERF_UCHE_RESERVED_110',
111: 'A7XX_PERF_UCHE_RESERVED_111',
112: 'A7XX_PERF_UCHE_RESERVED_112',
113: 'A7XX_PERF_UCHE_RESERVED_113',
114: 'A7XX_PERF_UCHE_RESERVED_114',
115: 'A7XX_PERF_UCHE_RESERVED_115',
116: 'A7XX_PERF_UCHE_RESERVED_116',
117: 'A7XX_PERF_UCHE_RESERVED_117',
118: 'A7XX_PERF_UCHE_RESERVED_118',
119: 'A7XX_PERF_UCHE_RESERVED_119',
120: 'A7XX_PERF_UCHE_RESERVED_120',
121: 'A7XX_PERF_UCHE_RESERVED_121',
122: 'A7XX_PERF_UCHE_RESERVED_122',
123: 'A7XX_PERF_UCHE_RESERVED_123',
124: 'A7XX_PERF_UCHE_RESERVED_124',
125: 'A7XX_PERF_UCHE_RESERVED_125',
126: 'A7XX_PERF_UCHE_RESERVED_126',
127: 'A7XX_PERF_UCHE_RESERVED_127',
128: 'A7XX_PERF_CCHE_BUSY_CYCLES',
129: 'A7XX_PERF_CCHE_STALL_CYCLES_UCHE',
130: 'A7XX_PERF_CCHE_UCHE_STALL_WRITE_DATA',
131: 'A7XX_PERF_CCHE_UCHE_LATENCY_CYCLES',
132: 'A7XX_PERF_CCHE_UCHE_LATENCY_SAMPLES',
133: 'A7XX_PERF_CCHE_READ_REQUESTS_SP_TOTAL',
134: 'A7XX_PERF_CCHE_READ_REQUESTS_SP_UBWC',
135: 'A7XX_PERF_CCHE_READ_REQUESTS_SP_GBIF',
136: 'A7XX_PERF_CCHE_READ_REQUESTS_SP_GMEM',
137: 'A7XX_PERF_CCHE_READ_REQUESTS_TP_TOTAL',
138: 'A7XX_PERF_CCHE_READ_REQUESTS_TP_UBWC',
139: 'A7XX_PERF_CCHE_READ_REQUESTS_TP_GBIF',
140: 'A7XX_PERF_CCHE_READ_REQUESTS_TP_GMEM',
141: 'A7XX_PERF_CCHE_READ_REQUESTS_VFD_TOTAL',
142: 'A7XX_PERF_CCHE_READ_REQUEST_VFD_GMEM',
143: 'A7XX_PERF_CCHE_READ_REQUEST_VFD_GBIF',
144: 'A7XX_PERF_CCHE_READ_REQUESTS_LRZ',
145: 'A7XX_PERF_CCHE_READ_REQUESTS_VPC',
146: 'A7XX_PERF_CCHE_WRITE_REQUESTS_SP',
147: 'A7XX_PERF_CCHE_WRITE_REQUESTS_LRZ',
148: 'A7XX_PERF_CCHE_READ_REQUESTS_GMEM',
149: 'A7XX_PERF_CCHE_WRITE_REQUESTS_GMEM',
150: 'A7XX_PERF_CCHE_UCHE_READ_BEATS_TP',
151: 'A7XX_PERF_CCHE_UCHE_READ_BEATS_VFD',
152: 'A7XX_PERF_CCHE_UCHE_READ_BEATS_SP',
153: 'A7XX_PERF_CCHE_UCHE_READ_BEATS_VPC',
154: 'A7XX_PERF_CCHE_UCHE_READ_BEATS_LRZ',
155: 'A7XX_PERF_CCHE_UCHE_READ_BEATS_CH0',
156: 'A7XX_PERF_CCHE_UCHE_READ_BEATS_CH1',
157: 'A7XX_PERF_CCHE_GMEM_READ_BEATS_VPC',
158: 'A7XX_PERF_CCHE_GMEM_READ_BEATS_TP',
159: 'A7XX_PERF_CCHE_GMEM_READ_BEATS_SP',
160: 'A7XX_PERF_CCHE_GMEM_READ_BEATS_VFD',
161: 'A7XX_PERF_CCHE_BANK_REQ0',
162: 'A7XX_PERF_CCHE_BANK_REQ1',
163: 'A7XX_PERF_CCHE_BANK_REQ2',
164: 'A7XX_PERF_CCHE_BANK_REQ3',
165: 'A7XX_PERF_CCHE_BANK_REQ4',
166: 'A7XX_PERF_CCHE_BANK_REQ5',
167: 'A7XX_PERF_CCHE_BANK_REQ6',
168: 'A7XX_PERF_CCHE_BANK_REQ7',
169: 'A7XX_PERF_CCHE_BANK_REQ8',
170: 'A7XX_PERF_CCHE_BANK_REQ9',
171: 'A7XX_PERF_CCHE_BANK_REQ10',
172: 'A7XX_PERF_CCHE_BANK_REQ11',
173: 'A7XX_PERF_CCHE_BANK_REQ12',
174: 'A7XX_PERF_CCHE_BANK_REQ13',
175: 'A7XX_PERF_CCHE_BANK_REQ14',
176: 'A7XX_PERF_CCHE_BANK_REQ15',
177: 'A7XX_PERF_CCHE_GBANK_REQ0',
178: 'A7XX_PERF_CCHE_GBANK_REQ1',
179: 'A7XX_PERF_CCHE_GBANK_REQ2',
180: 'A7XX_PERF_CCHE_GBANK_REQ3',
181: 'A7XX_PERF_CCHE_TPH_REF_FULL',
182: 'A7XX_PERF_CCHE_TPH_VICTIM_FULL',
183: 'A7XX_PERF_CCHE_TPH_EXT_FULL',
184: 'A7XX_PERF_CCHE_RAM_READ_REQ',
185: 'A7XX_PERF_CCHE_RAM_WRITE_REQ',
186: 'A7XX_PERF_CCHE_TPH_CONFLICT_CL',
187: 'A7XX_PERF_CCHE_DBANK_CONFLICT',
188: 'A7XX_PERF_CCHE_TPH_QUEUE_FULL',
189: 'A7XX_PERF_CCHE_DPH_QUEUE_FULL',
190: 'A7XX_PERF_CCHE_OPH_QUEUE_FULL',
191: 'A7XX_PERF_CCHE_WACK_QUEUE_FULL',
192: 'A7XX_PERF_CCHE_GMEM0_LOCAL_RD_REQUEST',
193: 'A7XX_PERF_CCHE_GMEM0_LOCAL_WR_REQUEST',
194: 'A7XX_PERF_CCHE_GMEM1_LOCAL_RD_REQUEST',
195: 'A7XX_PERF_CCHE_GMEM1_LOCAL_WR_REQUEST',
196: 'A7XX_PERF_CCHE_GMEM0_REMOTE_RD_REQUEST',
197: 'A7XX_PERF_CCHE_GMEM0_REMOTE_WR_REQUEST',
198: 'A7XX_PERF_CCHE_GMEM1_REMOTE_RD_REQUEST',
199: 'A7XX_PERF_CCHE_GMEM1_REMOTE_WR_REQUEST',
200: 'A7XX_PERF_CCHE_STALL_CYCLES_TP',
}
A7XX_PERF_UCHE_NEVER_COUNT = 0
A7XX_PERF_UCHE_BUSY_CYCLES = 1
A7XX_PERF_UCHE_STALL_CYCLES_ARBITER = 2
A7XX_PERF_UCHE_VBIF_STALL_WRITE_DATA = 3
A7XX_PERF_UCHE_STARVED_CYCLES_VBIF_DECMP = 4
A7XX_PERF_UCHE_STALL_CYCLES_DECMP = 5
A7XX_PERF_UCHE_ARBITER_STALL_CYCLES_VBIF = 6
A7XX_PERF_UCHE_VBIF_LATENCY_CYCLES = 7
A7XX_PERF_UCHE_VBIF_LATENCY_SAMPLES = 8
A7XX_PERF_UCHE_DCMP_LATENCY_SAMPLES = 9
A7XX_PERF_UCHE_DCMP_LATENCY_CYCLES = 10
A7XX_PERF_UCHE_READ_REQUESTS_SP = 11
A7XX_PERF_UCHE_READ_REQUESTS_TP = 12
A7XX_PERF_UCHE_READ_REQUESTS_TP_UBWC = 13
A7XX_PERF_UCHE_READ_REQUESTS_TP_GBIF = 14
A7XX_PERF_UCHE_READ_REQUESTS_TP_GMEM = 15
A7XX_PERF_UCHE_READ_REQUESTS_VFD = 16
A7XX_PERF_UCHE_READ_REQUESTS_VPC = 17
A7XX_PERF_UCHE_READ_REQUESTS_HLSQ = 18
A7XX_PERF_UCHE_READ_REQUESTS_LRZ = 19
A7XX_PERF_UCHE_READ_REQUESTS_PC = 20
A7XX_PERF_UCHE_WRITE_REQUESTS_SP = 21
A7XX_PERF_UCHE_WRITE_REQUESTS_LRZ = 22
A7XX_PERF_UCHE_WRITE_REQUESTS_VPC = 23
A7XX_PERF_UCHE_WRITE_REQUESTS_VSC = 24
A7XX_PERF_UCHE_VBIF_READ_BEATS_SP = 25
A7XX_PERF_UCHE_VBIF_READ_BEATS_TP = 26
A7XX_PERF_UCHE_VBIF_READ_BEATS_VFD = 27
A7XX_PERF_UCHE_VBIF_READ_BEATS_VPC = 28
A7XX_PERF_UCHE_VBIF_READ_BEATS_HLSQ = 29
A7XX_PERF_UCHE_VBIF_READ_BEATS_LRZ = 30
A7XX_PERF_UCHE_VBIF_READ_BEATS_PC = 31
A7XX_PERF_UCHE_VBIF_READ_BEATS_CH0 = 32
A7XX_PERF_UCHE_VBIF_READ_BEATS_CH1 = 33
A7XX_PERF_UCHE_VBIF_WRITE_BEATS_CH0 = 34
A7XX_PERF_UCHE_VBIF_WRITE_BEATS_CH1 = 35
A7XX_PERF_UCHE_GMEM_READ_BEATS = 36
A7XX_PERF_UCHE_GMEM_WRITE_BEATS = 37
A7XX_PERF_UCHE_UBWC_READ_BEATS = 38
A7XX_PERF_UCHE_UBWC_WRITE_BEATS = 39
A7XX_PERF_UCHE_EVICTS = 40
A7XX_PERF_UCHE_BANK_REQ0 = 41
A7XX_PERF_UCHE_BANK_REQ1 = 42
A7XX_PERF_UCHE_BANK_REQ2 = 43
A7XX_PERF_UCHE_BANK_REQ3 = 44
A7XX_PERF_UCHE_BANK_REQ4 = 45
A7XX_PERF_UCHE_BANK_REQ5 = 46
A7XX_PERF_UCHE_BANK_REQ6 = 47
A7XX_PERF_UCHE_BANK_REQ7 = 48
A7XX_PERF_UCHE_TPH_REF_FULL = 49
A7XX_PERF_UCHE_TPH_VICTIM_FULL = 50
A7XX_PERF_UCHE_TPH_EXT_FULL = 51
A7XX_PERF_UCHE_RAM_READ_REQ = 52
A7XX_PERF_UCHE_RAM_WRITE_REQ = 53
A7XX_PERF_UCHE_LONG_LINE_ALL_EVICTS = 54
A7XX_PERF_UCHE_LONG_LINE_PARTIAL_EVICTS = 55
A7XX_PERF_UCHE_TPH_CONFLICT_CL_CCHE = 56
A7XX_PERF_UCHE_TPH_CONFLICT_CL_OTHER = 57
A7XX_PERF_UCHE_DBANK_CONFLICT_CL_CCHE = 58
A7XX_PERF_UCHE_DBANK_CONFLICT_CL_OTHER_CLIENTS = 59
A7XX_PERF_UCHE_CCHE_TPH_QUEUE_FULL = 60
A7XX_PERF_UCHE_CCHE_DPH_IO_QUEUE_FULL = 61
A7XX_PERF_UCHE_CCHE_DPH_CMDPOOL_FULL = 62
A7XX_PERF_UCHE_EVICTS_SP = 63
A7XX_PERF_UCHE_EVICTS_LRZ = 64
A7XX_PERF_UCHE_READ_REQUESTS_VPCUS = 65
A7XX_PERF_UCHE_READ_REQUESTS_VFD_BYPASS_BV = 66
A7XX_PERF_UCHE_READ_REQUESTS_VFD_BYPASS_BR = 67
A7XX_PERF_BYPC_FULL = 68
A7XX_PERF_BYPC_FULL_CCHE_STALL = 69
A7XX_PERF_BYPC_VHUB_STALL = 70
A7XX_PERF_BYPD_FULL = 71
A7XX_PERF_BYPD_FULL_GBIF_STALL = 72
A7XX_PERF_VHUB_PTABLE_FULL = 73
A7XX_PERF_DHUB_PTABLE_FULL = 74
A7XX_PERF_UCHE_RESERVED_75 = 75
A7XX_PERF_UCHE_RESERVED_76 = 76
A7XX_PERF_UCHE_RESERVED_77 = 77
A7XX_PERF_UCHE_RESERVED_78 = 78
A7XX_PERF_UCHE_RESERVED_79 = 79
A7XX_PERF_UCHE_RESERVED_80 = 80
A7XX_PERF_UCHE_RESERVED_81 = 81
A7XX_PERF_UCHE_RESERVED_82 = 82
A7XX_PERF_UCHE_RESERVED_83 = 83
A7XX_PERF_UCHE_RESERVED_84 = 84
A7XX_PERF_UCHE_RESERVED_85 = 85
A7XX_PERF_UCHE_RESERVED_86 = 86
A7XX_PERF_UCHE_RESERVED_87 = 87
A7XX_PERF_UCHE_RESERVED_88 = 88
A7XX_PERF_UCHE_RESERVED_89 = 89
A7XX_PERF_UCHE_RESERVED_90 = 90
A7XX_PERF_UCHE_RESERVED_91 = 91
A7XX_PERF_UCHE_RESERVED_92 = 92
A7XX_PERF_UCHE_RESERVED_93 = 93
A7XX_PERF_UCHE_RESERVED_94 = 94
A7XX_PERF_UCHE_RESERVED_95 = 95
A7XX_PERF_UCHE_RESERVED_96 = 96
A7XX_PERF_UCHE_RESERVED_97 = 97
A7XX_PERF_UCHE_RESERVED_98 = 98
A7XX_PERF_UCHE_RESERVED_99 = 99
A7XX_PERF_UCHE_RESERVED_100 = 100
A7XX_PERF_UCHE_RESERVED_101 = 101
A7XX_PERF_UCHE_RESERVED_102 = 102
A7XX_PERF_UCHE_RESERVED_103 = 103
A7XX_PERF_UCHE_RESERVED_104 = 104
A7XX_PERF_UCHE_RESERVED_105 = 105
A7XX_PERF_UCHE_RESERVED_106 = 106
A7XX_PERF_UCHE_RESERVED_107 = 107
A7XX_PERF_UCHE_RESERVED_108 = 108
A7XX_PERF_UCHE_RESERVED_109 = 109
A7XX_PERF_UCHE_RESERVED_110 = 110
A7XX_PERF_UCHE_RESERVED_111 = 111
A7XX_PERF_UCHE_RESERVED_112 = 112
A7XX_PERF_UCHE_RESERVED_113 = 113
A7XX_PERF_UCHE_RESERVED_114 = 114
A7XX_PERF_UCHE_RESERVED_115 = 115
A7XX_PERF_UCHE_RESERVED_116 = 116
A7XX_PERF_UCHE_RESERVED_117 = 117
A7XX_PERF_UCHE_RESERVED_118 = 118
A7XX_PERF_UCHE_RESERVED_119 = 119
A7XX_PERF_UCHE_RESERVED_120 = 120
A7XX_PERF_UCHE_RESERVED_121 = 121
A7XX_PERF_UCHE_RESERVED_122 = 122
A7XX_PERF_UCHE_RESERVED_123 = 123
A7XX_PERF_UCHE_RESERVED_124 = 124
A7XX_PERF_UCHE_RESERVED_125 = 125
A7XX_PERF_UCHE_RESERVED_126 = 126
A7XX_PERF_UCHE_RESERVED_127 = 127
A7XX_PERF_CCHE_BUSY_CYCLES = 128
A7XX_PERF_CCHE_STALL_CYCLES_UCHE = 129
A7XX_PERF_CCHE_UCHE_STALL_WRITE_DATA = 130
A7XX_PERF_CCHE_UCHE_LATENCY_CYCLES = 131
A7XX_PERF_CCHE_UCHE_LATENCY_SAMPLES = 132
A7XX_PERF_CCHE_READ_REQUESTS_SP_TOTAL = 133
A7XX_PERF_CCHE_READ_REQUESTS_SP_UBWC = 134
A7XX_PERF_CCHE_READ_REQUESTS_SP_GBIF = 135
A7XX_PERF_CCHE_READ_REQUESTS_SP_GMEM = 136
A7XX_PERF_CCHE_READ_REQUESTS_TP_TOTAL = 137
A7XX_PERF_CCHE_READ_REQUESTS_TP_UBWC = 138
A7XX_PERF_CCHE_READ_REQUESTS_TP_GBIF = 139
A7XX_PERF_CCHE_READ_REQUESTS_TP_GMEM = 140
A7XX_PERF_CCHE_READ_REQUESTS_VFD_TOTAL = 141
A7XX_PERF_CCHE_READ_REQUEST_VFD_GMEM = 142
A7XX_PERF_CCHE_READ_REQUEST_VFD_GBIF = 143
A7XX_PERF_CCHE_READ_REQUESTS_LRZ = 144
A7XX_PERF_CCHE_READ_REQUESTS_VPC = 145
A7XX_PERF_CCHE_WRITE_REQUESTS_SP = 146
A7XX_PERF_CCHE_WRITE_REQUESTS_LRZ = 147
A7XX_PERF_CCHE_READ_REQUESTS_GMEM = 148
A7XX_PERF_CCHE_WRITE_REQUESTS_GMEM = 149
A7XX_PERF_CCHE_UCHE_READ_BEATS_TP = 150
A7XX_PERF_CCHE_UCHE_READ_BEATS_VFD = 151
A7XX_PERF_CCHE_UCHE_READ_BEATS_SP = 152
A7XX_PERF_CCHE_UCHE_READ_BEATS_VPC = 153
A7XX_PERF_CCHE_UCHE_READ_BEATS_LRZ = 154
A7XX_PERF_CCHE_UCHE_READ_BEATS_CH0 = 155
A7XX_PERF_CCHE_UCHE_READ_BEATS_CH1 = 156
A7XX_PERF_CCHE_GMEM_READ_BEATS_VPC = 157
A7XX_PERF_CCHE_GMEM_READ_BEATS_TP = 158
A7XX_PERF_CCHE_GMEM_READ_BEATS_SP = 159
A7XX_PERF_CCHE_GMEM_READ_BEATS_VFD = 160
A7XX_PERF_CCHE_BANK_REQ0 = 161
A7XX_PERF_CCHE_BANK_REQ1 = 162
A7XX_PERF_CCHE_BANK_REQ2 = 163
A7XX_PERF_CCHE_BANK_REQ3 = 164
A7XX_PERF_CCHE_BANK_REQ4 = 165
A7XX_PERF_CCHE_BANK_REQ5 = 166
A7XX_PERF_CCHE_BANK_REQ6 = 167
A7XX_PERF_CCHE_BANK_REQ7 = 168
A7XX_PERF_CCHE_BANK_REQ8 = 169
A7XX_PERF_CCHE_BANK_REQ9 = 170
A7XX_PERF_CCHE_BANK_REQ10 = 171
A7XX_PERF_CCHE_BANK_REQ11 = 172
A7XX_PERF_CCHE_BANK_REQ12 = 173
A7XX_PERF_CCHE_BANK_REQ13 = 174
A7XX_PERF_CCHE_BANK_REQ14 = 175
A7XX_PERF_CCHE_BANK_REQ15 = 176
A7XX_PERF_CCHE_GBANK_REQ0 = 177
A7XX_PERF_CCHE_GBANK_REQ1 = 178
A7XX_PERF_CCHE_GBANK_REQ2 = 179
A7XX_PERF_CCHE_GBANK_REQ3 = 180
A7XX_PERF_CCHE_TPH_REF_FULL = 181
A7XX_PERF_CCHE_TPH_VICTIM_FULL = 182
A7XX_PERF_CCHE_TPH_EXT_FULL = 183
A7XX_PERF_CCHE_RAM_READ_REQ = 184
A7XX_PERF_CCHE_RAM_WRITE_REQ = 185
A7XX_PERF_CCHE_TPH_CONFLICT_CL = 186
A7XX_PERF_CCHE_DBANK_CONFLICT = 187
A7XX_PERF_CCHE_TPH_QUEUE_FULL = 188
A7XX_PERF_CCHE_DPH_QUEUE_FULL = 189
A7XX_PERF_CCHE_OPH_QUEUE_FULL = 190
A7XX_PERF_CCHE_WACK_QUEUE_FULL = 191
A7XX_PERF_CCHE_GMEM0_LOCAL_RD_REQUEST = 192
A7XX_PERF_CCHE_GMEM0_LOCAL_WR_REQUEST = 193
A7XX_PERF_CCHE_GMEM1_LOCAL_RD_REQUEST = 194
A7XX_PERF_CCHE_GMEM1_LOCAL_WR_REQUEST = 195
A7XX_PERF_CCHE_GMEM0_REMOTE_RD_REQUEST = 196
A7XX_PERF_CCHE_GMEM0_REMOTE_WR_REQUEST = 197
A7XX_PERF_CCHE_GMEM1_REMOTE_RD_REQUEST = 198
A7XX_PERF_CCHE_GMEM1_REMOTE_WR_REQUEST = 199
A7XX_PERF_CCHE_STALL_CYCLES_TP = 200
a7xx_uche_perfcounter_select = ctypes.c_uint32 # enum
# values for enumeration 'a7xx_tp_perfcounter_select'
a7xx_tp_perfcounter_select__enumvalues = {
0: 'A7XX_PERF_TP_NEVER_COUNT',
1: 'A7XX_PERF_TP_BUSY_CYCLES',
2: 'A7XX_PERF_TP_STALL_CYCLES_UCHE',
3: 'A7XX_PERF_TP_LATENCY_CYCLES',
4: 'A7XX_PERF_TP_LATENCY_TRANS',
5: 'A7XX_PERF_TP_FLAG_FIFO_DELAY_SAMPLES',
6: 'A7XX_PERF_TP_FLAG_FIFO_DELAY_CYCLES',
7: 'A7XX_PERF_TP_L1_CACHELINE_REQUESTS',
8: 'A7XX_PERF_TP_L1_CACHELINE_MISSES',
9: 'A7XX_PERF_TP_SP_TP_TRANS',
10: 'A7XX_PERF_TP_TP_SP_TRANS',
11: 'A7XX_PERF_TP_OUTPUT_PIXELS',
12: 'A7XX_PERF_TP_FILTER_WORKLOAD_16BIT',
13: 'A7XX_PERF_TP_FILTER_WORKLOAD_32BIT',
14: 'A7XX_PERF_TP_QUADS_RECEIVED',
15: 'A7XX_PERF_TP_QUADS_OFFSET',
16: 'A7XX_PERF_TP_QUADS_SHADOW',
17: 'A7XX_PERF_TP_QUADS_ARRAY',
18: 'A7XX_PERF_TP_QUADS_GRADIENT',
19: 'A7XX_PERF_TP_QUADS_1D',
20: 'A7XX_PERF_TP_QUADS_2D',
21: 'A7XX_PERF_TP_QUADS_BUFFER',
22: 'A7XX_PERF_TP_QUADS_3D',
23: 'A7XX_PERF_TP_QUADS_CUBE',
24: 'A7XX_PERF_TP_DIVERGENT_QUADS_RECEIVED',
25: 'A7XX_PERF_TP_PRT_NON_RESIDENT_EVENTS',
26: 'A7XX_PERF_TP_OUTPUT_PIXELS_POINT',
27: 'A7XX_PERF_TP_OUTPUT_PIXELS_BILINEAR',
28: 'A7XX_PERF_TP_OUTPUT_PIXELS_MIP',
29: 'A7XX_PERF_TP_OUTPUT_PIXELS_ANISO',
30: 'A7XX_PERF_TP_OUTPUT_PIXELS_ZERO_LOD',
31: 'A7XX_PERF_TP_FLAG_CACHE_REQUESTS',
32: 'A7XX_PERF_TP_FLAG_CACHE_MISSES',
33: 'A7XX_PERF_TP_L1_5_L2_REQUESTS',
34: 'A7XX_PERF_TP_2D_OUTPUT_PIXELS',
35: 'A7XX_PERF_TP_2D_OUTPUT_PIXELS_POINT',
36: 'A7XX_PERF_TP_2D_OUTPUT_PIXELS_BILINEAR',
37: 'A7XX_PERF_TP_2D_FILTER_WORKLOAD_16BIT',
38: 'A7XX_PERF_TP_2D_FILTER_WORKLOAD_32BIT',
39: 'A7XX_PERF_TP_TPA2TPC_TRANS',
40: 'A7XX_PERF_TP_L1_MISSES_ASTC_1TILE',
41: 'A7XX_PERF_TP_L1_MISSES_ASTC_2TILE',
42: 'A7XX_PERF_TP_L1_MISSES_ASTC_4TILE',
43: 'A7XX_PERF_TP_L1_5_COMPRESS_REQS',
44: 'A7XX_PERF_TP_L1_5_L2_COMPRESS_MISS',
45: 'A7XX_PERF_TP_L1_BANK_CONFLICT',
46: 'A7XX_PERF_TP_L1_5_MISS_LATENCY_CYCLES',
47: 'A7XX_PERF_TP_L1_5_MISS_LATENCY_TRANS',
48: 'A7XX_PERF_TP_QUADS_CONSTANT_MULTIPLIED',
49: 'A7XX_PERF_TP_FRONTEND_WORKING_CYCLES',
50: 'A7XX_PERF_TP_L1_TAG_WORKING_CYCLES',
51: 'A7XX_PERF_TP_L1_DATA_WRITE_WORKING_CYCLES',
52: 'A7XX_PERF_TP_PRE_L1_DECOM_WORKING_CYCLES',
53: 'A7XX_PERF_TP_BACKEND_WORKING_CYCLES',
54: 'A7XX_PERF_TP_L1_5_CACHE_WORKING_CYCLES',
55: 'A7XX_PERF_TP_STARVE_CYCLES_SP',
56: 'A7XX_PERF_TP_STARVE_CYCLES_UCHE',
57: 'A7XX_PERF_TP_STALL_CYCLES_UFC',
58: 'A7XX_PERF_TP_FORMAT_DECOMP_POINT',
59: 'A7XX_PERF_TP_FILTER_POINT_FP16',
60: 'A7XX_PERF_TP_FILTER_POINT_FP32',
61: 'A7XX_PERF_TP_LATENCY_FIFO_FULL',
62: 'A7XX_PERF_TP_RESERVED_62',
63: 'A7XX_PERF_TP_RESERVED_63',
64: 'A7XX_PERF_TP_RESERVED_64',
65: 'A7XX_PERF_TP_RESERVED_65',
66: 'A7XX_PERF_TP_RESERVED_66',
67: 'A7XX_PERF_TP_RESERVED_67',
68: 'A7XX_PERF_TP_RESERVED_68',
69: 'A7XX_PERF_TP_RESERVED_69',
70: 'A7XX_PERF_TP_RESERVED_70',
71: 'A7XX_PERF_TP_RESERVED_71',
72: 'A7XX_PERF_TP_RESERVED_72',
73: 'A7XX_PERF_TP_RESERVED_73',
74: 'A7XX_PERF_TP_RESERVED_74',
75: 'A7XX_PERF_TP_RESERVED_75',
76: 'A7XX_PERF_TP_RESERVED_76',
77: 'A7XX_PERF_TP_RESERVED_77',
78: 'A7XX_PERF_TP_RESERVED_78',
79: 'A7XX_PERF_TP_RESERVED_79',
80: 'A7XX_PERF_TP_RESERVED_80',
81: 'A7XX_PERF_TP_RESERVED_81',
82: 'A7XX_PERF_TP_RESERVED_82',
83: 'A7XX_PERF_TP_RESERVED_83',
84: 'A7XX_PERF_TP_RESERVED_84',
85: 'A7XX_PERF_TP_RESERVED_85',
86: 'A7XX_PERF_TP_RESERVED_86',
87: 'A7XX_PERF_TP_RESERVED_87',
88: 'A7XX_PERF_TP_RESERVED_88',
89: 'A7XX_PERF_TP_RESERVED_89',
90: 'A7XX_PERF_TP_RESERVED_90',
91: 'A7XX_PERF_TP_RESERVED_91',
92: 'A7XX_PERF_TP_RESERVED_92',
93: 'A7XX_PERF_TP_RESERVED_93',
94: 'A7XX_PERF_TP_RESERVED_94',
95: 'A7XX_PERF_TP_RESERVED_95',
96: 'A7XX_PERF_TP_RESERVED_96',
97: 'A7XX_PERF_TP_RESERVED_97',
98: 'A7XX_PERF_TP_RESERVED_98',
99: 'A7XX_PERF_TP_RESERVED_99',
100: 'A7XX_PERF_TP_RESERVED_100',
101: 'A7XX_PERF_TP_RESERVED_101',
102: 'A7XX_PERF_TP_RESERVED_102',
103: 'A7XX_PERF_TP_RESERVED_103',
104: 'A7XX_PERF_TP_RESERVED_104',
105: 'A7XX_PERF_TP_RESERVED_105',
106: 'A7XX_PERF_TP_RESERVED_106',
107: 'A7XX_PERF_TP_RESERVED_107',
108: 'A7XX_PERF_TP_RESERVED_108',
109: 'A7XX_PERF_TP_RESERVED_109',
110: 'A7XX_PERF_TP_RESERVED_110',
111: 'A7XX_PERF_TP_RESERVED_111',
112: 'A7XX_PERF_TP_RESERVED_112',
113: 'A7XX_PERF_TP_RESERVED_113',
114: 'A7XX_PERF_TP_RESERVED_114',
115: 'A7XX_PERF_TP_RESERVED_115',
116: 'A7XX_PERF_TP_RESERVED_116',
117: 'A7XX_PERF_TP_RESERVED_117',
118: 'A7XX_PERF_TP_RESERVED_118',
119: 'A7XX_PERF_TP_RESERVED_119',
120: 'A7XX_PERF_TP_RESERVED_120',
121: 'A7XX_PERF_TP_RESERVED_121',
122: 'A7XX_PERF_TP_RESERVED_122',
123: 'A7XX_PERF_TP_RESERVED_123',
124: 'A7XX_PERF_TP_RESERVED_124',
125: 'A7XX_PERF_TP_RESERVED_125',
126: 'A7XX_PERF_TP_RESERVED_126',
127: 'A7XX_PERF_TP_RESERVED_127',
128: 'A7XX_PERF_TP_FORMAT_DECOMP_BILINEAR',
129: 'A7XX_PERF_TP_PACKED_POINT_BOTH_VALID_FP16',
130: 'A7XX_PERF_TP_PACKED_POINT_SINGLE_VALID_FP16',
131: 'A7XX_PERF_TP_PACKED_POINT_BOTH_VALID_FP32',
132: 'A7XX_PERF_TP_PACKED_POINT_SINGLE_VALID_FP32',
}
A7XX_PERF_TP_NEVER_COUNT = 0
A7XX_PERF_TP_BUSY_CYCLES = 1
A7XX_PERF_TP_STALL_CYCLES_UCHE = 2
A7XX_PERF_TP_LATENCY_CYCLES = 3
A7XX_PERF_TP_LATENCY_TRANS = 4
A7XX_PERF_TP_FLAG_FIFO_DELAY_SAMPLES = 5
A7XX_PERF_TP_FLAG_FIFO_DELAY_CYCLES = 6
A7XX_PERF_TP_L1_CACHELINE_REQUESTS = 7
A7XX_PERF_TP_L1_CACHELINE_MISSES = 8
A7XX_PERF_TP_SP_TP_TRANS = 9
A7XX_PERF_TP_TP_SP_TRANS = 10
A7XX_PERF_TP_OUTPUT_PIXELS = 11
A7XX_PERF_TP_FILTER_WORKLOAD_16BIT = 12
A7XX_PERF_TP_FILTER_WORKLOAD_32BIT = 13
A7XX_PERF_TP_QUADS_RECEIVED = 14
A7XX_PERF_TP_QUADS_OFFSET = 15
A7XX_PERF_TP_QUADS_SHADOW = 16
A7XX_PERF_TP_QUADS_ARRAY = 17
A7XX_PERF_TP_QUADS_GRADIENT = 18
A7XX_PERF_TP_QUADS_1D = 19
A7XX_PERF_TP_QUADS_2D = 20
A7XX_PERF_TP_QUADS_BUFFER = 21
A7XX_PERF_TP_QUADS_3D = 22
A7XX_PERF_TP_QUADS_CUBE = 23
A7XX_PERF_TP_DIVERGENT_QUADS_RECEIVED = 24
A7XX_PERF_TP_PRT_NON_RESIDENT_EVENTS = 25
A7XX_PERF_TP_OUTPUT_PIXELS_POINT = 26
A7XX_PERF_TP_OUTPUT_PIXELS_BILINEAR = 27
A7XX_PERF_TP_OUTPUT_PIXELS_MIP = 28
A7XX_PERF_TP_OUTPUT_PIXELS_ANISO = 29
A7XX_PERF_TP_OUTPUT_PIXELS_ZERO_LOD = 30
A7XX_PERF_TP_FLAG_CACHE_REQUESTS = 31
A7XX_PERF_TP_FLAG_CACHE_MISSES = 32
A7XX_PERF_TP_L1_5_L2_REQUESTS = 33
A7XX_PERF_TP_2D_OUTPUT_PIXELS = 34
A7XX_PERF_TP_2D_OUTPUT_PIXELS_POINT = 35
A7XX_PERF_TP_2D_OUTPUT_PIXELS_BILINEAR = 36
A7XX_PERF_TP_2D_FILTER_WORKLOAD_16BIT = 37
A7XX_PERF_TP_2D_FILTER_WORKLOAD_32BIT = 38
A7XX_PERF_TP_TPA2TPC_TRANS = 39
A7XX_PERF_TP_L1_MISSES_ASTC_1TILE = 40
A7XX_PERF_TP_L1_MISSES_ASTC_2TILE = 41
A7XX_PERF_TP_L1_MISSES_ASTC_4TILE = 42
A7XX_PERF_TP_L1_5_COMPRESS_REQS = 43
A7XX_PERF_TP_L1_5_L2_COMPRESS_MISS = 44
A7XX_PERF_TP_L1_BANK_CONFLICT = 45
A7XX_PERF_TP_L1_5_MISS_LATENCY_CYCLES = 46
A7XX_PERF_TP_L1_5_MISS_LATENCY_TRANS = 47
A7XX_PERF_TP_QUADS_CONSTANT_MULTIPLIED = 48
A7XX_PERF_TP_FRONTEND_WORKING_CYCLES = 49
A7XX_PERF_TP_L1_TAG_WORKING_CYCLES = 50
A7XX_PERF_TP_L1_DATA_WRITE_WORKING_CYCLES = 51
A7XX_PERF_TP_PRE_L1_DECOM_WORKING_CYCLES = 52
A7XX_PERF_TP_BACKEND_WORKING_CYCLES = 53
A7XX_PERF_TP_L1_5_CACHE_WORKING_CYCLES = 54
A7XX_PERF_TP_STARVE_CYCLES_SP = 55
A7XX_PERF_TP_STARVE_CYCLES_UCHE = 56
A7XX_PERF_TP_STALL_CYCLES_UFC = 57
A7XX_PERF_TP_FORMAT_DECOMP_POINT = 58
A7XX_PERF_TP_FILTER_POINT_FP16 = 59
A7XX_PERF_TP_FILTER_POINT_FP32 = 60
A7XX_PERF_TP_LATENCY_FIFO_FULL = 61
A7XX_PERF_TP_RESERVED_62 = 62
A7XX_PERF_TP_RESERVED_63 = 63
A7XX_PERF_TP_RESERVED_64 = 64
A7XX_PERF_TP_RESERVED_65 = 65
A7XX_PERF_TP_RESERVED_66 = 66
A7XX_PERF_TP_RESERVED_67 = 67
A7XX_PERF_TP_RESERVED_68 = 68
A7XX_PERF_TP_RESERVED_69 = 69
A7XX_PERF_TP_RESERVED_70 = 70
A7XX_PERF_TP_RESERVED_71 = 71
A7XX_PERF_TP_RESERVED_72 = 72
A7XX_PERF_TP_RESERVED_73 = 73
A7XX_PERF_TP_RESERVED_74 = 74
A7XX_PERF_TP_RESERVED_75 = 75
A7XX_PERF_TP_RESERVED_76 = 76
A7XX_PERF_TP_RESERVED_77 = 77
A7XX_PERF_TP_RESERVED_78 = 78
A7XX_PERF_TP_RESERVED_79 = 79
A7XX_PERF_TP_RESERVED_80 = 80
A7XX_PERF_TP_RESERVED_81 = 81
A7XX_PERF_TP_RESERVED_82 = 82
A7XX_PERF_TP_RESERVED_83 = 83
A7XX_PERF_TP_RESERVED_84 = 84
A7XX_PERF_TP_RESERVED_85 = 85
A7XX_PERF_TP_RESERVED_86 = 86
A7XX_PERF_TP_RESERVED_87 = 87
A7XX_PERF_TP_RESERVED_88 = 88
A7XX_PERF_TP_RESERVED_89 = 89
A7XX_PERF_TP_RESERVED_90 = 90
A7XX_PERF_TP_RESERVED_91 = 91
A7XX_PERF_TP_RESERVED_92 = 92
A7XX_PERF_TP_RESERVED_93 = 93
A7XX_PERF_TP_RESERVED_94 = 94
A7XX_PERF_TP_RESERVED_95 = 95
A7XX_PERF_TP_RESERVED_96 = 96
A7XX_PERF_TP_RESERVED_97 = 97
A7XX_PERF_TP_RESERVED_98 = 98
A7XX_PERF_TP_RESERVED_99 = 99
A7XX_PERF_TP_RESERVED_100 = 100
A7XX_PERF_TP_RESERVED_101 = 101
A7XX_PERF_TP_RESERVED_102 = 102
A7XX_PERF_TP_RESERVED_103 = 103
A7XX_PERF_TP_RESERVED_104 = 104
A7XX_PERF_TP_RESERVED_105 = 105
A7XX_PERF_TP_RESERVED_106 = 106
A7XX_PERF_TP_RESERVED_107 = 107
A7XX_PERF_TP_RESERVED_108 = 108
A7XX_PERF_TP_RESERVED_109 = 109
A7XX_PERF_TP_RESERVED_110 = 110
A7XX_PERF_TP_RESERVED_111 = 111
A7XX_PERF_TP_RESERVED_112 = 112
A7XX_PERF_TP_RESERVED_113 = 113
A7XX_PERF_TP_RESERVED_114 = 114
A7XX_PERF_TP_RESERVED_115 = 115
A7XX_PERF_TP_RESERVED_116 = 116
A7XX_PERF_TP_RESERVED_117 = 117
A7XX_PERF_TP_RESERVED_118 = 118
A7XX_PERF_TP_RESERVED_119 = 119
A7XX_PERF_TP_RESERVED_120 = 120
A7XX_PERF_TP_RESERVED_121 = 121
A7XX_PERF_TP_RESERVED_122 = 122
A7XX_PERF_TP_RESERVED_123 = 123
A7XX_PERF_TP_RESERVED_124 = 124
A7XX_PERF_TP_RESERVED_125 = 125
A7XX_PERF_TP_RESERVED_126 = 126
A7XX_PERF_TP_RESERVED_127 = 127
A7XX_PERF_TP_FORMAT_DECOMP_BILINEAR = 128
A7XX_PERF_TP_PACKED_POINT_BOTH_VALID_FP16 = 129
A7XX_PERF_TP_PACKED_POINT_SINGLE_VALID_FP16 = 130
A7XX_PERF_TP_PACKED_POINT_BOTH_VALID_FP32 = 131
A7XX_PERF_TP_PACKED_POINT_SINGLE_VALID_FP32 = 132
a7xx_tp_perfcounter_select = ctypes.c_uint32 # enum
# values for enumeration 'a7xx_sp_perfcounter_select'
a7xx_sp_perfcounter_select__enumvalues = {
0: 'A7XX_PERF_SP_NEVER_COUNT',
1: 'A7XX_PERF_SP_BUSY_CYCLES',
2: 'A7XX_PERF_SP_ALU_WORKING_CYCLES',
3: 'A7XX_PERF_SP_STALL_CYCLES_VPC_BE',
4: 'A7XX_PERF_SP_STALL_CYCLES_TP',
5: 'A7XX_PERF_SP_STALL_CYCLES_UCHE',
6: 'A7XX_PERF_SP_STALL_CYCLES_RB',
7: 'A7XX_PERF_SP_NON_EXECUTION_CYCLES',
8: 'A7XX_PERF_SP_WAVE_CONTEXTS',
9: 'A7XX_PERF_SP_WAVE_CONTEXT_CYCLES',
10: 'A7XX_PERF_SP_FS_STAGE_WAVE_CYCLES',
11: 'A7XX_PERF_SP_FS_STAGE_WAVE_SAMPLES',
12: 'A7XX_PERF_SP_VS_STAGE_WAVE_CYCLES',
13: 'A7XX_PERF_SP_VS_STAGE_WAVE_SAMPLES',
14: 'A7XX_PERF_SP_FS_STAGE_DURATION_CYCLES',
15: 'A7XX_PERF_SP_VS_STAGE_DURATION_CYCLES',
16: 'A7XX_PERF_SP_WAVE_CTRL_CYCLES',
17: 'A7XX_PERF_SP_WAVE_LOAD_CYCLES',
18: 'A7XX_PERF_SP_WAVE_EMIT_CYCLES',
19: 'A7XX_PERF_SP_WAVE_NOP_CYCLES',
20: 'A7XX_PERF_SP_WAVE_WAIT_CYCLES',
21: 'A7XX_PERF_SP_WAVE_FETCH_CYCLES',
22: 'A7XX_PERF_SP_WAVE_IDLE_CYCLES',
23: 'A7XX_PERF_SP_WAVE_END_CYCLES',
24: 'A7XX_PERF_SP_WAVE_LONG_SYNC_CYCLES',
25: 'A7XX_PERF_SP_WAVE_SHORT_SYNC_CYCLES',
26: 'A7XX_PERF_SP_WAVE_JOIN_CYCLES',
27: 'A7XX_PERF_SP_LM_LOAD_INSTRUCTIONS',
28: 'A7XX_PERF_SP_LM_STORE_INSTRUCTIONS',
29: 'A7XX_PERF_SP_LM_ATOMICS',
30: 'A7XX_PERF_SP_GM_LOAD_INSTRUCTIONS',
31: 'A7XX_PERF_SP_GM_STORE_INSTRUCTIONS',
32: 'A7XX_PERF_SP_GM_ATOMICS',
33: 'A7XX_PERF_SP_VS_STAGE_TEX_INSTRUCTIONS',
34: 'A7XX_PERF_SP_VS_STAGE_EFU_INSTRUCTIONS',
35: 'A7XX_PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS',
36: 'A7XX_PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS',
37: 'A7XX_PERF_SP_FS_STAGE_TEX_INSTRUCTIONS',
38: 'A7XX_PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS',
39: 'A7XX_PERF_SP_FS_STAGE_EFU_INSTRUCTIONS',
40: 'A7XX_PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS',
41: 'A7XX_PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS',
42: 'A7XX_PERF_SP_FS_STAGE_BARY_INSTRUCTIONS',
43: 'A7XX_PERF_SP_VS_INSTRUCTIONS',
44: 'A7XX_PERF_SP_FS_INSTRUCTIONS',
45: 'A7XX_PERF_SP_ADDR_LOCK_COUNT',
46: 'A7XX_PERF_SP_UCHE_READ_TRANS',
47: 'A7XX_PERF_SP_UCHE_WRITE_TRANS',
48: 'A7XX_PERF_SP_EXPORT_VPC_TRANS',
49: 'A7XX_PERF_SP_EXPORT_RB_TRANS',
50: 'A7XX_PERF_SP_PIXELS_KILLED',
51: 'A7XX_PERF_SP_ICL1_REQUESTS',
52: 'A7XX_PERF_SP_ICL1_MISSES',
53: 'A7XX_PERF_SP_HS_INSTRUCTIONS',
54: 'A7XX_PERF_SP_DS_INSTRUCTIONS',
55: 'A7XX_PERF_SP_GS_INSTRUCTIONS',
56: 'A7XX_PERF_SP_CS_INSTRUCTIONS',
57: 'A7XX_PERF_SP_GPR_READ',
58: 'A7XX_PERF_SP_GPR_WRITE',
59: 'A7XX_PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS',
60: 'A7XX_PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS',
61: 'A7XX_PERF_SP_LM_BANK_CONFLICTS',
62: 'A7XX_PERF_SP_TEX_CONTROL_WORKING_CYCLES',
63: 'A7XX_PERF_SP_LOAD_CONTROL_WORKING_CYCLES',
64: 'A7XX_PERF_SP_FLOW_CONTROL_WORKING_CYCLES',
65: 'A7XX_PERF_SP_LM_WORKING_CYCLES',
66: 'A7XX_PERF_SP_DISPATCHER_WORKING_CYCLES',
67: 'A7XX_PERF_SP_SEQUENCER_WORKING_CYCLES',
68: 'A7XX_PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP',
69: 'A7XX_PERF_SP_STARVE_CYCLES_HLSQ',
70: 'A7XX_PERF_SP_NON_EXECUTION_LS_CYCLES',
71: 'A7XX_PERF_SP_WORKING_EU',
72: 'A7XX_PERF_SP_ANY_EU_WORKING',
73: 'A7XX_PERF_SP_WORKING_EU_FS_STAGE',
74: 'A7XX_PERF_SP_ANY_EU_WORKING_FS_STAGE',
75: 'A7XX_PERF_SP_WORKING_EU_VS_STAGE',
76: 'A7XX_PERF_SP_ANY_EU_WORKING_VS_STAGE',
77: 'A7XX_PERF_SP_WORKING_EU_CS_STAGE',
78: 'A7XX_PERF_SP_ANY_EU_WORKING_CS_STAGE',
79: 'A7XX_PERF_SP_GPR_READ_PREFETCH',
80: 'A7XX_PERF_SP_GPR_READ_CONFLICT',
81: 'A7XX_PERF_SP_GPR_WRITE_CONFLICT',
82: 'A7XX_PERF_SP_GM_LOAD_LATENCY_CYCLES',
83: 'A7XX_PERF_SP_GM_LOAD_LATENCY_SAMPLES',
84: 'A7XX_PERF_SP_EXECUTABLE_WAVES',
85: 'A7XX_PERF_SP_ICL1_MISS_FETCH_CYCLES',
86: 'A7XX_PERF_SP_RESERVED_86',
87: 'A7XX_PERF_SP_BYPASS_BUSY_CYCLES',
88: 'A7XX_PERF_SP_ANY_EU_WORKING_LPAC',
89: 'A7XX_PERF_SP_WAVE_ALU_CYCLES',
90: 'A7XX_PERF_SP_WAVE_EFU_CYCLES',
91: 'A7XX_PERF_SP_WAVE_INT_CYCLES',
92: 'A7XX_PERF_SP_WAVE_CSP_CYCLES',
93: 'A7XX_PERF_SP_EWAVE_CONTEXTS',
94: 'A7XX_PERF_SP_EWAVE_CONTEXT_CYCLES',
95: 'A7XX_PERF_SP_LPAC_BUSY_CYCLES',
96: 'A7XX_PERF_SP_LPAC_INSTRUCTIONS',
97: 'A7XX_PERF_SP_FS_STAGE_1X_WAVES',
98: 'A7XX_PERF_SP_FS_STAGE_2X_WAVES',
99: 'A7XX_PERF_SP_QUADS',
100: 'A7XX_PERF_SP_CS_INVOCATIONS',
101: 'A7XX_PERF_SP_PIXELS',
102: 'A7XX_PERF_SP_LPAC_DRAWCALLS',
103: 'A7XX_PERF_SP_PI_WORKING_CYCLES',
104: 'A7XX_PERF_SP_WAVE_INPUT_CYCLES',
105: 'A7XX_PERF_SP_WAVE_OUTPUT_CYCLES',
106: 'A7XX_PERF_SP_WAVE_HWAVE_WAIT_CYCLES',
107: 'A7XX_PERF_SP_WAVE_HWAVE_SYNC',
108: 'A7XX_PERF_SP_OUTPUT_3D_PIXELS',
109: 'A7XX_PERF_SP_FULL_ALU_MAD_INSTRUCTIONS',
110: 'A7XX_PERF_SP_HALF_ALU_MAD_INSTRUCTIONS',
111: 'A7XX_PERF_SP_FULL_ALU_MUL_INSTRUCTIONS',
112: 'A7XX_PERF_SP_HALF_ALU_MUL_INSTRUCTIONS',
113: 'A7XX_PERF_SP_FULL_ALU_ADD_INSTRUCTIONS',
114: 'A7XX_PERF_SP_HALF_ALU_ADD_INSTRUCTIONS',
115: 'A7XX_PERF_SP_BARY_FP32_INSTRUCTIONS',
116: 'A7XX_PERF_SP_ALU_GPR_READ_CYCLES',
117: 'A7XX_PERF_SP_ALU_DATA_FORWARDING_CYCLES',
118: 'A7XX_PERF_SP_LM_FULL_CYCLES',
119: 'A7XX_PERF_SP_TEXTURE_FETCH_LATENCY_CYCLES',
120: 'A7XX_PERF_SP_TEXTURE_FETCH_LATENCY_SAMPLES',
121: 'A7XX_PERF_SP_FS_STAGE_PI_TEX_INSTRUCTION',
122: 'A7XX_PERF_SP_RAY_QUERY_INSTRUCTIONS',
123: 'A7XX_PERF_SP_RBRT_KICKOFF_FIBERS',
124: 'A7XX_PERF_SP_RBRT_KICKOFF_DQUADS',
125: 'A7XX_PERF_SP_RTU_BUSY_CYCLES',
126: 'A7XX_PERF_SP_RTU_L0_HITS',
127: 'A7XX_PERF_SP_RTU_L0_MISSES',
128: 'A7XX_PERF_SP_RTU_L0_HIT_ON_MISS',
129: 'A7XX_PERF_SP_RTU_STALL_CYCLES_WAVE_QUEUE',
130: 'A7XX_PERF_SP_RTU_STALL_CYCLES_L0_HIT_QUEUE',
131: 'A7XX_PERF_SP_RTU_STALL_CYCLES_L0_MISS_QUEUE',
132: 'A7XX_PERF_SP_RTU_STALL_CYCLES_L0D_IDX_QUEUE',
133: 'A7XX_PERF_SP_RTU_STALL_CYCLES_L0DATA',
134: 'A7XX_PERF_SP_RTU_STALL_CYCLES_REPLACE_CNT',
135: 'A7XX_PERF_SP_RTU_STALL_CYCLES_MRG_CNT',
136: 'A7XX_PERF_SP_RTU_STALL_CYCLES_UCHE',
137: 'A7XX_PERF_SP_RTU_OPERAND_FETCH_STALL_CYCLES_L0',
138: 'A7XX_PERF_SP_RTU_OPERAND_FETCH_STALL_CYCLES_INS_FIFO',
139: 'A7XX_PERF_SP_RTU_BVH_FETCH_LATENCY_CYCLES',
140: 'A7XX_PERF_SP_RTU_BVH_FETCH_LATENCY_SAMPLES',
141: 'A7XX_PERF_SP_STCHE_MISS_INC_VS',
142: 'A7XX_PERF_SP_STCHE_MISS_INC_FS',
143: 'A7XX_PERF_SP_STCHE_MISS_INC_BV',
144: 'A7XX_PERF_SP_STCHE_MISS_INC_LPAC',
145: 'A7XX_PERF_SP_VGPR_ACTIVE_CONTEXTS',
146: 'A7XX_PERF_SP_PGPR_ALLOC_CONTEXTS',
147: 'A7XX_PERF_SP_VGPR_ALLOC_CONTEXTS',
148: 'A7XX_PERF_SP_RTU_RAY_BOX_INTERSECTIONS',
149: 'A7XX_PERF_SP_RTU_RAY_TRIANGLE_INTERSECTIONS',
150: 'A7XX_PERF_SP_SCH_STALL_CYCLES_RTU',
151: 'A7XX_PERF_SP_EFU_WORKING_CYCLES',
152: 'A7XX_PERF_SP_BRANCH_TAKEN',
153: 'A7XX_PERF_SP_BRANCH_NOT_TAKEN',
154: 'A7XX_PERF_SP_BRANCH_INS_DIVERGENCY_COUNT',
155: 'A7XX_PERF_SP_BRANCH_INS_COUNT',
156: 'A7XX_PERF_SP_PREDICT_TAKEN',
157: 'A7XX_PERF_SP_PREDICT_NOT_TAKEN',
158: 'A7XX_PERF_SP_PREDICT_INS_DIVERGENCY_COUNT',
159: 'A7XX_PERF_SP_PREDICT_INS_COUNT',
160: 'A7XX_PERF_SP_CCHE_UAV_TOTAL_REQ',
161: 'A7XX_PERF_SP_CCHE_UAV_TOTAL_DUALQUAD',
162: 'A7XX_PERF_SP_CCHE_NONUAV_TOTAL_REQ',
163: 'A7XX_PERF_SP_CCHE_NONUAV_TOTAL_DUALQUAD',
164: 'A7XX_PERF_SP_LB_NONUAV_TOTAL_REQ',
165: 'A7XX_PERF_SP_LB_NONUAV_TOTAL_DUALQUAD',
166: 'A7XX_PERF_SP_LB_READ_XFER_ALU',
167: 'A7XX_PERF_SP_LB_ALU_READ_CONS',
168: 'A7XX_PERF_SP_LB_READ_ALU_BLOCK_OTHER',
169: 'A7XX_PERF_SP_LB_WRITE_XFER_VPC',
170: 'A7XX_PERF_SP_LB_WRITE_VPC_BLOCK_OTHER',
171: 'A7XX_PERF_SP_LB_LDST_RW_LM',
172: 'A7XX_PERF_SP_LB_LDST_RW_LM_BLOCKED',
173: 'A7XX_PERF_SP_LB_LDST_WRITE_CONS',
174: 'A7XX_PERF_SP_LB_LDST_WRITE_CONS_BLOCKED',
175: 'A7XX_PERF_SP_GPR_READ_BANK',
176: 'A7XX_PERF_SP_GPR_WRITE_BANK',
177: 'A7XX_PERF_SP_VS_WAVE_REQ_PENDING',
178: 'A7XX_PERF_SP_FS_WAVE_REQ_PENDING',
179: 'A7XX_PERF_SP_LPAC_WAVE_REQ_PENDING',
180: 'A7XX_PERF_SP_WAVE_SPLIT_CNT',
181: 'A7XX_PERF_SP_FS_OOO_WAVE_ACC',
}
A7XX_PERF_SP_NEVER_COUNT = 0
A7XX_PERF_SP_BUSY_CYCLES = 1
A7XX_PERF_SP_ALU_WORKING_CYCLES = 2
A7XX_PERF_SP_STALL_CYCLES_VPC_BE = 3
A7XX_PERF_SP_STALL_CYCLES_TP = 4
A7XX_PERF_SP_STALL_CYCLES_UCHE = 5
A7XX_PERF_SP_STALL_CYCLES_RB = 6
A7XX_PERF_SP_NON_EXECUTION_CYCLES = 7
A7XX_PERF_SP_WAVE_CONTEXTS = 8
A7XX_PERF_SP_WAVE_CONTEXT_CYCLES = 9
A7XX_PERF_SP_FS_STAGE_WAVE_CYCLES = 10
A7XX_PERF_SP_FS_STAGE_WAVE_SAMPLES = 11
A7XX_PERF_SP_VS_STAGE_WAVE_CYCLES = 12
A7XX_PERF_SP_VS_STAGE_WAVE_SAMPLES = 13
A7XX_PERF_SP_FS_STAGE_DURATION_CYCLES = 14
A7XX_PERF_SP_VS_STAGE_DURATION_CYCLES = 15
A7XX_PERF_SP_WAVE_CTRL_CYCLES = 16
A7XX_PERF_SP_WAVE_LOAD_CYCLES = 17
A7XX_PERF_SP_WAVE_EMIT_CYCLES = 18
A7XX_PERF_SP_WAVE_NOP_CYCLES = 19
A7XX_PERF_SP_WAVE_WAIT_CYCLES = 20
A7XX_PERF_SP_WAVE_FETCH_CYCLES = 21
A7XX_PERF_SP_WAVE_IDLE_CYCLES = 22
A7XX_PERF_SP_WAVE_END_CYCLES = 23
A7XX_PERF_SP_WAVE_LONG_SYNC_CYCLES = 24
A7XX_PERF_SP_WAVE_SHORT_SYNC_CYCLES = 25
A7XX_PERF_SP_WAVE_JOIN_CYCLES = 26
A7XX_PERF_SP_LM_LOAD_INSTRUCTIONS = 27
A7XX_PERF_SP_LM_STORE_INSTRUCTIONS = 28
A7XX_PERF_SP_LM_ATOMICS = 29
A7XX_PERF_SP_GM_LOAD_INSTRUCTIONS = 30
A7XX_PERF_SP_GM_STORE_INSTRUCTIONS = 31
A7XX_PERF_SP_GM_ATOMICS = 32
A7XX_PERF_SP_VS_STAGE_TEX_INSTRUCTIONS = 33
A7XX_PERF_SP_VS_STAGE_EFU_INSTRUCTIONS = 34
A7XX_PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS = 35
A7XX_PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS = 36
A7XX_PERF_SP_FS_STAGE_TEX_INSTRUCTIONS = 37
A7XX_PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS = 38
A7XX_PERF_SP_FS_STAGE_EFU_INSTRUCTIONS = 39
A7XX_PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS = 40
A7XX_PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS = 41
A7XX_PERF_SP_FS_STAGE_BARY_INSTRUCTIONS = 42
A7XX_PERF_SP_VS_INSTRUCTIONS = 43
A7XX_PERF_SP_FS_INSTRUCTIONS = 44
A7XX_PERF_SP_ADDR_LOCK_COUNT = 45
A7XX_PERF_SP_UCHE_READ_TRANS = 46
A7XX_PERF_SP_UCHE_WRITE_TRANS = 47
A7XX_PERF_SP_EXPORT_VPC_TRANS = 48
A7XX_PERF_SP_EXPORT_RB_TRANS = 49
A7XX_PERF_SP_PIXELS_KILLED = 50
A7XX_PERF_SP_ICL1_REQUESTS = 51
A7XX_PERF_SP_ICL1_MISSES = 52
A7XX_PERF_SP_HS_INSTRUCTIONS = 53
A7XX_PERF_SP_DS_INSTRUCTIONS = 54
A7XX_PERF_SP_GS_INSTRUCTIONS = 55
A7XX_PERF_SP_CS_INSTRUCTIONS = 56
A7XX_PERF_SP_GPR_READ = 57
A7XX_PERF_SP_GPR_WRITE = 58
A7XX_PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS = 59
A7XX_PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS = 60
A7XX_PERF_SP_LM_BANK_CONFLICTS = 61
A7XX_PERF_SP_TEX_CONTROL_WORKING_CYCLES = 62
A7XX_PERF_SP_LOAD_CONTROL_WORKING_CYCLES = 63
A7XX_PERF_SP_FLOW_CONTROL_WORKING_CYCLES = 64
A7XX_PERF_SP_LM_WORKING_CYCLES = 65
A7XX_PERF_SP_DISPATCHER_WORKING_CYCLES = 66
A7XX_PERF_SP_SEQUENCER_WORKING_CYCLES = 67
A7XX_PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP = 68
A7XX_PERF_SP_STARVE_CYCLES_HLSQ = 69
A7XX_PERF_SP_NON_EXECUTION_LS_CYCLES = 70
A7XX_PERF_SP_WORKING_EU = 71
A7XX_PERF_SP_ANY_EU_WORKING = 72
A7XX_PERF_SP_WORKING_EU_FS_STAGE = 73
A7XX_PERF_SP_ANY_EU_WORKING_FS_STAGE = 74
A7XX_PERF_SP_WORKING_EU_VS_STAGE = 75
A7XX_PERF_SP_ANY_EU_WORKING_VS_STAGE = 76
A7XX_PERF_SP_WORKING_EU_CS_STAGE = 77
A7XX_PERF_SP_ANY_EU_WORKING_CS_STAGE = 78
A7XX_PERF_SP_GPR_READ_PREFETCH = 79
A7XX_PERF_SP_GPR_READ_CONFLICT = 80
A7XX_PERF_SP_GPR_WRITE_CONFLICT = 81
A7XX_PERF_SP_GM_LOAD_LATENCY_CYCLES = 82
A7XX_PERF_SP_GM_LOAD_LATENCY_SAMPLES = 83
A7XX_PERF_SP_EXECUTABLE_WAVES = 84
A7XX_PERF_SP_ICL1_MISS_FETCH_CYCLES = 85
A7XX_PERF_SP_RESERVED_86 = 86
A7XX_PERF_SP_BYPASS_BUSY_CYCLES = 87
A7XX_PERF_SP_ANY_EU_WORKING_LPAC = 88
A7XX_PERF_SP_WAVE_ALU_CYCLES = 89
A7XX_PERF_SP_WAVE_EFU_CYCLES = 90
A7XX_PERF_SP_WAVE_INT_CYCLES = 91
A7XX_PERF_SP_WAVE_CSP_CYCLES = 92
A7XX_PERF_SP_EWAVE_CONTEXTS = 93
A7XX_PERF_SP_EWAVE_CONTEXT_CYCLES = 94
A7XX_PERF_SP_LPAC_BUSY_CYCLES = 95
A7XX_PERF_SP_LPAC_INSTRUCTIONS = 96
A7XX_PERF_SP_FS_STAGE_1X_WAVES = 97
A7XX_PERF_SP_FS_STAGE_2X_WAVES = 98
A7XX_PERF_SP_QUADS = 99
A7XX_PERF_SP_CS_INVOCATIONS = 100
A7XX_PERF_SP_PIXELS = 101
A7XX_PERF_SP_LPAC_DRAWCALLS = 102
A7XX_PERF_SP_PI_WORKING_CYCLES = 103
A7XX_PERF_SP_WAVE_INPUT_CYCLES = 104
A7XX_PERF_SP_WAVE_OUTPUT_CYCLES = 105
A7XX_PERF_SP_WAVE_HWAVE_WAIT_CYCLES = 106
A7XX_PERF_SP_WAVE_HWAVE_SYNC = 107
A7XX_PERF_SP_OUTPUT_3D_PIXELS = 108
A7XX_PERF_SP_FULL_ALU_MAD_INSTRUCTIONS = 109
A7XX_PERF_SP_HALF_ALU_MAD_INSTRUCTIONS = 110
A7XX_PERF_SP_FULL_ALU_MUL_INSTRUCTIONS = 111
A7XX_PERF_SP_HALF_ALU_MUL_INSTRUCTIONS = 112
A7XX_PERF_SP_FULL_ALU_ADD_INSTRUCTIONS = 113
A7XX_PERF_SP_HALF_ALU_ADD_INSTRUCTIONS = 114
A7XX_PERF_SP_BARY_FP32_INSTRUCTIONS = 115
A7XX_PERF_SP_ALU_GPR_READ_CYCLES = 116
A7XX_PERF_SP_ALU_DATA_FORWARDING_CYCLES = 117
A7XX_PERF_SP_LM_FULL_CYCLES = 118
A7XX_PERF_SP_TEXTURE_FETCH_LATENCY_CYCLES = 119
A7XX_PERF_SP_TEXTURE_FETCH_LATENCY_SAMPLES = 120
A7XX_PERF_SP_FS_STAGE_PI_TEX_INSTRUCTION = 121
A7XX_PERF_SP_RAY_QUERY_INSTRUCTIONS = 122
A7XX_PERF_SP_RBRT_KICKOFF_FIBERS = 123
A7XX_PERF_SP_RBRT_KICKOFF_DQUADS = 124
A7XX_PERF_SP_RTU_BUSY_CYCLES = 125
A7XX_PERF_SP_RTU_L0_HITS = 126
A7XX_PERF_SP_RTU_L0_MISSES = 127
A7XX_PERF_SP_RTU_L0_HIT_ON_MISS = 128
A7XX_PERF_SP_RTU_STALL_CYCLES_WAVE_QUEUE = 129
A7XX_PERF_SP_RTU_STALL_CYCLES_L0_HIT_QUEUE = 130
A7XX_PERF_SP_RTU_STALL_CYCLES_L0_MISS_QUEUE = 131
A7XX_PERF_SP_RTU_STALL_CYCLES_L0D_IDX_QUEUE = 132
A7XX_PERF_SP_RTU_STALL_CYCLES_L0DATA = 133
A7XX_PERF_SP_RTU_STALL_CYCLES_REPLACE_CNT = 134
A7XX_PERF_SP_RTU_STALL_CYCLES_MRG_CNT = 135
A7XX_PERF_SP_RTU_STALL_CYCLES_UCHE = 136
A7XX_PERF_SP_RTU_OPERAND_FETCH_STALL_CYCLES_L0 = 137
A7XX_PERF_SP_RTU_OPERAND_FETCH_STALL_CYCLES_INS_FIFO = 138
A7XX_PERF_SP_RTU_BVH_FETCH_LATENCY_CYCLES = 139
A7XX_PERF_SP_RTU_BVH_FETCH_LATENCY_SAMPLES = 140
A7XX_PERF_SP_STCHE_MISS_INC_VS = 141
A7XX_PERF_SP_STCHE_MISS_INC_FS = 142
A7XX_PERF_SP_STCHE_MISS_INC_BV = 143
A7XX_PERF_SP_STCHE_MISS_INC_LPAC = 144
A7XX_PERF_SP_VGPR_ACTIVE_CONTEXTS = 145
A7XX_PERF_SP_PGPR_ALLOC_CONTEXTS = 146
A7XX_PERF_SP_VGPR_ALLOC_CONTEXTS = 147
A7XX_PERF_SP_RTU_RAY_BOX_INTERSECTIONS = 148
A7XX_PERF_SP_RTU_RAY_TRIANGLE_INTERSECTIONS = 149
A7XX_PERF_SP_SCH_STALL_CYCLES_RTU = 150
A7XX_PERF_SP_EFU_WORKING_CYCLES = 151
A7XX_PERF_SP_BRANCH_TAKEN = 152
A7XX_PERF_SP_BRANCH_NOT_TAKEN = 153
A7XX_PERF_SP_BRANCH_INS_DIVERGENCY_COUNT = 154
A7XX_PERF_SP_BRANCH_INS_COUNT = 155
A7XX_PERF_SP_PREDICT_TAKEN = 156
A7XX_PERF_SP_PREDICT_NOT_TAKEN = 157
A7XX_PERF_SP_PREDICT_INS_DIVERGENCY_COUNT = 158
A7XX_PERF_SP_PREDICT_INS_COUNT = 159
A7XX_PERF_SP_CCHE_UAV_TOTAL_REQ = 160
A7XX_PERF_SP_CCHE_UAV_TOTAL_DUALQUAD = 161
A7XX_PERF_SP_CCHE_NONUAV_TOTAL_REQ = 162
A7XX_PERF_SP_CCHE_NONUAV_TOTAL_DUALQUAD = 163
A7XX_PERF_SP_LB_NONUAV_TOTAL_REQ = 164
A7XX_PERF_SP_LB_NONUAV_TOTAL_DUALQUAD = 165
A7XX_PERF_SP_LB_READ_XFER_ALU = 166
A7XX_PERF_SP_LB_ALU_READ_CONS = 167
A7XX_PERF_SP_LB_READ_ALU_BLOCK_OTHER = 168
A7XX_PERF_SP_LB_WRITE_XFER_VPC = 169
A7XX_PERF_SP_LB_WRITE_VPC_BLOCK_OTHER = 170
A7XX_PERF_SP_LB_LDST_RW_LM = 171
A7XX_PERF_SP_LB_LDST_RW_LM_BLOCKED = 172
A7XX_PERF_SP_LB_LDST_WRITE_CONS = 173
A7XX_PERF_SP_LB_LDST_WRITE_CONS_BLOCKED = 174
A7XX_PERF_SP_GPR_READ_BANK = 175
A7XX_PERF_SP_GPR_WRITE_BANK = 176
A7XX_PERF_SP_VS_WAVE_REQ_PENDING = 177
A7XX_PERF_SP_FS_WAVE_REQ_PENDING = 178
A7XX_PERF_SP_LPAC_WAVE_REQ_PENDING = 179
A7XX_PERF_SP_WAVE_SPLIT_CNT = 180
A7XX_PERF_SP_FS_OOO_WAVE_ACC = 181
a7xx_sp_perfcounter_select = ctypes.c_uint32 # enum
# values for enumeration 'a7xx_rb_perfcounter_select'
a7xx_rb_perfcounter_select__enumvalues = {
0: 'A7XX_PERF_RB_NEVER_COUNT',
1: 'A7XX_PERF_RB_BUSY_CYCLES',
2: 'A7XX_PERF_RB_STALL_CYCLES_HLSQ',
3: 'A7XX_PERF_RB_STALL_CYCLES_FIFO0_FULL',
4: 'A7XX_PERF_RB_STALL_CYCLES_FIFO1_FULL',
5: 'A7XX_PERF_RB_STALL_CYCLES_FIFO2_FULL',
6: 'A7XX_PERF_RB_STARVE_CYCLES_SP',
7: 'A7XX_PERF_RB_STARVE_CYCLES_LRZ_TILE',
8: 'A7XX_PERF_RB_STARVE_CYCLES_CCU',
9: 'A7XX_PERF_RB_STARVE_CYCLES_Z_PLANE',
10: 'A7XX_PERF_RB_STARVE_CYCLES_BARY_PLANE',
11: 'A7XX_PERF_RB_Z_WORKLOAD',
12: 'A7XX_PERF_RB_HLSQ_ACTIVE',
13: 'A7XX_PERF_RB_Z_READ',
14: 'A7XX_PERF_RB_Z_WRITE',
15: 'A7XX_PERF_RB_C_READ',
16: 'A7XX_PERF_RB_C_WRITE',
17: 'A7XX_PERF_RB_TOTAL_PASS',
18: 'A7XX_PERF_RB_Z_PASS',
19: 'A7XX_PERF_RB_Z_FAIL',
20: 'A7XX_PERF_RB_S_FAIL',
21: 'A7XX_PERF_RB_BLENDED_FXP_COMPONENTS',
22: 'A7XX_PERF_RB_BLENDED_FP16_COMPONENTS',
23: 'A7XX_PERF_RB_PS_INVOCATIONS',
24: 'A7XX_PERF_RB_2D_ALIVE_CYCLES',
25: 'A7XX_PERF_RB_2D_STARVE_CYCLES_SP',
26: 'A7XX_PERF_RB_2D_VALID_PIXELS',
27: 'A7XX_PERF_RB_3D_PIXELS',
28: 'A7XX_PERF_RB_BLENDER_WORKING_CYCLES',
29: 'A7XX_PERF_RB_ZPROC_WORKING_CYCLES',
30: 'A7XX_PERF_RB_CPROC_WORKING_CYCLES',
31: 'A7XX_PERF_RB_SAMPLER_WORKING_CYCLES',
32: 'A7XX_PERF_RB_STALL_CYCLES_CCU_COLOR_READ',
33: 'A7XX_PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE',
34: 'A7XX_PERF_RB_STALL_CYCLES_CCU_DEPTH_READ',
35: 'A7XX_PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE',
36: 'A7XX_PERF_RB_STALL_CYCLES_VPC_BE',
37: 'A7XX_PERF_RB_BLENDED_FP32_COMPONENTS',
38: 'A7XX_PERF_RB_COLOR_PIX_TILES',
39: 'A7XX_PERF_RB_STALL_CYCLES_CCU',
40: 'A7XX_PERF_RB_EARLY_Z_ARB3_GRANT',
41: 'A7XX_PERF_RB_LATE_Z_ARB3_GRANT',
42: 'A7XX_PERF_RB_EARLY_Z_SKIP_GRANT',
43: 'A7XX_PERF_RB_VRS_1X1_QUADS',
44: 'A7XX_PERF_RB_VRS_2X1_QUADS',
45: 'A7XX_PERF_RB_VRS_1X2_QUADS',
46: 'A7XX_PERF_RB_VRS_2X2_QUADS',
47: 'A7XX_PERF_RB_VRS_2X4_QUADS',
48: 'A7XX_PERF_RB_VRS_4X2_QUADS',
49: 'A7XX_PERF_RB_VRS_4X4_QUADS',
}
A7XX_PERF_RB_NEVER_COUNT = 0
A7XX_PERF_RB_BUSY_CYCLES = 1
A7XX_PERF_RB_STALL_CYCLES_HLSQ = 2
A7XX_PERF_RB_STALL_CYCLES_FIFO0_FULL = 3
A7XX_PERF_RB_STALL_CYCLES_FIFO1_FULL = 4
A7XX_PERF_RB_STALL_CYCLES_FIFO2_FULL = 5
A7XX_PERF_RB_STARVE_CYCLES_SP = 6
A7XX_PERF_RB_STARVE_CYCLES_LRZ_TILE = 7
A7XX_PERF_RB_STARVE_CYCLES_CCU = 8
A7XX_PERF_RB_STARVE_CYCLES_Z_PLANE = 9
A7XX_PERF_RB_STARVE_CYCLES_BARY_PLANE = 10
A7XX_PERF_RB_Z_WORKLOAD = 11
A7XX_PERF_RB_HLSQ_ACTIVE = 12
A7XX_PERF_RB_Z_READ = 13
A7XX_PERF_RB_Z_WRITE = 14
A7XX_PERF_RB_C_READ = 15
A7XX_PERF_RB_C_WRITE = 16
A7XX_PERF_RB_TOTAL_PASS = 17
A7XX_PERF_RB_Z_PASS = 18
A7XX_PERF_RB_Z_FAIL = 19
A7XX_PERF_RB_S_FAIL = 20
A7XX_PERF_RB_BLENDED_FXP_COMPONENTS = 21
A7XX_PERF_RB_BLENDED_FP16_COMPONENTS = 22
A7XX_PERF_RB_PS_INVOCATIONS = 23
A7XX_PERF_RB_2D_ALIVE_CYCLES = 24
A7XX_PERF_RB_2D_STARVE_CYCLES_SP = 25
A7XX_PERF_RB_2D_VALID_PIXELS = 26
A7XX_PERF_RB_3D_PIXELS = 27
A7XX_PERF_RB_BLENDER_WORKING_CYCLES = 28
A7XX_PERF_RB_ZPROC_WORKING_CYCLES = 29
A7XX_PERF_RB_CPROC_WORKING_CYCLES = 30
A7XX_PERF_RB_SAMPLER_WORKING_CYCLES = 31
A7XX_PERF_RB_STALL_CYCLES_CCU_COLOR_READ = 32
A7XX_PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE = 33
A7XX_PERF_RB_STALL_CYCLES_CCU_DEPTH_READ = 34
A7XX_PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE = 35
A7XX_PERF_RB_STALL_CYCLES_VPC_BE = 36
A7XX_PERF_RB_BLENDED_FP32_COMPONENTS = 37
A7XX_PERF_RB_COLOR_PIX_TILES = 38
A7XX_PERF_RB_STALL_CYCLES_CCU = 39
A7XX_PERF_RB_EARLY_Z_ARB3_GRANT = 40
A7XX_PERF_RB_LATE_Z_ARB3_GRANT = 41
A7XX_PERF_RB_EARLY_Z_SKIP_GRANT = 42
A7XX_PERF_RB_VRS_1X1_QUADS = 43
A7XX_PERF_RB_VRS_2X1_QUADS = 44
A7XX_PERF_RB_VRS_1X2_QUADS = 45
A7XX_PERF_RB_VRS_2X2_QUADS = 46
A7XX_PERF_RB_VRS_2X4_QUADS = 47
A7XX_PERF_RB_VRS_4X2_QUADS = 48
A7XX_PERF_RB_VRS_4X4_QUADS = 49
a7xx_rb_perfcounter_select = ctypes.c_uint32 # enum
# values for enumeration 'a7xx_vsc_perfcounter_select'
a7xx_vsc_perfcounter_select__enumvalues = {
0: 'A7XX_PERF_VSC_NEVER_COUNT',
1: 'A7XX_PERF_VSC_BUSY_CYCLES',
2: 'A7XX_PERF_VSC_WORKING_CYCLES',
3: 'A7XX_PERF_VSC_STALL_CYCLES_UCHE',
4: 'A7XX_PERF_VSC_EOT_NUM',
5: 'A7XX_PERF_VSC_INPUT_TILES',
6: 'A7XX_PERF_VSC_TILE_COMP_TRAN',
7: 'A7XX_PERF_VSC_TILE_BYPASS_TRAN',
}
A7XX_PERF_VSC_NEVER_COUNT = 0
A7XX_PERF_VSC_BUSY_CYCLES = 1
A7XX_PERF_VSC_WORKING_CYCLES = 2
A7XX_PERF_VSC_STALL_CYCLES_UCHE = 3
A7XX_PERF_VSC_EOT_NUM = 4
A7XX_PERF_VSC_INPUT_TILES = 5
A7XX_PERF_VSC_TILE_COMP_TRAN = 6
A7XX_PERF_VSC_TILE_BYPASS_TRAN = 7
a7xx_vsc_perfcounter_select = ctypes.c_uint32 # enum
# values for enumeration 'a7xx_ccu_perfcounter_select'
a7xx_ccu_perfcounter_select__enumvalues = {
0: 'A7XX_PERF_CCU_NEVER_COUNT',
1: 'A7XX_PERF_CCU_BUSY_CYCLES',
2: 'A7XX_PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN',
3: 'A7XX_PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN',
4: 'A7XX_PERF_CCU_DEPTH_BLOCKS',
5: 'A7XX_PERF_CCU_COLOR_BLOCKS',
6: 'A7XX_PERF_CCU_DEPTH_BLOCK_HIT',
7: 'A7XX_PERF_CCU_COLOR_BLOCK_HIT',
8: 'A7XX_PERF_CCU_PARTIAL_BLOCK_READ',
9: 'A7XX_PERF_CCU_GMEM_READ',
10: 'A7XX_PERF_CCU_GMEM_WRITE',
11: 'A7XX_PERF_CCU_2D_RD_REQ',
12: 'A7XX_PERF_CCU_2D_WR_REQ',
13: 'A7XX_PERF_CCU_UBWC_COLOR_BLOCKS_CONCURRENT',
14: 'A7XX_PERF_CCU_UBWC_DEPTH_BLOCKS_CONCURRENT',
15: 'A7XX_PERF_CCU_COLOR_RESOLVE_DROPPED',
16: 'A7XX_PERF_CCU_DEPTH_RESOLVE_DROPPED',
17: 'A7XX_PERF_CCU_COLOR_RENDER_CONCURRENT',
18: 'A7XX_PERF_CCU_DEPTH_RENDER_CONCURRENT',
19: 'A7XX_PERF_CCU_COLOR_RESOLVE_AFTER_RENDER',
20: 'A7XX_PERF_CCU_DEPTH_RESOLVE_AFTER_RENDER',
21: 'A7XX_PERF_CCU_GMEM_EXTRA_DEPTH_READ',
22: 'A7XX_PERF_CCU_GMEM_COLOR_READ_4AA',
23: 'A7XX_PERF_CCU_GMEM_COLOR_READ_4AA_FULL',
24: 'A7XX_PERF_CCU_COLOR_EVB_STALL',
25: 'A7XX_PERF_CCU_RENDER_OVERLAP_CRE_C',
26: 'A7XX_PERF_CCU_RENDER_OVERLAP_CRE_Z',
27: 'A7XX_PERF_CCU_RENDER_STALL_BY_CRE_C',
28: 'A7XX_PERF_CCU_RENDER_STALL_BY_CRE_Z',
29: 'A7XX_PERF_CCU_FULL_SURFACE_RESOLVE_CYCLES',
30: 'A7XX_PERF_CCU_RENDER_OVERLAP_FULL_SURFACE_RESOLVE',
31: 'A7XX_PERF_CCU_STALL_BY_FULL_SURFACE_RESOLVE',
32: 'A7XX_PERF_CCU_RESERVED_32',
33: 'A7XX_PERF_CCU_RESERVED_33',
34: 'A7XX_PERF_CCU_RESERVED_34',
35: 'A7XX_PERF_CCU_RESERVED_35',
36: 'A7XX_PERF_CCU_RESERVED_36',
37: 'A7XX_PERF_CCU_RESERVED_37',
38: 'A7XX_PERF_CCU_RESERVED_38',
39: 'A7XX_PERF_CCU_RESERVED_39',
40: 'A7XX_PERF_CCU_RESERVED_40',
41: 'A7XX_PERF_CCU_RESERVED_41',
42: 'A7XX_PERF_CCU_RESERVED_42',
43: 'A7XX_PERF_CCU_RESERVED_43',
44: 'A7XX_PERF_CCU_RESERVED_44',
45: 'A7XX_PERF_CCU_RESERVED_45',
46: 'A7XX_PERF_CCU_RESERVED_46',
47: 'A7XX_PERF_CCU_RESERVED_47',
48: 'A7XX_PERF_CCU_RESERVED_48',
49: 'A7XX_PERF_CCU_RESERVED_49',
50: 'A7XX_PERF_CCU_RESERVED_50',
51: 'A7XX_PERF_CCU_RESERVED_51',
52: 'A7XX_PERF_CCU_RESERVED_52',
53: 'A7XX_PERF_CCU_RESERVED_53',
54: 'A7XX_PERF_CCU_RESERVED_54',
55: 'A7XX_PERF_CCU_RESERVED_55',
56: 'A7XX_PERF_CCU_RESERVED_56',
57: 'A7XX_PERF_CCU_RESERVED_57',
58: 'A7XX_PERF_CCU_RESERVED_58',
59: 'A7XX_PERF_CCU_RESERVED_59',
60: 'A7XX_PERF_CCU_RESERVED_60',
61: 'A7XX_PERF_CCU_RESERVED_61',
62: 'A7XX_PERF_CCU_RESERVED_62',
63: 'A7XX_PERF_CCU_RESERVED_63',
64: 'A7XX_PERF_UFC_L0_TP_HINT_REQUESTS',
65: 'A7XX_PERF_UFC_L0_TP_HINT_TAG_MISS',
66: 'A7XX_PERF_UFC_L0_TP_HINT_TAG_HIT_RDY',
67: 'A7XX_PERF_UFC_L0_TP_HINT_TAG_HIT_NRDY',
68: 'A7XX_PERF_UFC_L0_TP_HINT_IS_FCLEAR',
69: 'A7XX_PERF_UFC_L0_TP_HINT_IS_ALPHA0',
70: 'A7XX_PERF_UFC_L0_TP_HINT_IS_ALPHA1',
71: 'A7XX_PERF_UFC_L0_TP_HINT_IS_UNCOMP',
72: 'A7XX_PERF_UFC_L0_SP_REQUESTS',
73: 'A7XX_PERF_UFC_L0_SP_FILTER_HIT',
74: 'A7XX_PERF_UFC_L0_SP_FILTER_MISS',
75: 'A7XX_PERF_UFC_L0_SP_REQ_STALLED_CYCLES',
76: 'A7XX_PERF_UFC_L0_TP_REQ_STALLED_CYCLES',
77: 'A7XX_PERF_UFC_L0_TP_RTN_STALLED_CYCLES',
78: 'A7XX_PERF_CCU_RESERVED_78',
79: 'A7XX_PERF_CCU_RESERVED_79',
80: 'A7XX_PERF_CCU_RESERVED_80',
81: 'A7XX_PERF_CCU_RESERVED_81',
82: 'A7XX_PERF_CCU_RESERVED_82',
83: 'A7XX_PERF_CCU_RESERVED_83',
84: 'A7XX_PERF_CCU_RESERVED_84',
85: 'A7XX_PERF_CCU_RESERVED_85',
86: 'A7XX_PERF_CCU_RESERVED_86',
87: 'A7XX_PERF_CCU_RESERVED_87',
88: 'A7XX_PERF_CCU_RESERVED_88',
89: 'A7XX_PERF_CCU_RESERVED_89',
90: 'A7XX_PERF_CCU_RESERVED_90',
91: 'A7XX_PERF_CCU_RESERVED_91',
92: 'A7XX_PERF_CCU_RESERVED_92',
93: 'A7XX_PERF_CCU_RESERVED_93',
94: 'A7XX_PERF_CCU_RESERVED_94',
95: 'A7XX_PERF_CCU_RESERVED_95',
96: 'A7XX_PERF_CCU_RESERVED_96',
97: 'A7XX_PERF_CCU_RESERVED_97',
98: 'A7XX_PERF_CCU_RESERVED_98',
99: 'A7XX_PERF_CCU_RESERVED_99',
100: 'A7XX_PERF_CCU_RESERVED_100',
101: 'A7XX_PERF_CCU_RESERVED_101',
102: 'A7XX_PERF_CCU_RESERVED_102',
103: 'A7XX_PERF_CCU_RESERVED_103',
104: 'A7XX_PERF_CCU_RESERVED_104',
105: 'A7XX_PERF_CCU_RESERVED_105',
106: 'A7XX_PERF_CCU_RESERVED_106',
107: 'A7XX_PERF_CCU_RESERVED_107',
108: 'A7XX_PERF_CCU_RESERVED_108',
109: 'A7XX_PERF_CCU_RESERVED_109',
110: 'A7XX_PERF_CCU_RESERVED_110',
111: 'A7XX_PERF_CCU_RESERVED_111',
112: 'A7XX_PERF_CCU_RESERVED_112',
113: 'A7XX_PERF_CCU_RESERVED_113',
114: 'A7XX_PERF_CCU_RESERVED_114',
115: 'A7XX_PERF_CCU_RESERVED_115',
116: 'A7XX_PERF_CCU_RESERVED_116',
117: 'A7XX_PERF_CCU_RESERVED_117',
118: 'A7XX_PERF_CCU_RESERVED_118',
119: 'A7XX_PERF_CCU_RESERVED_119',
120: 'A7XX_PERF_CCU_RESERVED_120',
121: 'A7XX_PERF_CCU_RESERVED_121',
122: 'A7XX_PERF_CCU_RESERVED_122',
123: 'A7XX_PERF_CCU_RESERVED_123',
124: 'A7XX_PERF_CCU_RESERVED_124',
125: 'A7XX_PERF_CCU_RESERVED_125',
126: 'A7XX_PERF_CCU_RESERVED_126',
127: 'A7XX_PERF_CCU_RESERVED_127',
128: 'A7XX_PERF_CRE_RESOLVE_EVENTS',
129: 'A7XX_PERF_CRE_CONCURRENT_RESOLVE_EVENTS',
130: 'A7XX_PERF_CRE_DROPPED_CLEAR_EVENTS',
131: 'A7XX_PERF_CRE_ST_BLOCKS_CONCURRENT',
132: 'A7XX_PERF_CRE_LRZ_ST_BLOCKS_CONCURRENT',
133: 'A7XX_PERF_CRE_SP_UFC_PREFETCH_REQUESTS',
134: 'A7XX_PERF_CRE_RESOLVE_CDP_PREFETCH_REQUESTS',
135: 'A7XX_PERF_CRE_RESOLVE_UFC_PREFETCH_REQUESTS',
136: 'A7XX_PERF_CRE_DR_UFC_PREFTCH_REQUESTS',
}
A7XX_PERF_CCU_NEVER_COUNT = 0
A7XX_PERF_CCU_BUSY_CYCLES = 1
A7XX_PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN = 2
A7XX_PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN = 3
A7XX_PERF_CCU_DEPTH_BLOCKS = 4
A7XX_PERF_CCU_COLOR_BLOCKS = 5
A7XX_PERF_CCU_DEPTH_BLOCK_HIT = 6
A7XX_PERF_CCU_COLOR_BLOCK_HIT = 7
A7XX_PERF_CCU_PARTIAL_BLOCK_READ = 8
A7XX_PERF_CCU_GMEM_READ = 9
A7XX_PERF_CCU_GMEM_WRITE = 10
A7XX_PERF_CCU_2D_RD_REQ = 11
A7XX_PERF_CCU_2D_WR_REQ = 12
A7XX_PERF_CCU_UBWC_COLOR_BLOCKS_CONCURRENT = 13
A7XX_PERF_CCU_UBWC_DEPTH_BLOCKS_CONCURRENT = 14
A7XX_PERF_CCU_COLOR_RESOLVE_DROPPED = 15
A7XX_PERF_CCU_DEPTH_RESOLVE_DROPPED = 16
A7XX_PERF_CCU_COLOR_RENDER_CONCURRENT = 17
A7XX_PERF_CCU_DEPTH_RENDER_CONCURRENT = 18
A7XX_PERF_CCU_COLOR_RESOLVE_AFTER_RENDER = 19
A7XX_PERF_CCU_DEPTH_RESOLVE_AFTER_RENDER = 20
A7XX_PERF_CCU_GMEM_EXTRA_DEPTH_READ = 21
A7XX_PERF_CCU_GMEM_COLOR_READ_4AA = 22
A7XX_PERF_CCU_GMEM_COLOR_READ_4AA_FULL = 23
A7XX_PERF_CCU_COLOR_EVB_STALL = 24
A7XX_PERF_CCU_RENDER_OVERLAP_CRE_C = 25
A7XX_PERF_CCU_RENDER_OVERLAP_CRE_Z = 26
A7XX_PERF_CCU_RENDER_STALL_BY_CRE_C = 27
A7XX_PERF_CCU_RENDER_STALL_BY_CRE_Z = 28
A7XX_PERF_CCU_FULL_SURFACE_RESOLVE_CYCLES = 29
A7XX_PERF_CCU_RENDER_OVERLAP_FULL_SURFACE_RESOLVE = 30
A7XX_PERF_CCU_STALL_BY_FULL_SURFACE_RESOLVE = 31
A7XX_PERF_CCU_RESERVED_32 = 32
A7XX_PERF_CCU_RESERVED_33 = 33
A7XX_PERF_CCU_RESERVED_34 = 34
A7XX_PERF_CCU_RESERVED_35 = 35
A7XX_PERF_CCU_RESERVED_36 = 36
A7XX_PERF_CCU_RESERVED_37 = 37
A7XX_PERF_CCU_RESERVED_38 = 38
A7XX_PERF_CCU_RESERVED_39 = 39
A7XX_PERF_CCU_RESERVED_40 = 40
A7XX_PERF_CCU_RESERVED_41 = 41
A7XX_PERF_CCU_RESERVED_42 = 42
A7XX_PERF_CCU_RESERVED_43 = 43
A7XX_PERF_CCU_RESERVED_44 = 44
A7XX_PERF_CCU_RESERVED_45 = 45
A7XX_PERF_CCU_RESERVED_46 = 46
A7XX_PERF_CCU_RESERVED_47 = 47
A7XX_PERF_CCU_RESERVED_48 = 48
A7XX_PERF_CCU_RESERVED_49 = 49
A7XX_PERF_CCU_RESERVED_50 = 50
A7XX_PERF_CCU_RESERVED_51 = 51
A7XX_PERF_CCU_RESERVED_52 = 52
A7XX_PERF_CCU_RESERVED_53 = 53
A7XX_PERF_CCU_RESERVED_54 = 54
A7XX_PERF_CCU_RESERVED_55 = 55
A7XX_PERF_CCU_RESERVED_56 = 56
A7XX_PERF_CCU_RESERVED_57 = 57
A7XX_PERF_CCU_RESERVED_58 = 58
A7XX_PERF_CCU_RESERVED_59 = 59
A7XX_PERF_CCU_RESERVED_60 = 60
A7XX_PERF_CCU_RESERVED_61 = 61
A7XX_PERF_CCU_RESERVED_62 = 62
A7XX_PERF_CCU_RESERVED_63 = 63
A7XX_PERF_UFC_L0_TP_HINT_REQUESTS = 64
A7XX_PERF_UFC_L0_TP_HINT_TAG_MISS = 65
A7XX_PERF_UFC_L0_TP_HINT_TAG_HIT_RDY = 66
A7XX_PERF_UFC_L0_TP_HINT_TAG_HIT_NRDY = 67
A7XX_PERF_UFC_L0_TP_HINT_IS_FCLEAR = 68
A7XX_PERF_UFC_L0_TP_HINT_IS_ALPHA0 = 69
A7XX_PERF_UFC_L0_TP_HINT_IS_ALPHA1 = 70
A7XX_PERF_UFC_L0_TP_HINT_IS_UNCOMP = 71
A7XX_PERF_UFC_L0_SP_REQUESTS = 72
A7XX_PERF_UFC_L0_SP_FILTER_HIT = 73
A7XX_PERF_UFC_L0_SP_FILTER_MISS = 74
A7XX_PERF_UFC_L0_SP_REQ_STALLED_CYCLES = 75
A7XX_PERF_UFC_L0_TP_REQ_STALLED_CYCLES = 76
A7XX_PERF_UFC_L0_TP_RTN_STALLED_CYCLES = 77
A7XX_PERF_CCU_RESERVED_78 = 78
A7XX_PERF_CCU_RESERVED_79 = 79
A7XX_PERF_CCU_RESERVED_80 = 80
A7XX_PERF_CCU_RESERVED_81 = 81
A7XX_PERF_CCU_RESERVED_82 = 82
A7XX_PERF_CCU_RESERVED_83 = 83
A7XX_PERF_CCU_RESERVED_84 = 84
A7XX_PERF_CCU_RESERVED_85 = 85
A7XX_PERF_CCU_RESERVED_86 = 86
A7XX_PERF_CCU_RESERVED_87 = 87
A7XX_PERF_CCU_RESERVED_88 = 88
A7XX_PERF_CCU_RESERVED_89 = 89
A7XX_PERF_CCU_RESERVED_90 = 90
A7XX_PERF_CCU_RESERVED_91 = 91
A7XX_PERF_CCU_RESERVED_92 = 92
A7XX_PERF_CCU_RESERVED_93 = 93
A7XX_PERF_CCU_RESERVED_94 = 94
A7XX_PERF_CCU_RESERVED_95 = 95
A7XX_PERF_CCU_RESERVED_96 = 96
A7XX_PERF_CCU_RESERVED_97 = 97
A7XX_PERF_CCU_RESERVED_98 = 98
A7XX_PERF_CCU_RESERVED_99 = 99
A7XX_PERF_CCU_RESERVED_100 = 100
A7XX_PERF_CCU_RESERVED_101 = 101
A7XX_PERF_CCU_RESERVED_102 = 102
A7XX_PERF_CCU_RESERVED_103 = 103
A7XX_PERF_CCU_RESERVED_104 = 104
A7XX_PERF_CCU_RESERVED_105 = 105
A7XX_PERF_CCU_RESERVED_106 = 106
A7XX_PERF_CCU_RESERVED_107 = 107
A7XX_PERF_CCU_RESERVED_108 = 108
A7XX_PERF_CCU_RESERVED_109 = 109
A7XX_PERF_CCU_RESERVED_110 = 110
A7XX_PERF_CCU_RESERVED_111 = 111
A7XX_PERF_CCU_RESERVED_112 = 112
A7XX_PERF_CCU_RESERVED_113 = 113
A7XX_PERF_CCU_RESERVED_114 = 114
A7XX_PERF_CCU_RESERVED_115 = 115
A7XX_PERF_CCU_RESERVED_116 = 116
A7XX_PERF_CCU_RESERVED_117 = 117
A7XX_PERF_CCU_RESERVED_118 = 118
A7XX_PERF_CCU_RESERVED_119 = 119
A7XX_PERF_CCU_RESERVED_120 = 120
A7XX_PERF_CCU_RESERVED_121 = 121
A7XX_PERF_CCU_RESERVED_122 = 122
A7XX_PERF_CCU_RESERVED_123 = 123
A7XX_PERF_CCU_RESERVED_124 = 124
A7XX_PERF_CCU_RESERVED_125 = 125
A7XX_PERF_CCU_RESERVED_126 = 126
A7XX_PERF_CCU_RESERVED_127 = 127
A7XX_PERF_CRE_RESOLVE_EVENTS = 128
A7XX_PERF_CRE_CONCURRENT_RESOLVE_EVENTS = 129
A7XX_PERF_CRE_DROPPED_CLEAR_EVENTS = 130
A7XX_PERF_CRE_ST_BLOCKS_CONCURRENT = 131
A7XX_PERF_CRE_LRZ_ST_BLOCKS_CONCURRENT = 132
A7XX_PERF_CRE_SP_UFC_PREFETCH_REQUESTS = 133
A7XX_PERF_CRE_RESOLVE_CDP_PREFETCH_REQUESTS = 134
A7XX_PERF_CRE_RESOLVE_UFC_PREFETCH_REQUESTS = 135
A7XX_PERF_CRE_DR_UFC_PREFTCH_REQUESTS = 136
a7xx_ccu_perfcounter_select = ctypes.c_uint32 # enum
# values for enumeration 'a7xx_lrz_perfcounter_select'
a7xx_lrz_perfcounter_select__enumvalues = {
0: 'A7XX_PERF_LRZ_NEVER_COUNT',
1: 'A7XX_PERF_LRZ_BUSY_CYCLES',
2: 'A7XX_PERF_LRZ_STARVE_CYCLES_RAS',
3: 'A7XX_PERF_LRZ_STALL_CYCLES_RB',
4: 'A7XX_PERF_LRZ_STALL_CYCLES_VSC',
5: 'A7XX_PERF_LRZ_STALL_CYCLES_VPC_BE',
6: 'A7XX_PERF_LRZ_STALL_CYCLES_FLAG_ACR',
7: 'A7XX_PERF_LRZ_STALL_CYCLES_UCHE',
8: 'A7XX_PERF_LRZ_LRZ_READ',
9: 'A7XX_PERF_LRZ_LRZ_WRITE',
10: 'A7XX_PERF_LRZ_READ_LATENCY',
11: 'A7XX_PERF_LRZ_MERGE_CACHE_UPDATING',
12: 'A7XX_PERF_LRZ_PRIM_KILLED_BY_MASKGEN',
13: 'A7XX_PERF_LRZ_PRIM_KILLED_BY_LRZ',
14: 'A7XX_PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ',
15: 'A7XX_PERF_LRZ_FULL_8X8_TILES',
16: 'A7XX_PERF_LRZ_PARTIAL_8X8_TILES',
17: 'A7XX_PERF_LRZ_TILE_KILLED',
18: 'A7XX_PERF_LRZ_TOTAL_PIXEL',
19: 'A7XX_PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ',
20: 'A7XX_PERF_LRZ_FEEDBACK_ACCEPT',
21: 'A7XX_PERF_LRZ_FEEDBACK_DISCARD',
22: 'A7XX_PERF_LRZ_FEEDBACK_STALL',
23: 'A7XX_PERF_LRZ_STALL_CYCLES_RB_ZPLANE',
24: 'A7XX_PERF_LRZ_STALL_CYCLES_RB_BPLANE',
25: 'A7XX_PERF_LRZ_RAS_MASK_TRANS',
26: 'A7XX_PERF_LRZ_STALL_CYCLES_MVC',
27: 'A7XX_PERF_LRZ_TILE_KILLED_BY_IMAGE_VRS',
28: 'A7XX_PERF_LRZ_TILE_KILLED_BY_Z',
29: 'A7XX_PERF_LRZ_STALL_CYCLES_HLSQ_BATCH',
30: 'A7XX_PERF_LRZ_NUM_FLOCK',
}
A7XX_PERF_LRZ_NEVER_COUNT = 0
A7XX_PERF_LRZ_BUSY_CYCLES = 1
A7XX_PERF_LRZ_STARVE_CYCLES_RAS = 2
A7XX_PERF_LRZ_STALL_CYCLES_RB = 3
A7XX_PERF_LRZ_STALL_CYCLES_VSC = 4
A7XX_PERF_LRZ_STALL_CYCLES_VPC_BE = 5
A7XX_PERF_LRZ_STALL_CYCLES_FLAG_ACR = 6
A7XX_PERF_LRZ_STALL_CYCLES_UCHE = 7
A7XX_PERF_LRZ_LRZ_READ = 8
A7XX_PERF_LRZ_LRZ_WRITE = 9
A7XX_PERF_LRZ_READ_LATENCY = 10
A7XX_PERF_LRZ_MERGE_CACHE_UPDATING = 11
A7XX_PERF_LRZ_PRIM_KILLED_BY_MASKGEN = 12
A7XX_PERF_LRZ_PRIM_KILLED_BY_LRZ = 13
A7XX_PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ = 14
A7XX_PERF_LRZ_FULL_8X8_TILES = 15
A7XX_PERF_LRZ_PARTIAL_8X8_TILES = 16
A7XX_PERF_LRZ_TILE_KILLED = 17
A7XX_PERF_LRZ_TOTAL_PIXEL = 18
A7XX_PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ = 19
A7XX_PERF_LRZ_FEEDBACK_ACCEPT = 20
A7XX_PERF_LRZ_FEEDBACK_DISCARD = 21
A7XX_PERF_LRZ_FEEDBACK_STALL = 22
A7XX_PERF_LRZ_STALL_CYCLES_RB_ZPLANE = 23
A7XX_PERF_LRZ_STALL_CYCLES_RB_BPLANE = 24
A7XX_PERF_LRZ_RAS_MASK_TRANS = 25
A7XX_PERF_LRZ_STALL_CYCLES_MVC = 26
A7XX_PERF_LRZ_TILE_KILLED_BY_IMAGE_VRS = 27
A7XX_PERF_LRZ_TILE_KILLED_BY_Z = 28
A7XX_PERF_LRZ_STALL_CYCLES_HLSQ_BATCH = 29
A7XX_PERF_LRZ_NUM_FLOCK = 30
a7xx_lrz_perfcounter_select = ctypes.c_uint32 # enum
# values for enumeration 'a7xx_cmp_perfcounter_select'
a7xx_cmp_perfcounter_select__enumvalues = {
0: 'A7XX_PERF_CMPDECMP_NEVER_COUNT',
1: 'A7XX_PERF_CMPDECMP_STALL_CYCLES_ARB',
2: 'A7XX_PERF_CMPDECMP_VBIF_LATENCY_CYCLES',
3: 'A7XX_PERF_CMPDECMP_VBIF_LATENCY_SAMPLES',
4: 'A7XX_PERF_CMPDECMP_VBIF_READ_DATA_CCU',
5: 'A7XX_PERF_CMPDECMP_VBIF_WRITE_DATA_CCU',
6: 'A7XX_PERF_CMPDECMP_VBIF_READ_REQUEST',
7: 'A7XX_PERF_CMPDECMP_VBIF_WRITE_REQUEST',
8: 'A7XX_PERF_CMPDECMP_VBIF_READ_DATA',
9: 'A7XX_PERF_CMPDECMP_VBIF_WRITE_DATA',
10: 'A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT',
11: 'A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT',
12: 'A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT',
13: 'A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT',
14: 'A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT',
15: 'A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT',
16: 'A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT',
17: 'A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT',
18: 'A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT',
19: 'A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT',
20: 'A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT',
21: 'A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT',
22: 'A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT',
23: 'A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT',
24: 'A7XX_PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0',
25: 'A7XX_PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1',
26: 'A7XX_PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE',
27: 'A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT',
28: 'A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT',
29: 'A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT',
30: 'A7XX_PERF_CMPDECMP_CDP_FILTER_HIT',
31: 'A7XX_PERF_CMPDECMP_CDP_FILTER_MISS',
32: 'A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG0_COUNT',
33: 'A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG1_COUNT',
34: 'A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG2_COUNT',
35: 'A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG3_COUNT',
36: 'A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG4_COUNT',
37: 'A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG5_COUNT',
38: 'A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG6_COUNT',
39: 'A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG8_COUNT',
40: 'A7XX_PERF_CMPDECMP_COLOR_READ_FLAG0_COUNT',
41: 'A7XX_PERF_CMPDECMP_COLOR_READ_FLAG1_COUNT',
42: 'A7XX_PERF_CMPDECMP_COLOR_READ_FLAG2_COUNT',
43: 'A7XX_PERF_CMPDECMP_COLOR_READ_FLAG3_COUNT',
44: 'A7XX_PERF_CMPDECMP_COLOR_READ_FLAG4_COUNT',
45: 'A7XX_PERF_CMPDECMP_COLOR_READ_FLAG5_COUNT',
46: 'A7XX_PERF_CMPDECMP_COLOR_READ_FLAG6_COUNT',
47: 'A7XX_PERF_CMPDECMP_COLOR_READ_FLAG8_COUNT',
}
A7XX_PERF_CMPDECMP_NEVER_COUNT = 0
A7XX_PERF_CMPDECMP_STALL_CYCLES_ARB = 1
A7XX_PERF_CMPDECMP_VBIF_LATENCY_CYCLES = 2
A7XX_PERF_CMPDECMP_VBIF_LATENCY_SAMPLES = 3
A7XX_PERF_CMPDECMP_VBIF_READ_DATA_CCU = 4
A7XX_PERF_CMPDECMP_VBIF_WRITE_DATA_CCU = 5
A7XX_PERF_CMPDECMP_VBIF_READ_REQUEST = 6
A7XX_PERF_CMPDECMP_VBIF_WRITE_REQUEST = 7
A7XX_PERF_CMPDECMP_VBIF_READ_DATA = 8
A7XX_PERF_CMPDECMP_VBIF_WRITE_DATA = 9
A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT = 10
A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT = 11
A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT = 12
A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT = 13
A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT = 14
A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT = 15
A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT = 16
A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT = 17
A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT = 18
A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT = 19
A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT = 20
A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT = 21
A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT = 22
A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT = 23
A7XX_PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0 = 24
A7XX_PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1 = 25
A7XX_PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE = 26
A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT = 27
A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT = 28
A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT = 29
A7XX_PERF_CMPDECMP_CDP_FILTER_HIT = 30
A7XX_PERF_CMPDECMP_CDP_FILTER_MISS = 31
A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG0_COUNT = 32
A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG1_COUNT = 33
A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG2_COUNT = 34
A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG3_COUNT = 35
A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG4_COUNT = 36
A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG5_COUNT = 37
A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG6_COUNT = 38
A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG8_COUNT = 39
A7XX_PERF_CMPDECMP_COLOR_READ_FLAG0_COUNT = 40
A7XX_PERF_CMPDECMP_COLOR_READ_FLAG1_COUNT = 41
A7XX_PERF_CMPDECMP_COLOR_READ_FLAG2_COUNT = 42
A7XX_PERF_CMPDECMP_COLOR_READ_FLAG3_COUNT = 43
A7XX_PERF_CMPDECMP_COLOR_READ_FLAG4_COUNT = 44
A7XX_PERF_CMPDECMP_COLOR_READ_FLAG5_COUNT = 45
A7XX_PERF_CMPDECMP_COLOR_READ_FLAG6_COUNT = 46
A7XX_PERF_CMPDECMP_COLOR_READ_FLAG8_COUNT = 47
a7xx_cmp_perfcounter_select = ctypes.c_uint32 # enum
# values for enumeration 'a7xx_gbif_perfcounter_select'
a7xx_gbif_perfcounter_select__enumvalues = {
0: 'A7XX_PERF_GBIF_NEVER_COUNT',
1: 'A7XX_PERF_GBIF_RESERVED_1',
2: 'A7XX_PERF_GBIF_RESERVED_2',
3: 'A7XX_PERF_GBIF_RESERVED_3',
4: 'A7XX_PERF_GBIF_RESERVED_4',
5: 'A7XX_PERF_GBIF_RESERVED_5',
6: 'A7XX_PERF_GBIF_RESERVED_6',
7: 'A7XX_PERF_GBIF_RESERVED_7',
8: 'A7XX_PERF_GBIF_RESERVED_8',
9: 'A7XX_PERF_GBIF_RESERVED_9',
10: 'A7XX_PERF_GBIF_AXI0_READ_REQUESTS_TOTAL',
11: 'A7XX_PERF_GBIF_AXI1_READ_REQUESTS_TOTAL',
12: 'A7XX_PERF_GBIF_RESERVED_12',
13: 'A7XX_PERF_GBIF_RESERVED_13',
14: 'A7XX_PERF_GBIF_RESERVED_14',
15: 'A7XX_PERF_GBIF_RESERVED_15',
16: 'A7XX_PERF_GBIF_RESERVED_16',
17: 'A7XX_PERF_GBIF_RESERVED_17',
18: 'A7XX_PERF_GBIF_RESERVED_18',
19: 'A7XX_PERF_GBIF_RESERVED_19',
20: 'A7XX_PERF_GBIF_RESERVED_20',
21: 'A7XX_PERF_GBIF_RESERVED_21',
22: 'A7XX_PERF_GBIF_AXI0_WRITE_REQUESTS_TOTAL',
23: 'A7XX_PERF_GBIF_AXI1_WRITE_REQUESTS_TOTAL',
24: 'A7XX_PERF_GBIF_RESERVED_24',
25: 'A7XX_PERF_GBIF_RESERVED_25',
26: 'A7XX_PERF_GBIF_RESERVED_26',
27: 'A7XX_PERF_GBIF_RESERVED_27',
28: 'A7XX_PERF_GBIF_RESERVED_28',
29: 'A7XX_PERF_GBIF_RESERVED_29',
30: 'A7XX_PERF_GBIF_RESERVED_30',
31: 'A7XX_PERF_GBIF_RESERVED_31',
32: 'A7XX_PERF_GBIF_RESERVED_32',
33: 'A7XX_PERF_GBIF_RESERVED_33',
34: 'A7XX_PERF_GBIF_AXI0_READ_DATA_BEATS_TOTAL',
35: 'A7XX_PERF_GBIF_AXI1_READ_DATA_BEATS_TOTAL',
36: 'A7XX_PERF_GBIF_RESERVED_36',
37: 'A7XX_PERF_GBIF_RESERVED_37',
38: 'A7XX_PERF_GBIF_RESERVED_38',
39: 'A7XX_PERF_GBIF_RESERVED_39',
40: 'A7XX_PERF_GBIF_RESERVED_40',
41: 'A7XX_PERF_GBIF_RESERVED_41',
42: 'A7XX_PERF_GBIF_RESERVED_42',
43: 'A7XX_PERF_GBIF_RESERVED_43',
44: 'A7XX_PERF_GBIF_RESERVED_44',
45: 'A7XX_PERF_GBIF_RESERVED_45',
46: 'A7XX_PERF_GBIF_AXI0_WRITE_DATA_BEATS_TOTAL',
47: 'A7XX_PERF_GBIF_AXI1_WRITE_DATA_BEATS_TOTAL',
48: 'A7XX_PERF_GBIF_RESERVED_48',
49: 'A7XX_PERF_GBIF_RESERVED_49',
50: 'A7XX_PERF_GBIF_RESERVED_50',
51: 'A7XX_PERF_GBIF_RESERVED_51',
52: 'A7XX_PERF_GBIF_RESERVED_52',
53: 'A7XX_PERF_GBIF_RESERVED_53',
54: 'A7XX_PERF_GBIF_RESERVED_54',
55: 'A7XX_PERF_GBIF_RESERVED_55',
56: 'A7XX_PERF_GBIF_RESERVED_56',
57: 'A7XX_PERF_GBIF_RESERVED_57',
58: 'A7XX_PERF_GBIF_RESERVED_58',
59: 'A7XX_PERF_GBIF_RESERVED_59',
60: 'A7XX_PERF_GBIF_RESERVED_60',
61: 'A7XX_PERF_GBIF_RESERVED_61',
62: 'A7XX_PERF_GBIF_RESERVED_62',
63: 'A7XX_PERF_GBIF_RESERVED_63',
64: 'A7XX_PERF_GBIF_RESERVED_64',
65: 'A7XX_PERF_GBIF_RESERVED_65',
66: 'A7XX_PERF_GBIF_RESERVED_66',
67: 'A7XX_PERF_GBIF_RESERVED_67',
68: 'A7XX_PERF_GBIF_CYCLES_CH0_HELD_OFF_RD_ALL',
69: 'A7XX_PERF_GBIF_CYCLES_CH1_HELD_OFF_RD_ALL',
70: 'A7XX_PERF_GBIF_CYCLES_CH0_HELD_OFF_WR_ALL',
71: 'A7XX_PERF_GBIF_CYCLES_CH1_HELD_OFF_WR_ALL',
72: 'A7XX_PERF_GBIF_AXI_CH0_REQUEST_HELD_OFF',
73: 'A7XX_PERF_GBIF_AXI_CH1_REQUEST_HELD_OFF',
74: 'A7XX_PERF_GBIF_AXI_REQUEST_HELD_OFF',
75: 'A7XX_PERF_GBIF_AXI_CH0_WRITE_DATA_HELD_OFF',
76: 'A7XX_PERF_GBIF_AXI_CH1_WRITE_DATA_HELD_OFF',
77: 'A7XX_PERF_GBIF_AXI_ALL_WRITE_DATA_HELD_OFF',
78: 'A7XX_PERF_GBIF_RESERVED_78',
79: 'A7XX_PERF_GBIF_RESERVED_79',
80: 'A7XX_PERF_GBIF_RESERVED_80',
81: 'A7XX_PERF_GBIF_RESERVED_81',
82: 'A7XX_PERF_GBIF_RESERVED_82',
83: 'A7XX_PERF_GBIF_RESERVED_83',
84: 'A7XX_PERF_GBIF_RESERVED_84',
85: 'A7XX_PERF_GBIF_RESERVED_85',
86: 'A7XX_PERF_GBIF_RESERVED_86',
87: 'A7XX_PERF_GBIF_RESERVED_87',
88: 'A7XX_PERF_GBIF_RESERVED_88',
89: 'A7XX_PERF_GBIF_RESERVED_89',
90: 'A7XX_PERF_GBIF_RESERVED_90',
91: 'A7XX_PERF_GBIF_RESERVED_91',
92: 'A7XX_PERF_GBIF_RESERVED_92',
93: 'A7XX_PERF_GBIF_RESERVED_93',
94: 'A7XX_PERF_GBIF_RESERVED_94',
95: 'A7XX_PERF_GBIF_RESERVED_95',
96: 'A7XX_PERF_GBIF_RESERVED_96',
97: 'A7XX_PERF_GBIF_RESERVED_97',
98: 'A7XX_PERF_GBIF_RESERVED_98',
99: 'A7XX_PERF_GBIF_RESERVED_99',
100: 'A7XX_PERF_GBIF_RESERVED_100',
101: 'A7XX_PERF_GBIF_RESERVED_101',
102: 'A7XX_PERF_GBIF_RESERVED_102',
103: 'A7XX_PERF_GBIF_RESERVED_103',
104: 'A7XX_PERF_GBIF_RESERVED_104',
105: 'A7XX_PERF_GBIF_RESERVED_105',
106: 'A7XX_PERF_GBIF_RESERVED_106',
107: 'A7XX_PERF_GBIF_RESERVED_107',
108: 'A7XX_PERF_GBIF_RESERVED_108',
109: 'A7XX_PERF_GBIF_RESERVED_109',
110: 'A7XX_PERF_GBIF_RESERVED_110',
111: 'A7XX_PERF_GBIF_RESERVED_111',
112: 'A7XX_PERF_GBIF_RESERVED_112',
113: 'A7XX_PERF_GBIF_RESERVED_113',
114: 'A7XX_PERF_GBIF_RESERVED_114',
115: 'A7XX_PERF_GBIF_RESERVED_115',
116: 'A7XX_PERF_GBIF_RESERVED_116',
117: 'A7XX_PERF_GBIF_RESERVED_117',
118: 'A7XX_PERF_GBIF_RESERVED_118',
119: 'A7XX_PERF_GBIF_RESERVED_119',
120: 'A7XX_PERF_GBIF_RESERVED_120',
121: 'A7XX_PERF_GBIF_RESERVED_121',
122: 'A7XX_PERF_GBIF_RESERVED_122',
123: 'A7XX_PERF_GBIF_RESERVED_123',
124: 'A7XX_PERF_GBIF_RESERVED_124',
125: 'A7XX_PERF_GBIF_RESERVED_125',
126: 'A7XX_PERF_GBIF_RESERVED_126',
127: 'A7XX_PERF_GBIF_RESERVED_127',
128: 'A7XX_PERF_GBIF_RESERVED_128',
129: 'A7XX_PERF_GBIF_RESERVED_129',
130: 'A7XX_PERF_GBIF_RESERVED_130',
131: 'A7XX_PERF_GBIF_RESERVED_131',
132: 'A7XX_PERF_GBIF_RESERVED_132',
133: 'A7XX_PERF_GBIF_RESERVED_133',
134: 'A7XX_PERF_GBIF_RESERVED_134',
135: 'A7XX_PERF_GBIF_RESERVED_135',
136: 'A7XX_PERF_GBIF_RESERVED_136',
137: 'A7XX_PERF_GBIF_RESERVED_137',
138: 'A7XX_PERF_GBIF_RESERVED_138',
139: 'A7XX_PERF_GBIF_RESERVED_139',
140: 'A7XX_PERF_GBIF_RESERVED_140',
141: 'A7XX_PERF_GBIF_RESERVED_141',
142: 'A7XX_PERF_GBIF_RESERVED_142',
143: 'A7XX_PERF_GBIF_RESERVED_143',
144: 'A7XX_PERF_GBIF_RESERVED_144',
145: 'A7XX_PERF_GBIF_RESERVED_145',
146: 'A7XX_PERF_GBIF_RESERVED_146',
147: 'A7XX_PERF_GBIF_RESERVED_147',
148: 'A7XX_PERF_GBIF_RESERVED_148',
149: 'A7XX_PERF_GBIF_RESERVED_149',
150: 'A7XX_PERF_GBIF_RESERVED_150',
151: 'A7XX_PERF_GBIF_RESERVED_151',
152: 'A7XX_PERF_GBIF_RESERVED_152',
153: 'A7XX_PERF_GBIF_RESERVED_153',
154: 'A7XX_PERF_GBIF_RESERVED_154',
155: 'A7XX_PERF_GBIF_RESERVED_155',
156: 'A7XX_PERF_GBIF_RESERVED_156',
157: 'A7XX_PERF_GBIF_READ_BEAT_ALL_CHANNELS',
158: 'A7XX_PERF_GBIF_WRITE_BEAT_ALL_CHANNELS',
159: 'A7XX_PERF_GBIF_READ_AND_WRITE_BEAT_ALL_CHANNELS',
160: 'A7XX_PERF_GBIF_RSC0_REQUESTS_TOTAL',
161: 'A7XX_PERF_GBIF_RSC1_REQUESTS_TOTAL',
}
A7XX_PERF_GBIF_NEVER_COUNT = 0
A7XX_PERF_GBIF_RESERVED_1 = 1
A7XX_PERF_GBIF_RESERVED_2 = 2
A7XX_PERF_GBIF_RESERVED_3 = 3
A7XX_PERF_GBIF_RESERVED_4 = 4
A7XX_PERF_GBIF_RESERVED_5 = 5
A7XX_PERF_GBIF_RESERVED_6 = 6
A7XX_PERF_GBIF_RESERVED_7 = 7
A7XX_PERF_GBIF_RESERVED_8 = 8
A7XX_PERF_GBIF_RESERVED_9 = 9
A7XX_PERF_GBIF_AXI0_READ_REQUESTS_TOTAL = 10
A7XX_PERF_GBIF_AXI1_READ_REQUESTS_TOTAL = 11
A7XX_PERF_GBIF_RESERVED_12 = 12
A7XX_PERF_GBIF_RESERVED_13 = 13
A7XX_PERF_GBIF_RESERVED_14 = 14
A7XX_PERF_GBIF_RESERVED_15 = 15
A7XX_PERF_GBIF_RESERVED_16 = 16
A7XX_PERF_GBIF_RESERVED_17 = 17
A7XX_PERF_GBIF_RESERVED_18 = 18
A7XX_PERF_GBIF_RESERVED_19 = 19
A7XX_PERF_GBIF_RESERVED_20 = 20
A7XX_PERF_GBIF_RESERVED_21 = 21
A7XX_PERF_GBIF_AXI0_WRITE_REQUESTS_TOTAL = 22
A7XX_PERF_GBIF_AXI1_WRITE_REQUESTS_TOTAL = 23
A7XX_PERF_GBIF_RESERVED_24 = 24
A7XX_PERF_GBIF_RESERVED_25 = 25
A7XX_PERF_GBIF_RESERVED_26 = 26
A7XX_PERF_GBIF_RESERVED_27 = 27
A7XX_PERF_GBIF_RESERVED_28 = 28
A7XX_PERF_GBIF_RESERVED_29 = 29
A7XX_PERF_GBIF_RESERVED_30 = 30
A7XX_PERF_GBIF_RESERVED_31 = 31
A7XX_PERF_GBIF_RESERVED_32 = 32
A7XX_PERF_GBIF_RESERVED_33 = 33
A7XX_PERF_GBIF_AXI0_READ_DATA_BEATS_TOTAL = 34
A7XX_PERF_GBIF_AXI1_READ_DATA_BEATS_TOTAL = 35
A7XX_PERF_GBIF_RESERVED_36 = 36
A7XX_PERF_GBIF_RESERVED_37 = 37
A7XX_PERF_GBIF_RESERVED_38 = 38
A7XX_PERF_GBIF_RESERVED_39 = 39
A7XX_PERF_GBIF_RESERVED_40 = 40
A7XX_PERF_GBIF_RESERVED_41 = 41
A7XX_PERF_GBIF_RESERVED_42 = 42
A7XX_PERF_GBIF_RESERVED_43 = 43
A7XX_PERF_GBIF_RESERVED_44 = 44
A7XX_PERF_GBIF_RESERVED_45 = 45
A7XX_PERF_GBIF_AXI0_WRITE_DATA_BEATS_TOTAL = 46
A7XX_PERF_GBIF_AXI1_WRITE_DATA_BEATS_TOTAL = 47
A7XX_PERF_GBIF_RESERVED_48 = 48
A7XX_PERF_GBIF_RESERVED_49 = 49
A7XX_PERF_GBIF_RESERVED_50 = 50
A7XX_PERF_GBIF_RESERVED_51 = 51
A7XX_PERF_GBIF_RESERVED_52 = 52
A7XX_PERF_GBIF_RESERVED_53 = 53
A7XX_PERF_GBIF_RESERVED_54 = 54
A7XX_PERF_GBIF_RESERVED_55 = 55
A7XX_PERF_GBIF_RESERVED_56 = 56
A7XX_PERF_GBIF_RESERVED_57 = 57
A7XX_PERF_GBIF_RESERVED_58 = 58
A7XX_PERF_GBIF_RESERVED_59 = 59
A7XX_PERF_GBIF_RESERVED_60 = 60
A7XX_PERF_GBIF_RESERVED_61 = 61
A7XX_PERF_GBIF_RESERVED_62 = 62
A7XX_PERF_GBIF_RESERVED_63 = 63
A7XX_PERF_GBIF_RESERVED_64 = 64
A7XX_PERF_GBIF_RESERVED_65 = 65
A7XX_PERF_GBIF_RESERVED_66 = 66
A7XX_PERF_GBIF_RESERVED_67 = 67
A7XX_PERF_GBIF_CYCLES_CH0_HELD_OFF_RD_ALL = 68
A7XX_PERF_GBIF_CYCLES_CH1_HELD_OFF_RD_ALL = 69
A7XX_PERF_GBIF_CYCLES_CH0_HELD_OFF_WR_ALL = 70
A7XX_PERF_GBIF_CYCLES_CH1_HELD_OFF_WR_ALL = 71
A7XX_PERF_GBIF_AXI_CH0_REQUEST_HELD_OFF = 72
A7XX_PERF_GBIF_AXI_CH1_REQUEST_HELD_OFF = 73
A7XX_PERF_GBIF_AXI_REQUEST_HELD_OFF = 74
A7XX_PERF_GBIF_AXI_CH0_WRITE_DATA_HELD_OFF = 75
A7XX_PERF_GBIF_AXI_CH1_WRITE_DATA_HELD_OFF = 76
A7XX_PERF_GBIF_AXI_ALL_WRITE_DATA_HELD_OFF = 77
A7XX_PERF_GBIF_RESERVED_78 = 78
A7XX_PERF_GBIF_RESERVED_79 = 79
A7XX_PERF_GBIF_RESERVED_80 = 80
A7XX_PERF_GBIF_RESERVED_81 = 81
A7XX_PERF_GBIF_RESERVED_82 = 82
A7XX_PERF_GBIF_RESERVED_83 = 83
A7XX_PERF_GBIF_RESERVED_84 = 84
A7XX_PERF_GBIF_RESERVED_85 = 85
A7XX_PERF_GBIF_RESERVED_86 = 86
A7XX_PERF_GBIF_RESERVED_87 = 87
A7XX_PERF_GBIF_RESERVED_88 = 88
A7XX_PERF_GBIF_RESERVED_89 = 89
A7XX_PERF_GBIF_RESERVED_90 = 90
A7XX_PERF_GBIF_RESERVED_91 = 91
A7XX_PERF_GBIF_RESERVED_92 = 92
A7XX_PERF_GBIF_RESERVED_93 = 93
A7XX_PERF_GBIF_RESERVED_94 = 94
A7XX_PERF_GBIF_RESERVED_95 = 95
A7XX_PERF_GBIF_RESERVED_96 = 96
A7XX_PERF_GBIF_RESERVED_97 = 97
A7XX_PERF_GBIF_RESERVED_98 = 98
A7XX_PERF_GBIF_RESERVED_99 = 99
A7XX_PERF_GBIF_RESERVED_100 = 100
A7XX_PERF_GBIF_RESERVED_101 = 101
A7XX_PERF_GBIF_RESERVED_102 = 102
A7XX_PERF_GBIF_RESERVED_103 = 103
A7XX_PERF_GBIF_RESERVED_104 = 104
A7XX_PERF_GBIF_RESERVED_105 = 105
A7XX_PERF_GBIF_RESERVED_106 = 106
A7XX_PERF_GBIF_RESERVED_107 = 107
A7XX_PERF_GBIF_RESERVED_108 = 108
A7XX_PERF_GBIF_RESERVED_109 = 109
A7XX_PERF_GBIF_RESERVED_110 = 110
A7XX_PERF_GBIF_RESERVED_111 = 111
A7XX_PERF_GBIF_RESERVED_112 = 112
A7XX_PERF_GBIF_RESERVED_113 = 113
A7XX_PERF_GBIF_RESERVED_114 = 114
A7XX_PERF_GBIF_RESERVED_115 = 115
A7XX_PERF_GBIF_RESERVED_116 = 116
A7XX_PERF_GBIF_RESERVED_117 = 117
A7XX_PERF_GBIF_RESERVED_118 = 118
A7XX_PERF_GBIF_RESERVED_119 = 119
A7XX_PERF_GBIF_RESERVED_120 = 120
A7XX_PERF_GBIF_RESERVED_121 = 121
A7XX_PERF_GBIF_RESERVED_122 = 122
A7XX_PERF_GBIF_RESERVED_123 = 123
A7XX_PERF_GBIF_RESERVED_124 = 124
A7XX_PERF_GBIF_RESERVED_125 = 125
A7XX_PERF_GBIF_RESERVED_126 = 126
A7XX_PERF_GBIF_RESERVED_127 = 127
A7XX_PERF_GBIF_RESERVED_128 = 128
A7XX_PERF_GBIF_RESERVED_129 = 129
A7XX_PERF_GBIF_RESERVED_130 = 130
A7XX_PERF_GBIF_RESERVED_131 = 131
A7XX_PERF_GBIF_RESERVED_132 = 132
A7XX_PERF_GBIF_RESERVED_133 = 133
A7XX_PERF_GBIF_RESERVED_134 = 134
A7XX_PERF_GBIF_RESERVED_135 = 135
A7XX_PERF_GBIF_RESERVED_136 = 136
A7XX_PERF_GBIF_RESERVED_137 = 137
A7XX_PERF_GBIF_RESERVED_138 = 138
A7XX_PERF_GBIF_RESERVED_139 = 139
A7XX_PERF_GBIF_RESERVED_140 = 140
A7XX_PERF_GBIF_RESERVED_141 = 141
A7XX_PERF_GBIF_RESERVED_142 = 142
A7XX_PERF_GBIF_RESERVED_143 = 143
A7XX_PERF_GBIF_RESERVED_144 = 144
A7XX_PERF_GBIF_RESERVED_145 = 145
A7XX_PERF_GBIF_RESERVED_146 = 146
A7XX_PERF_GBIF_RESERVED_147 = 147
A7XX_PERF_GBIF_RESERVED_148 = 148
A7XX_PERF_GBIF_RESERVED_149 = 149
A7XX_PERF_GBIF_RESERVED_150 = 150
A7XX_PERF_GBIF_RESERVED_151 = 151
A7XX_PERF_GBIF_RESERVED_152 = 152
A7XX_PERF_GBIF_RESERVED_153 = 153
A7XX_PERF_GBIF_RESERVED_154 = 154
A7XX_PERF_GBIF_RESERVED_155 = 155
A7XX_PERF_GBIF_RESERVED_156 = 156
A7XX_PERF_GBIF_READ_BEAT_ALL_CHANNELS = 157
A7XX_PERF_GBIF_WRITE_BEAT_ALL_CHANNELS = 158
A7XX_PERF_GBIF_READ_AND_WRITE_BEAT_ALL_CHANNELS = 159
A7XX_PERF_GBIF_RSC0_REQUESTS_TOTAL = 160
A7XX_PERF_GBIF_RSC1_REQUESTS_TOTAL = 161
a7xx_gbif_perfcounter_select = ctypes.c_uint32 # enum
# values for enumeration 'a7xx_ufc_perfcounter_select'
a7xx_ufc_perfcounter_select__enumvalues = {
0: 'A7XX_PERF_UFC_NEVER_COUNT',
1: 'A7XX_PERF_UFC_BUSY_CYCLES',
2: 'A7XX_PERF_UFC_READ_DATA_VBIF',
3: 'A7XX_PERF_UFC_WRITE_DATA_VBIF',
4: 'A7XX_PERF_UFC_READ_REQUEST_VBIF',
5: 'A7XX_PERF_UFC_WRITE_REQUEST_VBIF',
6: 'A7XX_PERF_UFC_MAIN_HIT_CRE_PREFETCH',
7: 'A7XX_PERF_UFC_MAIN_HIT_SP_PREFETCH',
8: 'A7XX_PERF_UFC_MAIN_HIT_TP_PREFETCH',
9: 'A7XX_PERF_UFC_MAIN_HIT_UBWC_READ',
10: 'A7XX_PERF_UFC_MAIN_HIT_UBWC_WRITE',
11: 'A7XX_PERF_UFC_MAIN_MISS_CRE_PREFETCH',
12: 'A7XX_PERF_UFC_MAIN_MISS_SP_PREFETCH',
13: 'A7XX_PERF_UFC_MAIN_MISS_TP_PREFETCH',
14: 'A7XX_PERF_UFC_MAIN_MISS_UBWC_READ',
15: 'A7XX_PERF_UFC_MAIN_MISS_UBWC_WRITE',
16: 'A7XX_PERF_UFC_MAIN_UBWC_RD_NRDY',
17: 'A7XX_PERF_UFC_MAIN_UBWC_RD_RDY',
18: 'A7XX_PERF_UFC_MAIN_TP_RD_NRDY',
19: 'A7XX_PERF_UFC_MAIN_TP_RD_RDY',
20: 'A7XX_PERF_UFC_STALL_CYCLES_GBIF_CMD',
21: 'A7XX_PERF_UFC_STALL_CYCLES_GBIF_RDATA',
22: 'A7XX_PERF_UFC_STALL_CYCLES_GBIF_WDATA',
23: 'A7XX_PERF_UFC_STALL_CYCLES_UBWC_WR_FLAG',
24: 'A7XX_PERF_UFC_STALL_CYCLES_UBWC_FLAG_RTN',
25: 'A7XX_PERF_UFC_STALL_CYCLES_UBWC_EVENT',
26: 'A7XX_PERF_UFC_UBWC_REQ_STALLED_CYCLES',
27: 'A7XX_PERF_UFC_UBWC_RD_STALLED_CYCLES',
28: 'A7XX_PERF_UFC_UBWC_WR_STALLED_CYCLES',
29: 'A7XX_PERF_UFC_PREFETCH_STALLED_CYCLES',
30: 'A7XX_PERF_UFC_EVICTION_STALLED_CYCLES',
31: 'A7XX_PERF_UFC_LOCK_STALLED_CYCLES',
32: 'A7XX_PERF_UFC_MISS_LATENCY_CYCLES',
33: 'A7XX_PERF_UFC_MISS_LATENCY_SAMPLES',
34: 'A7XX_PERF_UFC_L1_CRE_REQUESTS',
35: 'A7XX_PERF_UFC_L1_CRE_STALLED_CYCLES',
36: 'A7XX_PERF_UFC_L1_CRE_FILTER_HIT',
37: 'A7XX_PERF_UFC_L1_CRE_FILTER_MISS',
38: 'A7XX_PERF_UFC_L1_SP_REQUESTS',
39: 'A7XX_PERF_UFC_L1_SP_STALLED_CYCLES',
40: 'A7XX_PERF_UFC_L1_SP_FILTER_HIT',
41: 'A7XX_PERF_UFC_L1_SP_FILTER_MISS',
42: 'A7XX_PERF_UFC_L1_TP_HINT_REQUESTS',
43: 'A7XX_PERF_UFC_L1_TP_STALLED_CYCLES',
44: 'A7XX_PERF_UFC_L1_TP_HINT_TAG_MISS',
45: 'A7XX_PERF_UFC_L1_TP_HINT_TAG_HIT_RDY',
46: 'A7XX_PERF_UFC_L1_TP_HINT_TAG_HIT_NRDY',
}
A7XX_PERF_UFC_NEVER_COUNT = 0
A7XX_PERF_UFC_BUSY_CYCLES = 1
A7XX_PERF_UFC_READ_DATA_VBIF = 2
A7XX_PERF_UFC_WRITE_DATA_VBIF = 3
A7XX_PERF_UFC_READ_REQUEST_VBIF = 4
A7XX_PERF_UFC_WRITE_REQUEST_VBIF = 5
A7XX_PERF_UFC_MAIN_HIT_CRE_PREFETCH = 6
A7XX_PERF_UFC_MAIN_HIT_SP_PREFETCH = 7
A7XX_PERF_UFC_MAIN_HIT_TP_PREFETCH = 8
A7XX_PERF_UFC_MAIN_HIT_UBWC_READ = 9
A7XX_PERF_UFC_MAIN_HIT_UBWC_WRITE = 10
A7XX_PERF_UFC_MAIN_MISS_CRE_PREFETCH = 11
A7XX_PERF_UFC_MAIN_MISS_SP_PREFETCH = 12
A7XX_PERF_UFC_MAIN_MISS_TP_PREFETCH = 13
A7XX_PERF_UFC_MAIN_MISS_UBWC_READ = 14
A7XX_PERF_UFC_MAIN_MISS_UBWC_WRITE = 15
A7XX_PERF_UFC_MAIN_UBWC_RD_NRDY = 16
A7XX_PERF_UFC_MAIN_UBWC_RD_RDY = 17
A7XX_PERF_UFC_MAIN_TP_RD_NRDY = 18
A7XX_PERF_UFC_MAIN_TP_RD_RDY = 19
A7XX_PERF_UFC_STALL_CYCLES_GBIF_CMD = 20
A7XX_PERF_UFC_STALL_CYCLES_GBIF_RDATA = 21
A7XX_PERF_UFC_STALL_CYCLES_GBIF_WDATA = 22
A7XX_PERF_UFC_STALL_CYCLES_UBWC_WR_FLAG = 23
A7XX_PERF_UFC_STALL_CYCLES_UBWC_FLAG_RTN = 24
A7XX_PERF_UFC_STALL_CYCLES_UBWC_EVENT = 25
A7XX_PERF_UFC_UBWC_REQ_STALLED_CYCLES = 26
A7XX_PERF_UFC_UBWC_RD_STALLED_CYCLES = 27
A7XX_PERF_UFC_UBWC_WR_STALLED_CYCLES = 28
A7XX_PERF_UFC_PREFETCH_STALLED_CYCLES = 29
A7XX_PERF_UFC_EVICTION_STALLED_CYCLES = 30
A7XX_PERF_UFC_LOCK_STALLED_CYCLES = 31
A7XX_PERF_UFC_MISS_LATENCY_CYCLES = 32
A7XX_PERF_UFC_MISS_LATENCY_SAMPLES = 33
A7XX_PERF_UFC_L1_CRE_REQUESTS = 34
A7XX_PERF_UFC_L1_CRE_STALLED_CYCLES = 35
A7XX_PERF_UFC_L1_CRE_FILTER_HIT = 36
A7XX_PERF_UFC_L1_CRE_FILTER_MISS = 37
A7XX_PERF_UFC_L1_SP_REQUESTS = 38
A7XX_PERF_UFC_L1_SP_STALLED_CYCLES = 39
A7XX_PERF_UFC_L1_SP_FILTER_HIT = 40
A7XX_PERF_UFC_L1_SP_FILTER_MISS = 41
A7XX_PERF_UFC_L1_TP_HINT_REQUESTS = 42
A7XX_PERF_UFC_L1_TP_STALLED_CYCLES = 43
A7XX_PERF_UFC_L1_TP_HINT_TAG_MISS = 44
A7XX_PERF_UFC_L1_TP_HINT_TAG_HIT_RDY = 45
A7XX_PERF_UFC_L1_TP_HINT_TAG_HIT_NRDY = 46
a7xx_ufc_perfcounter_select = ctypes.c_uint32 # enum
# values for enumeration 'a6xx_sequenced_thread_dist'
a6xx_sequenced_thread_dist__enumvalues = {
0: 'DIST_SCREEN_COORD',
1: 'DIST_ALL_TO_RB0',
}
DIST_SCREEN_COORD = 0
DIST_ALL_TO_RB0 = 1
a6xx_sequenced_thread_dist = ctypes.c_uint32 # enum
# values for enumeration 'a6xx_single_prim_mode'
a6xx_single_prim_mode__enumvalues = {
0: 'NO_FLUSH',
1: 'FLUSH_PER_OVERLAP_AND_OVERWRITE',
3: 'FLUSH_PER_OVERLAP',
}
NO_FLUSH = 0
FLUSH_PER_OVERLAP_AND_OVERWRITE = 1
FLUSH_PER_OVERLAP = 3
a6xx_single_prim_mode = ctypes.c_uint32 # enum
# values for enumeration 'a6xx_raster_mode'
a6xx_raster_mode__enumvalues = {
0: 'TYPE_TILED',
1: 'TYPE_WRITER',
}
TYPE_TILED = 0
TYPE_WRITER = 1
a6xx_raster_mode = ctypes.c_uint32 # enum
# values for enumeration 'a6xx_raster_direction'
a6xx_raster_direction__enumvalues = {
0: 'LR_TB',
1: 'RL_TB',
2: 'LR_BT',
3: 'RB_BT',
}
LR_TB = 0
RL_TB = 1
LR_BT = 2
RB_BT = 3
a6xx_raster_direction = ctypes.c_uint32 # enum
# values for enumeration 'a6xx_render_mode'
a6xx_render_mode__enumvalues = {
0: 'RENDERING_PASS',
1: 'BINNING_PASS',
}
RENDERING_PASS = 0
BINNING_PASS = 1
a6xx_render_mode = ctypes.c_uint32 # enum
# values for enumeration 'a6xx_buffers_location'
a6xx_buffers_location__enumvalues = {
0: 'BUFFERS_IN_GMEM',
3: 'BUFFERS_IN_SYSMEM',
}
BUFFERS_IN_GMEM = 0
BUFFERS_IN_SYSMEM = 3
a6xx_buffers_location = ctypes.c_uint32 # enum
# values for enumeration 'a6xx_lrz_dir_status'
a6xx_lrz_dir_status__enumvalues = {
1: 'LRZ_DIR_LE',
2: 'LRZ_DIR_GE',
3: 'LRZ_DIR_INVALID',
}
LRZ_DIR_LE = 1
LRZ_DIR_GE = 2
LRZ_DIR_INVALID = 3
a6xx_lrz_dir_status = ctypes.c_uint32 # enum
# values for enumeration 'a6xx_fragcoord_sample_mode'
a6xx_fragcoord_sample_mode__enumvalues = {
0: 'FRAGCOORD_CENTER',
3: 'FRAGCOORD_SAMPLE',
}
FRAGCOORD_CENTER = 0
FRAGCOORD_SAMPLE = 3
a6xx_fragcoord_sample_mode = ctypes.c_uint32 # enum
# values for enumeration 'a6xx_rotation'
a6xx_rotation__enumvalues = {
0: 'ROTATE_0',
1: 'ROTATE_90',
2: 'ROTATE_180',
3: 'ROTATE_270',
4: 'ROTATE_HFLIP',
5: 'ROTATE_VFLIP',
}
ROTATE_0 = 0
ROTATE_90 = 1
ROTATE_180 = 2
ROTATE_270 = 3
ROTATE_HFLIP = 4
ROTATE_VFLIP = 5
a6xx_rotation = ctypes.c_uint32 # enum
# values for enumeration 'a6xx_ccu_cache_size'
a6xx_ccu_cache_size__enumvalues = {
0: 'CCU_CACHE_SIZE_FULL',
1: 'CCU_CACHE_SIZE_HALF',
2: 'CCU_CACHE_SIZE_QUARTER',
3: 'CCU_CACHE_SIZE_EIGHTH',
}
CCU_CACHE_SIZE_FULL = 0
CCU_CACHE_SIZE_HALF = 1
CCU_CACHE_SIZE_QUARTER = 2
CCU_CACHE_SIZE_EIGHTH = 3
a6xx_ccu_cache_size = ctypes.c_uint32 # enum
# values for enumeration 'a6xx_varying_interp_mode'
a6xx_varying_interp_mode__enumvalues = {
0: 'INTERP_SMOOTH',
1: 'INTERP_FLAT',
2: 'INTERP_ZERO',
3: 'INTERP_ONE',
}
INTERP_SMOOTH = 0
INTERP_FLAT = 1
INTERP_ZERO = 2
INTERP_ONE = 3
a6xx_varying_interp_mode = ctypes.c_uint32 # enum
# values for enumeration 'a6xx_varying_ps_repl_mode'
a6xx_varying_ps_repl_mode__enumvalues = {
0: 'PS_REPL_NONE',
1: 'PS_REPL_S',
2: 'PS_REPL_T',
3: 'PS_REPL_ONE_MINUS_T',
}
PS_REPL_NONE = 0
PS_REPL_S = 1
PS_REPL_T = 2
PS_REPL_ONE_MINUS_T = 3
a6xx_varying_ps_repl_mode = ctypes.c_uint32 # enum
# values for enumeration 'a6xx_threadsize'
a6xx_threadsize__enumvalues = {
0: 'THREAD64',
1: 'THREAD128',
}
THREAD64 = 0
THREAD128 = 1
a6xx_threadsize = ctypes.c_uint32 # enum
# values for enumeration 'a6xx_bindless_descriptor_size'
a6xx_bindless_descriptor_size__enumvalues = {
1: 'BINDLESS_DESCRIPTOR_16B',
3: 'BINDLESS_DESCRIPTOR_64B',
}
BINDLESS_DESCRIPTOR_16B = 1
BINDLESS_DESCRIPTOR_64B = 3
a6xx_bindless_descriptor_size = ctypes.c_uint32 # enum
# values for enumeration 'a6xx_isam_mode'
a6xx_isam_mode__enumvalues = {
1: 'ISAMMODE_CL',
2: 'ISAMMODE_GL',
}
ISAMMODE_CL = 1
ISAMMODE_GL = 2
a6xx_isam_mode = ctypes.c_uint32 # enum
# values for enumeration 'a7xx_cs_yalign'
a7xx_cs_yalign__enumvalues = {
8: 'CS_YALIGN_1',
4: 'CS_YALIGN_2',
2: 'CS_YALIGN_4',
1: 'CS_YALIGN_8',
}
CS_YALIGN_1 = 8
CS_YALIGN_2 = 4
CS_YALIGN_4 = 2
CS_YALIGN_8 = 1
a7xx_cs_yalign = ctypes.c_uint32 # enum
# values for enumeration 'a6xx_tex_filter'
a6xx_tex_filter__enumvalues = {
0: 'A6XX_TEX_NEAREST',
1: 'A6XX_TEX_LINEAR',
2: 'A6XX_TEX_ANISO',
3: 'A6XX_TEX_CUBIC',
}
A6XX_TEX_NEAREST = 0
A6XX_TEX_LINEAR = 1
A6XX_TEX_ANISO = 2
A6XX_TEX_CUBIC = 3
a6xx_tex_filter = ctypes.c_uint32 # enum
# values for enumeration 'a6xx_tex_clamp'
a6xx_tex_clamp__enumvalues = {
0: 'A6XX_TEX_REPEAT',
1: 'A6XX_TEX_CLAMP_TO_EDGE',
2: 'A6XX_TEX_MIRROR_REPEAT',
3: 'A6XX_TEX_CLAMP_TO_BORDER',
4: 'A6XX_TEX_MIRROR_CLAMP',
}
A6XX_TEX_REPEAT = 0
A6XX_TEX_CLAMP_TO_EDGE = 1
A6XX_TEX_MIRROR_REPEAT = 2
A6XX_TEX_CLAMP_TO_BORDER = 3
A6XX_TEX_MIRROR_CLAMP = 4
a6xx_tex_clamp = ctypes.c_uint32 # enum
# values for enumeration 'a6xx_tex_aniso'
a6xx_tex_aniso__enumvalues = {
0: 'A6XX_TEX_ANISO_1',
1: 'A6XX_TEX_ANISO_2',
2: 'A6XX_TEX_ANISO_4',
3: 'A6XX_TEX_ANISO_8',
4: 'A6XX_TEX_ANISO_16',
}
A6XX_TEX_ANISO_1 = 0
A6XX_TEX_ANISO_2 = 1
A6XX_TEX_ANISO_4 = 2
A6XX_TEX_ANISO_8 = 3
A6XX_TEX_ANISO_16 = 4
a6xx_tex_aniso = ctypes.c_uint32 # enum
# values for enumeration 'a6xx_reduction_mode'
a6xx_reduction_mode__enumvalues = {
0: 'A6XX_REDUCTION_MODE_AVERAGE',
1: 'A6XX_REDUCTION_MODE_MIN',
2: 'A6XX_REDUCTION_MODE_MAX',
}
A6XX_REDUCTION_MODE_AVERAGE = 0
A6XX_REDUCTION_MODE_MIN = 1
A6XX_REDUCTION_MODE_MAX = 2
a6xx_reduction_mode = ctypes.c_uint32 # enum
# values for enumeration 'a6xx_tex_swiz'
a6xx_tex_swiz__enumvalues = {
0: 'A6XX_TEX_X',
1: 'A6XX_TEX_Y',
2: 'A6XX_TEX_Z',
3: 'A6XX_TEX_W',
4: 'A6XX_TEX_ZERO',
5: 'A6XX_TEX_ONE',
}
A6XX_TEX_X = 0
A6XX_TEX_Y = 1
A6XX_TEX_Z = 2
A6XX_TEX_W = 3
A6XX_TEX_ZERO = 4
A6XX_TEX_ONE = 5
a6xx_tex_swiz = ctypes.c_uint32 # enum
# values for enumeration 'a6xx_tex_type'
a6xx_tex_type__enumvalues = {
0: 'A6XX_TEX_1D',
1: 'A6XX_TEX_2D',
2: 'A6XX_TEX_CUBE',
3: 'A6XX_TEX_3D',
4: 'A6XX_TEX_BUFFER',
}
A6XX_TEX_1D = 0
A6XX_TEX_2D = 1
A6XX_TEX_CUBE = 2
A6XX_TEX_3D = 3
A6XX_TEX_BUFFER = 4
a6xx_tex_type = ctypes.c_uint32 # enum
__all__ = \
['A2XX', 'A3XX', 'A4XX', 'A4XX_CP_DRAW_INDIRECT_0_GS_ENABLE',
'A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__MASK',
'A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__SHIFT',
'A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__MASK',
'A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__SHIFT',
'A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__MASK',
'A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__SHIFT',
'A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__MASK',
'A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__SHIFT',
'A4XX_CP_DRAW_INDIRECT_0_TESS_ENABLE',
'A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__MASK',
'A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__SHIFT',
'A4XX_CP_DRAW_INDIRECT_1_INDIRECT__MASK',
'A4XX_CP_DRAW_INDIRECT_1_INDIRECT__SHIFT',
'A4XX_CP_DRAW_INDX_INDIRECT_0_GS_ENABLE',
'A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__MASK',
'A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__SHIFT',
'A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE__MASK',
'A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE__SHIFT',
'A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__MASK',
'A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__SHIFT',
'A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__MASK',
'A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__SHIFT',
'A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_ENABLE',
'A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__MASK',
'A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__SHIFT',
'A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__MASK',
'A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__SHIFT',
'A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__MASK',
'A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__SHIFT',
'A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__MASK',
'A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__SHIFT',
'A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__MASK',
'A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__SHIFT',
'A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__MASK',
'A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__SHIFT',
'A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__MASK',
'A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__SHIFT',
'A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__MASK',
'A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__SHIFT', 'A5XX',
'A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__MASK',
'A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__SHIFT',
'A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__MASK',
'A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__SHIFT',
'A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__MASK',
'A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__SHIFT',
'A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__MASK',
'A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__SHIFT',
'A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__MASK',
'A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__SHIFT',
'A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__MASK',
'A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__SHIFT',
'A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__MASK',
'A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__SHIFT',
'A5XX_CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__MASK',
'A5XX_CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__SHIFT',
'A5XX_CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__MASK',
'A5XX_CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__SHIFT',
'A5XX_CP_DRAW_INDX_OFFSET_6_MAX_INDICES__MASK',
'A5XX_CP_DRAW_INDX_OFFSET_6_MAX_INDICES__SHIFT',
'A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__MASK',
'A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__SHIFT',
'A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__MASK',
'A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__SHIFT',
'A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__MASK',
'A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__SHIFT',
'A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__MASK',
'A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__SHIFT',
'A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__MASK',
'A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__SHIFT', 'A6XX',
'A6XX_CP_2D_EVENT_END_STATE_ID__MASK',
'A6XX_CP_2D_EVENT_END_STATE_ID__SHIFT',
'A6XX_CP_2D_EVENT_START_STATE_ID__MASK',
'A6XX_CP_2D_EVENT_START_STATE_ID__SHIFT',
'A6XX_CP_APRIV_CNTL_CDREAD', 'A6XX_CP_APRIV_CNTL_CDWRITE',
'A6XX_CP_APRIV_CNTL_ICACHE', 'A6XX_CP_APRIV_CNTL_RBFETCH',
'A6XX_CP_APRIV_CNTL_RBPRIVLEVEL', 'A6XX_CP_APRIV_CNTL_RBRPWB',
'A6XX_CP_CP2GMU_STATUS_IFPC',
'A6XX_CP_DRAW_INDIRECT_MULTI_0_GS_ENABLE',
'A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE__MASK',
'A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE__SHIFT',
'A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE__MASK',
'A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE__SHIFT',
'A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE__MASK',
'A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE__SHIFT',
'A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT__MASK',
'A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT__SHIFT',
'A6XX_CP_DRAW_INDIRECT_MULTI_0_TESS_ENABLE',
'A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL__MASK',
'A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL__SHIFT',
'A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__MASK',
'A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__SHIFT',
'A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE__MASK',
'A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE__SHIFT',
'A6XX_CP_EVENT_END_STATE_ID__MASK',
'A6XX_CP_EVENT_END_STATE_ID__SHIFT',
'A6XX_CP_EVENT_START_STATE_ID__MASK',
'A6XX_CP_EVENT_START_STATE_ID__SHIFT', 'A6XX_CP_INT_CP_AHB_ERROR',
'A6XX_CP_INT_CP_HW_FAULT_ERROR',
'A6XX_CP_INT_CP_HW_FAULT_ERROR_BV',
'A6XX_CP_INT_CP_HW_FAULT_ERROR_LPAC',
'A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR',
'A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR_BV',
'A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR_LPAC',
'A6XX_CP_INT_CP_OPCODE_ERROR', 'A6XX_CP_INT_CP_OPCODE_ERROR_BV',
'A6XX_CP_INT_CP_OPCODE_ERROR_LPAC',
'A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR',
'A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR_BV',
'A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR_LPAC',
'A6XX_CP_INT_CP_UCODE_ERROR', 'A6XX_CP_INT_CP_UCODE_ERROR_BV',
'A6XX_CP_INT_CP_UCODE_ERROR_LPAC',
'A6XX_CP_INT_CP_VSD_PARITY_ERROR',
'A6XX_CP_PROTECT_CNTL_ACCESS_FAULT_ON_VIOL_EN',
'A6XX_CP_PROTECT_CNTL_ACCESS_PROT_EN',
'A6XX_CP_PROTECT_CNTL_LAST_SPAN_INF_RANGE',
'A6XX_CP_PROTECT_REG_BASE_ADDR__MASK',
'A6XX_CP_PROTECT_REG_BASE_ADDR__SHIFT',
'A6XX_CP_PROTECT_REG_MASK_LEN__MASK',
'A6XX_CP_PROTECT_REG_MASK_LEN__SHIFT', 'A6XX_CP_PROTECT_REG_READ',
'A6XX_CP_REG_TEST_0_BIT__MASK', 'A6XX_CP_REG_TEST_0_BIT__SHIFT',
'A6XX_CP_REG_TEST_0_PRED_BIT__MASK',
'A6XX_CP_REG_TEST_0_PRED_BIT__SHIFT',
'A6XX_CP_REG_TEST_0_PRED_UPDATE', 'A6XX_CP_REG_TEST_0_REG__MASK',
'A6XX_CP_REG_TEST_0_REG__SHIFT',
'A6XX_CP_REG_TEST_0_SCRATCH_MEM_OFFSET__MASK',
'A6XX_CP_REG_TEST_0_SCRATCH_MEM_OFFSET__SHIFT',
'A6XX_CP_REG_TEST_0_SKIP_WAIT_FOR_ME',
'A6XX_CP_REG_TEST_0_SOURCE__MASK',
'A6XX_CP_REG_TEST_0_SOURCE__SHIFT',
'A6XX_CP_ROQ_AVAIL_IB1_REM__MASK',
'A6XX_CP_ROQ_AVAIL_IB1_REM__SHIFT',
'A6XX_CP_ROQ_AVAIL_IB2_REM__MASK',
'A6XX_CP_ROQ_AVAIL_IB2_REM__SHIFT',
'A6XX_CP_ROQ_AVAIL_MRB_REM__MASK',
'A6XX_CP_ROQ_AVAIL_MRB_REM__SHIFT',
'A6XX_CP_ROQ_AVAIL_RB_REM__MASK',
'A6XX_CP_ROQ_AVAIL_RB_REM__SHIFT',
'A6XX_CP_ROQ_AVAIL_SDS_REM__MASK',
'A6XX_CP_ROQ_AVAIL_SDS_REM__SHIFT',
'A6XX_CP_ROQ_AVAIL_VSD_REM__MASK',
'A6XX_CP_ROQ_AVAIL_VSD_REM__SHIFT',
'A6XX_CP_ROQ_IB1_STAT_RPTR__MASK',
'A6XX_CP_ROQ_IB1_STAT_RPTR__SHIFT',
'A6XX_CP_ROQ_IB1_STAT_WPTR__MASK',
'A6XX_CP_ROQ_IB1_STAT_WPTR__SHIFT',
'A6XX_CP_ROQ_IB2_STAT_RPTR__MASK',
'A6XX_CP_ROQ_IB2_STAT_RPTR__SHIFT',
'A6XX_CP_ROQ_IB2_STAT_WPTR__MASK',
'A6XX_CP_ROQ_IB2_STAT_WPTR__SHIFT',
'A6XX_CP_ROQ_MRB_STAT_RPTR__MASK',
'A6XX_CP_ROQ_MRB_STAT_RPTR__SHIFT',
'A6XX_CP_ROQ_MRB_STAT_WPTR__MASK',
'A6XX_CP_ROQ_MRB_STAT_WPTR__SHIFT',
'A6XX_CP_ROQ_RB_STAT_RPTR__MASK',
'A6XX_CP_ROQ_RB_STAT_RPTR__SHIFT',
'A6XX_CP_ROQ_RB_STAT_WPTR__MASK',
'A6XX_CP_ROQ_RB_STAT_WPTR__SHIFT',
'A6XX_CP_ROQ_SDS_STAT_RPTR__MASK',
'A6XX_CP_ROQ_SDS_STAT_RPTR__SHIFT',
'A6XX_CP_ROQ_SDS_STAT_WPTR__MASK',
'A6XX_CP_ROQ_SDS_STAT_WPTR__SHIFT',
'A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__MASK',
'A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__SHIFT',
'A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__MASK',
'A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__SHIFT',
'A6XX_CP_ROQ_THRESHOLDS_1_MRB_START__MASK',
'A6XX_CP_ROQ_THRESHOLDS_1_MRB_START__SHIFT',
'A6XX_CP_ROQ_THRESHOLDS_1_VSD_START__MASK',
'A6XX_CP_ROQ_THRESHOLDS_1_VSD_START__SHIFT',
'A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__MASK',
'A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__SHIFT',
'A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__MASK',
'A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__SHIFT',
'A6XX_CP_ROQ_VSD_STAT_RPTR__MASK',
'A6XX_CP_ROQ_VSD_STAT_RPTR__SHIFT',
'A6XX_CP_ROQ_VSD_STAT_WPTR__MASK',
'A6XX_CP_ROQ_VSD_STAT_WPTR__SHIFT',
'A6XX_CP_SET_MARKER_0_MARKER__MASK',
'A6XX_CP_SET_MARKER_0_MARKER__SHIFT',
'A6XX_CP_SET_MARKER_0_MODE__MASK',
'A6XX_CP_SET_MARKER_0_MODE__SHIFT',
'A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__MASK',
'A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__SHIFT',
'A6XX_CP_SET_PSEUDO_REG__1_LO__MASK',
'A6XX_CP_SET_PSEUDO_REG__1_LO__SHIFT',
'A6XX_CP_SET_PSEUDO_REG__2_HI__MASK',
'A6XX_CP_SET_PSEUDO_REG__2_HI__SHIFT',
'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK',
'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT',
'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK',
'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT',
'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK',
'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT',
'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK',
'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT',
'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK',
'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT',
'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK',
'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT',
'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK',
'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT',
'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK',
'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT',
'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK',
'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT',
'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK',
'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT',
'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK',
'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT',
'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK',
'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT',
'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK',
'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT',
'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK',
'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT',
'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK',
'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT',
'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK',
'A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT',
'A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK',
'A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT',
'A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK',
'A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT',
'A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK',
'A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT',
'A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK',
'A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT',
'A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__MASK',
'A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__SHIFT',
'A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__MASK',
'A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__SHIFT',
'A6XX_DBGBUS_A2D', 'A6XX_DBGBUS_CCUFCHE', 'A6XX_DBGBUS_CCU_0',
'A6XX_DBGBUS_CCU_1', 'A6XX_DBGBUS_CCU_2', 'A6XX_DBGBUS_COM',
'A6XX_DBGBUS_CP', 'A6XX_DBGBUS_CX', 'A6XX_DBGBUS_DBGC',
'A6XX_DBGBUS_DCS', 'A6XX_DBGBUS_DPM', 'A6XX_DBGBUS_GBIF_GX',
'A6XX_DBGBUS_GMU_CX', 'A6XX_DBGBUS_GMU_GX', 'A6XX_DBGBUS_GPC',
'A6XX_DBGBUS_HLSQ', 'A6XX_DBGBUS_HLSQ_SPTP', 'A6XX_DBGBUS_LARC',
'A6XX_DBGBUS_LRZ', 'A6XX_DBGBUS_PC', 'A6XX_DBGBUS_RAS',
'A6XX_DBGBUS_RBBM', 'A6XX_DBGBUS_RBP', 'A6XX_DBGBUS_RB_0',
'A6XX_DBGBUS_RB_1', 'A6XX_DBGBUS_RB_2', 'A6XX_DBGBUS_SPTP_0',
'A6XX_DBGBUS_SPTP_1', 'A6XX_DBGBUS_SPTP_2', 'A6XX_DBGBUS_SPTP_3',
'A6XX_DBGBUS_SPTP_4', 'A6XX_DBGBUS_SPTP_5', 'A6XX_DBGBUS_SP_0',
'A6XX_DBGBUS_SP_1', 'A6XX_DBGBUS_SP_2', 'A6XX_DBGBUS_TESS',
'A6XX_DBGBUS_TPFCHE', 'A6XX_DBGBUS_TPL1_0', 'A6XX_DBGBUS_TPL1_1',
'A6XX_DBGBUS_TPL1_2', 'A6XX_DBGBUS_TPL1_3', 'A6XX_DBGBUS_TPL1_4',
'A6XX_DBGBUS_TPL1_5', 'A6XX_DBGBUS_TSE', 'A6XX_DBGBUS_UCHE',
'A6XX_DBGBUS_UCHE_WRAPPER', 'A6XX_DBGBUS_VBIF',
'A6XX_DBGBUS_VFDP', 'A6XX_DBGBUS_VFD_0', 'A6XX_DBGBUS_VFD_1',
'A6XX_DBGBUS_VFD_2', 'A6XX_DBGBUS_VFD_3', 'A6XX_DBGBUS_VFD_4',
'A6XX_DBGBUS_VFD_5', 'A6XX_DBGBUS_VPC', 'A6XX_DBGBUS_VSC',
'A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK',
'A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT',
'A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK',
'A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT',
'A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK',
'A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT',
'A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK',
'A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT',
'A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK',
'A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT',
'A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK',
'A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT',
'A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK',
'A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT',
'A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK',
'A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT',
'A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK',
'A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT',
'A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK',
'A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT',
'A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK',
'A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT',
'A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK',
'A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT',
'A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK',
'A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT',
'A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK',
'A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT',
'A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK',
'A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT',
'A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK',
'A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT',
'A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK',
'A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT',
'A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK',
'A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT',
'A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK',
'A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT',
'A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK',
'A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT',
'A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__MASK',
'A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__SHIFT',
'A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__MASK',
'A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__SHIFT',
'A6XX_EARLY_LRZ_LATE_Z', 'A6XX_EARLY_Z',
'A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__MASK',
'A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT',
'A6XX_GRAS_2D_BLIT_CNTL_D24S8',
'A6XX_GRAS_2D_BLIT_CNTL_IFMT__MASK',
'A6XX_GRAS_2D_BLIT_CNTL_IFMT__SHIFT',
'A6XX_GRAS_2D_BLIT_CNTL_MASK__MASK',
'A6XX_GRAS_2D_BLIT_CNTL_MASK__SHIFT',
'A6XX_GRAS_2D_BLIT_CNTL_OVERWRITEEN',
'A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE__MASK',
'A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE__SHIFT',
'A6XX_GRAS_2D_BLIT_CNTL_ROTATE__MASK',
'A6XX_GRAS_2D_BLIT_CNTL_ROTATE__SHIFT',
'A6XX_GRAS_2D_BLIT_CNTL_SCISSOR',
'A6XX_GRAS_2D_BLIT_CNTL_SOLID_COLOR',
'A6XX_GRAS_2D_BLIT_CNTL_UNK17__MASK',
'A6XX_GRAS_2D_BLIT_CNTL_UNK17__SHIFT',
'A6XX_GRAS_2D_BLIT_CNTL_UNK30',
'A6XX_GRAS_2D_BLIT_CNTL_UNK4__MASK',
'A6XX_GRAS_2D_BLIT_CNTL_UNK4__SHIFT',
'A6XX_GRAS_2D_DST_BR_X__MASK', 'A6XX_GRAS_2D_DST_BR_X__SHIFT',
'A6XX_GRAS_2D_DST_BR_Y__MASK', 'A6XX_GRAS_2D_DST_BR_Y__SHIFT',
'A6XX_GRAS_2D_DST_TL_X__MASK', 'A6XX_GRAS_2D_DST_TL_X__SHIFT',
'A6XX_GRAS_2D_DST_TL_Y__MASK', 'A6XX_GRAS_2D_DST_TL_Y__SHIFT',
'A6XX_GRAS_2D_RESOLVE_CNTL_1_X__MASK',
'A6XX_GRAS_2D_RESOLVE_CNTL_1_X__SHIFT',
'A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__MASK',
'A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__SHIFT',
'A6XX_GRAS_2D_RESOLVE_CNTL_2_X__MASK',
'A6XX_GRAS_2D_RESOLVE_CNTL_2_X__SHIFT',
'A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__MASK',
'A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__SHIFT',
'A6XX_GRAS_2D_SRC_BR_X__MASK', 'A6XX_GRAS_2D_SRC_BR_X__SHIFT',
'A6XX_GRAS_2D_SRC_BR_Y__MASK', 'A6XX_GRAS_2D_SRC_BR_Y__SHIFT',
'A6XX_GRAS_2D_SRC_TL_X__MASK', 'A6XX_GRAS_2D_SRC_TL_X__SHIFT',
'A6XX_GRAS_2D_SRC_TL_Y__MASK', 'A6XX_GRAS_2D_SRC_TL_Y__SHIFT',
'A6XX_GRAS_BIN_CONTROL_BINH__MASK',
'A6XX_GRAS_BIN_CONTROL_BINH__SHIFT',
'A6XX_GRAS_BIN_CONTROL_BINW__MASK',
'A6XX_GRAS_BIN_CONTROL_BINW__SHIFT',
'A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION__MASK',
'A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION__SHIFT',
'A6XX_GRAS_BIN_CONTROL_FORCE_LRZ_WRITE_DIS',
'A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK',
'A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT',
'A6XX_GRAS_BIN_CONTROL_RENDER_MODE__MASK',
'A6XX_GRAS_BIN_CONTROL_RENDER_MODE__SHIFT',
'A6XX_GRAS_BIN_CONTROL_UNK27', 'A6XX_GRAS_CL_CNTL_CLIP_DISABLE',
'A6XX_GRAS_CL_CNTL_PERSP_DIVISION_DISABLE',
'A6XX_GRAS_CL_CNTL_VP_CLIP_CODE_IGNORE',
'A6XX_GRAS_CL_CNTL_VP_XFORM_DISABLE',
'A6XX_GRAS_CL_CNTL_ZERO_GB_SCALE_Z',
'A6XX_GRAS_CL_CNTL_ZFAR_CLIP_DISABLE',
'A6XX_GRAS_CL_CNTL_ZNEAR_CLIP_DISABLE',
'A6XX_GRAS_CL_CNTL_Z_CLAMP_ENABLE',
'A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK',
'A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT',
'A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK',
'A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT',
'A6XX_GRAS_CL_VPORT_XOFFSET__MASK',
'A6XX_GRAS_CL_VPORT_XOFFSET__SHIFT',
'A6XX_GRAS_CL_VPORT_XSCALE__MASK',
'A6XX_GRAS_CL_VPORT_XSCALE__SHIFT',
'A6XX_GRAS_CL_VPORT_YOFFSET__MASK',
'A6XX_GRAS_CL_VPORT_YOFFSET__SHIFT',
'A6XX_GRAS_CL_VPORT_YSCALE__MASK',
'A6XX_GRAS_CL_VPORT_YSCALE__SHIFT',
'A6XX_GRAS_CL_VPORT_ZOFFSET__MASK',
'A6XX_GRAS_CL_VPORT_ZOFFSET__SHIFT',
'A6XX_GRAS_CL_VPORT_ZSCALE__MASK',
'A6XX_GRAS_CL_VPORT_ZSCALE__SHIFT',
'A6XX_GRAS_CL_Z_CLAMP_MAX__MASK',
'A6XX_GRAS_CL_Z_CLAMP_MAX__SHIFT',
'A6XX_GRAS_CL_Z_CLAMP_MIN__MASK',
'A6XX_GRAS_CL_Z_CLAMP_MIN__SHIFT',
'A6XX_GRAS_CNTL_COORD_MASK__MASK',
'A6XX_GRAS_CNTL_COORD_MASK__SHIFT',
'A6XX_GRAS_CNTL_IJ_LINEAR_CENTROID',
'A6XX_GRAS_CNTL_IJ_LINEAR_PIXEL',
'A6XX_GRAS_CNTL_IJ_LINEAR_SAMPLE',
'A6XX_GRAS_CNTL_IJ_PERSP_CENTROID',
'A6XX_GRAS_CNTL_IJ_PERSP_PIXEL', 'A6XX_GRAS_CNTL_IJ_PERSP_SAMPLE',
'A6XX_GRAS_CNTL_UNK10', 'A6XX_GRAS_CNTL_UNK11',
'A6XX_GRAS_DBG_ECO_CNTL_LRZCACHELOCKDIS',
'A6XX_GRAS_DBG_ECO_CNTL_UNK7',
'A6XX_GRAS_DEST_MSAA_CNTL_MSAA_DISABLE',
'A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__MASK',
'A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__SHIFT',
'A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__MASK',
'A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__SHIFT',
'A6XX_GRAS_DS_CL_CNTL_CULL_MASK__MASK',
'A6XX_GRAS_DS_CL_CNTL_CULL_MASK__SHIFT',
'A6XX_GRAS_DS_LAYER_CNTL_WRITES_LAYER',
'A6XX_GRAS_DS_LAYER_CNTL_WRITES_VIEW',
'A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__MASK',
'A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__SHIFT',
'A6XX_GRAS_GS_CL_CNTL_CULL_MASK__MASK',
'A6XX_GRAS_GS_CL_CNTL_CULL_MASK__SHIFT',
'A6XX_GRAS_GS_LAYER_CNTL_WRITES_LAYER',
'A6XX_GRAS_GS_LAYER_CNTL_WRITES_VIEW',
'A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK',
'A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT',
'A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__MASK',
'A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__SHIFT',
'A6XX_GRAS_LRZ_CNTL_DIR_WRITE', 'A6XX_GRAS_LRZ_CNTL_DIR__MASK',
'A6XX_GRAS_LRZ_CNTL_DIR__SHIFT',
'A6XX_GRAS_LRZ_CNTL_DISABLE_ON_WRONG_DIR',
'A6XX_GRAS_LRZ_CNTL_ENABLE', 'A6XX_GRAS_LRZ_CNTL_FC_ENABLE',
'A6XX_GRAS_LRZ_CNTL_GREATER', 'A6XX_GRAS_LRZ_CNTL_LRZ_WRITE',
'A6XX_GRAS_LRZ_CNTL_Z_BOUNDS_ENABLE',
'A6XX_GRAS_LRZ_CNTL_Z_FUNC__MASK',
'A6XX_GRAS_LRZ_CNTL_Z_FUNC__SHIFT',
'A6XX_GRAS_LRZ_CNTL_Z_TEST_ENABLE',
'A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_LAYER__MASK',
'A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_LAYER__SHIFT',
'A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_MIP_LEVEL__MASK',
'A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_MIP_LEVEL__SHIFT',
'A6XX_GRAS_LRZ_DEPTH_VIEW_LAYER_COUNT__MASK',
'A6XX_GRAS_LRZ_DEPTH_VIEW_LAYER_COUNT__SHIFT',
'A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT__MASK',
'A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT__SHIFT',
'A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE__MASK',
'A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE__SHIFT',
'A6XX_GRAS_LRZ_PS_INPUT_CNTL_SAMPLEID',
'A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__MASK',
'A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__SHIFT',
'A6XX_GRAS_RAS_MSAA_CNTL_UNK2', 'A6XX_GRAS_RAS_MSAA_CNTL_UNK3',
'A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE',
'A6XX_GRAS_SAMPLE_CONFIG_LOCATION_ENABLE',
'A6XX_GRAS_SAMPLE_CONFIG_UNK0',
'A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK',
'A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT',
'A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK',
'A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT',
'A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK',
'A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT',
'A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK',
'A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT',
'A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK',
'A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT',
'A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK',
'A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT',
'A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK',
'A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT',
'A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK',
'A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT',
'A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK',
'A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT',
'A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK',
'A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT',
'A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK',
'A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT',
'A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK',
'A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT',
'A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK',
'A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT',
'A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK',
'A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT',
'A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK',
'A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT',
'A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK',
'A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT',
'A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE__MASK',
'A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE__SHIFT',
'A6XX_GRAS_SC_CNTL_EARLYVIZOUTEN',
'A6XX_GRAS_SC_CNTL_RASTER_DIRECTION__MASK',
'A6XX_GRAS_SC_CNTL_RASTER_DIRECTION__SHIFT',
'A6XX_GRAS_SC_CNTL_RASTER_MODE__MASK',
'A6XX_GRAS_SC_CNTL_RASTER_MODE__SHIFT',
'A6XX_GRAS_SC_CNTL_ROTATION__MASK',
'A6XX_GRAS_SC_CNTL_ROTATION__SHIFT',
'A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION__MASK',
'A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION__SHIFT',
'A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE__MASK',
'A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE__SHIFT',
'A6XX_GRAS_SC_CNTL_UNK9',
'A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK',
'A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT',
'A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK',
'A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT',
'A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK',
'A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT',
'A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK',
'A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT',
'A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__MASK',
'A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__SHIFT',
'A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__MASK',
'A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__SHIFT',
'A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__MASK',
'A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__SHIFT',
'A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__MASK',
'A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__SHIFT',
'A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK',
'A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT',
'A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK',
'A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT',
'A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK',
'A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT',
'A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK',
'A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT',
'A6XX_GRAS_SU_CNTL_CULL_BACK', 'A6XX_GRAS_SU_CNTL_CULL_FRONT',
'A6XX_GRAS_SU_CNTL_FRONT_CW',
'A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK',
'A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT',
'A6XX_GRAS_SU_CNTL_LINE_MODE__MASK',
'A6XX_GRAS_SU_CNTL_LINE_MODE__SHIFT',
'A6XX_GRAS_SU_CNTL_MULTIVIEW_ENABLE',
'A6XX_GRAS_SU_CNTL_POLY_OFFSET',
'A6XX_GRAS_SU_CNTL_RENDERTARGETINDEXINCR',
'A6XX_GRAS_SU_CNTL_UNK12', 'A6XX_GRAS_SU_CNTL_UNK15__MASK',
'A6XX_GRAS_SU_CNTL_UNK15__SHIFT', 'A6XX_GRAS_SU_CNTL_UNK20__MASK',
'A6XX_GRAS_SU_CNTL_UNK20__SHIFT',
'A6XX_GRAS_SU_CNTL_VIEWPORTINDEXINCR',
'A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_CONSERVATIVERASEN',
'A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_INNERCONSERVATIVERASEN',
'A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT__MASK',
'A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT__SHIFT',
'A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4__MASK',
'A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4__SHIFT',
'A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK',
'A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT',
'A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3',
'A6XX_GRAS_SU_DEPTH_CNTL_Z_TEST_ENABLE',
'A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__MASK',
'A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__SHIFT',
'A6XX_GRAS_SU_PATH_RENDERING_CNTL_LINELENGTHEN',
'A6XX_GRAS_SU_PATH_RENDERING_CNTL_UNK0',
'A6XX_GRAS_SU_POINT_MINMAX_MAX__MASK',
'A6XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT',
'A6XX_GRAS_SU_POINT_MINMAX_MIN__MASK',
'A6XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT',
'A6XX_GRAS_SU_POINT_SIZE__MASK', 'A6XX_GRAS_SU_POINT_SIZE__SHIFT',
'A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK',
'A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT',
'A6XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK',
'A6XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT',
'A6XX_GRAS_SU_POLY_OFFSET_SCALE__MASK',
'A6XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT',
'A6XX_GRAS_SU_STENCIL_CNTL_STENCIL_ENABLE',
'A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__MASK',
'A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__SHIFT',
'A6XX_GRAS_VS_CL_CNTL_CULL_MASK__MASK',
'A6XX_GRAS_VS_CL_CNTL_CULL_MASK__SHIFT',
'A6XX_GRAS_VS_LAYER_CNTL_WRITES_LAYER',
'A6XX_GRAS_VS_LAYER_CNTL_WRITES_VIEW',
'A6XX_HLSQ_2D_EVENT_CMD_EVENT__MASK',
'A6XX_HLSQ_2D_EVENT_CMD_EVENT__SHIFT',
'A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__MASK',
'A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__SHIFT',
'A6XX_HLSQ_BACKEND_META',
'A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK',
'A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT',
'A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK',
'A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT',
'A6XX_HLSQ_CHUNK_CPS_RAM', 'A6XX_HLSQ_CHUNK_CPS_RAM_TAG',
'A6XX_HLSQ_CHUNK_CVS_RAM', 'A6XX_HLSQ_CHUNK_CVS_RAM_TAG',
'A6XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK',
'A6XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT',
'A6XX_HLSQ_CONTROL_2_REG_CENTERRHW__MASK',
'A6XX_HLSQ_CONTROL_2_REG_CENTERRHW__SHIFT',
'A6XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK',
'A6XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT',
'A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK',
'A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT',
'A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK',
'A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT',
'A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK',
'A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT',
'A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK',
'A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT',
'A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK',
'A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT',
'A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK',
'A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT',
'A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK',
'A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT',
'A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK',
'A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT',
'A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK',
'A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT',
'A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK',
'A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT',
'A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__MASK',
'A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__SHIFT',
'A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__MASK',
'A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__SHIFT',
'A6XX_HLSQ_CPS_MISC_RAM', 'A6XX_HLSQ_CPS_MISC_RAM_TAG',
'A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK',
'A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT',
'A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK',
'A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT',
'A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK',
'A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT',
'A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK',
'A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT',
'A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__MASK',
'A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__SHIFT',
'A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__MASK',
'A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__SHIFT',
'A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__MASK',
'A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT',
'A6XX_HLSQ_CS_CNTL_1_SINGLE_SP_CORE',
'A6XX_HLSQ_CS_CNTL_1_THREADSIZE_SCALAR',
'A6XX_HLSQ_CS_CNTL_1_THREADSIZE__MASK',
'A6XX_HLSQ_CS_CNTL_1_THREADSIZE__SHIFT',
'A6XX_HLSQ_CS_CNTL_CONSTLEN__MASK',
'A6XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT', 'A6XX_HLSQ_CS_CNTL_ENABLED',
'A6XX_HLSQ_CS_CNTL_READ_IMM_SHARED_CONSTS',
'A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK',
'A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT',
'A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK',
'A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT',
'A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK',
'A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT',
'A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK',
'A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT',
'A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK',
'A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT',
'A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK',
'A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT',
'A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK',
'A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT',
'A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK',
'A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT',
'A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK',
'A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT',
'A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK',
'A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT',
'A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE__MASK',
'A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE__SHIFT',
'A6XX_HLSQ_CS_UNKNOWN_B9D0_UNK5',
'A6XX_HLSQ_CS_UNKNOWN_B9D0_UNK6', 'A6XX_HLSQ_CVS_MISC_RAM',
'A6XX_HLSQ_CVS_MISC_RAM_TAG', 'A6XX_HLSQ_DATAPATH_META',
'A6XX_HLSQ_DISPATCH_CMD_STATE_ID__MASK',
'A6XX_HLSQ_DISPATCH_CMD_STATE_ID__SHIFT',
'A6XX_HLSQ_DRAW_CMD_STATE_ID__MASK',
'A6XX_HLSQ_DRAW_CMD_STATE_ID__SHIFT',
'A6XX_HLSQ_DS_CNTL_CONSTLEN__MASK',
'A6XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT', 'A6XX_HLSQ_DS_CNTL_ENABLED',
'A6XX_HLSQ_DS_CNTL_READ_IMM_SHARED_CONSTS',
'A6XX_HLSQ_EVENT_CMD_EVENT__MASK',
'A6XX_HLSQ_EVENT_CMD_EVENT__SHIFT',
'A6XX_HLSQ_EVENT_CMD_STATE_ID__MASK',
'A6XX_HLSQ_EVENT_CMD_STATE_ID__SHIFT', 'A6XX_HLSQ_FRONTEND_META',
'A6XX_HLSQ_FS_CNTL_0_THREADSIZE__MASK',
'A6XX_HLSQ_FS_CNTL_0_THREADSIZE__SHIFT',
'A6XX_HLSQ_FS_CNTL_0_UNK2__MASK',
'A6XX_HLSQ_FS_CNTL_0_UNK2__SHIFT', 'A6XX_HLSQ_FS_CNTL_0_VARYINGS',
'A6XX_HLSQ_FS_CNTL_CONSTLEN__MASK',
'A6XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT', 'A6XX_HLSQ_FS_CNTL_ENABLED',
'A6XX_HLSQ_FS_CNTL_READ_IMM_SHARED_CONSTS',
'A6XX_HLSQ_GFX_CPS_CONST_RAM', 'A6XX_HLSQ_GFX_CPS_CONST_RAM_TAG',
'A6XX_HLSQ_GFX_CVS_CONST_RAM', 'A6XX_HLSQ_GFX_CVS_CONST_RAM_TAG',
'A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK',
'A6XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT', 'A6XX_HLSQ_GS_CNTL_ENABLED',
'A6XX_HLSQ_GS_CNTL_READ_IMM_SHARED_CONSTS',
'A6XX_HLSQ_HS_CNTL_CONSTLEN__MASK',
'A6XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT', 'A6XX_HLSQ_HS_CNTL_ENABLED',
'A6XX_HLSQ_HS_CNTL_READ_IMM_SHARED_CONSTS',
'A6XX_HLSQ_ICB_CPS_CB_BASE_TAG', 'A6XX_HLSQ_ICB_CVS_CB_BASE_TAG',
'A6XX_HLSQ_INDIRECT_META', 'A6XX_HLSQ_INST_RAM',
'A6XX_HLSQ_INST_RAM_1', 'A6XX_HLSQ_INST_RAM_TAG',
'A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__MASK',
'A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__SHIFT',
'A6XX_HLSQ_INVALIDATE_CMD_CS_IBO',
'A6XX_HLSQ_INVALIDATE_CMD_CS_SHARED_CONST',
'A6XX_HLSQ_INVALIDATE_CMD_CS_STATE',
'A6XX_HLSQ_INVALIDATE_CMD_DS_STATE',
'A6XX_HLSQ_INVALIDATE_CMD_FS_STATE',
'A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__MASK',
'A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__SHIFT',
'A6XX_HLSQ_INVALIDATE_CMD_GFX_IBO',
'A6XX_HLSQ_INVALIDATE_CMD_GFX_SHARED_CONST',
'A6XX_HLSQ_INVALIDATE_CMD_GS_STATE',
'A6XX_HLSQ_INVALIDATE_CMD_HS_STATE',
'A6XX_HLSQ_INVALIDATE_CMD_VS_STATE', 'A6XX_HLSQ_PWR_REST_RAM',
'A6XX_HLSQ_PWR_REST_TAG', 'A6XX_HLSQ_SHARED_CONSTS_ENABLE',
'A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK',
'A6XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT', 'A6XX_HLSQ_VS_CNTL_ENABLED',
'A6XX_HLSQ_VS_CNTL_READ_IMM_SHARED_CONSTS', 'A6XX_INVALID_ZTEST',
'A6XX_LATE_Z', 'A6XX_PC_2D_EVENT_CMD_EVENT__MASK',
'A6XX_PC_2D_EVENT_CMD_EVENT__SHIFT',
'A6XX_PC_2D_EVENT_CMD_STATE_ID__MASK',
'A6XX_PC_2D_EVENT_CMD_STATE_ID__SHIFT',
'A6XX_PC_DGEN_SU_CONSERVATIVE_RAS_CNTL_CONSERVATIVERASEN',
'A6XX_PC_DISPATCH_CMD_STATE_ID__MASK',
'A6XX_PC_DISPATCH_CMD_STATE_ID__SHIFT',
'A6XX_PC_DRAW_CMD_STATE_ID__MASK',
'A6XX_PC_DRAW_CMD_STATE_ID__SHIFT',
'A6XX_PC_DRAW_INITIATOR_GS_ENABLE',
'A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__MASK',
'A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__SHIFT',
'A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__MASK',
'A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__SHIFT',
'A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__MASK',
'A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__SHIFT',
'A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__MASK',
'A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__SHIFT',
'A6XX_PC_DRAW_INITIATOR_TESS_ENABLE',
'A6XX_PC_DRAW_INITIATOR_VIS_CULL__MASK',
'A6XX_PC_DRAW_INITIATOR_VIS_CULL__SHIFT',
'A6XX_PC_DS_OUT_CNTL_CLIP_MASK__MASK',
'A6XX_PC_DS_OUT_CNTL_CLIP_MASK__SHIFT',
'A6XX_PC_DS_OUT_CNTL_LAYER', 'A6XX_PC_DS_OUT_CNTL_PRIMITIVE_ID',
'A6XX_PC_DS_OUT_CNTL_PSIZE', 'A6XX_PC_DS_OUT_CNTL_SHADINGRATE',
'A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__MASK',
'A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__SHIFT',
'A6XX_PC_DS_OUT_CNTL_VIEW', 'A6XX_PC_EVENT_CMD_EVENT__MASK',
'A6XX_PC_EVENT_CMD_EVENT__SHIFT',
'A6XX_PC_EVENT_CMD_STATE_ID__MASK',
'A6XX_PC_EVENT_CMD_STATE_ID__SHIFT',
'A6XX_PC_GS_OUT_CNTL_CLIP_MASK__MASK',
'A6XX_PC_GS_OUT_CNTL_CLIP_MASK__SHIFT',
'A6XX_PC_GS_OUT_CNTL_LAYER', 'A6XX_PC_GS_OUT_CNTL_PRIMITIVE_ID',
'A6XX_PC_GS_OUT_CNTL_PSIZE', 'A6XX_PC_GS_OUT_CNTL_SHADINGRATE',
'A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__MASK',
'A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__SHIFT',
'A6XX_PC_GS_OUT_CNTL_VIEW', 'A6XX_PC_HS_INPUT_SIZE_SIZE__MASK',
'A6XX_PC_HS_INPUT_SIZE_SIZE__SHIFT',
'A6XX_PC_HS_INPUT_SIZE_UNK13',
'A6XX_PC_HS_OUT_CNTL_CLIP_MASK__MASK',
'A6XX_PC_HS_OUT_CNTL_CLIP_MASK__SHIFT',
'A6XX_PC_HS_OUT_CNTL_LAYER', 'A6XX_PC_HS_OUT_CNTL_PRIMITIVE_ID',
'A6XX_PC_HS_OUT_CNTL_PSIZE', 'A6XX_PC_HS_OUT_CNTL_SHADINGRATE',
'A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC__MASK',
'A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC__SHIFT',
'A6XX_PC_HS_OUT_CNTL_VIEW',
'A6XX_PC_MULTIVIEW_CNTL_DISABLEMULTIPOS',
'A6XX_PC_MULTIVIEW_CNTL_ENABLE',
'A6XX_PC_MULTIVIEW_CNTL_VIEWS__MASK',
'A6XX_PC_MULTIVIEW_CNTL_VIEWS__SHIFT',
'A6XX_PC_POLYGON_MODE_MODE__MASK',
'A6XX_PC_POLYGON_MODE_MODE__SHIFT',
'A6XX_PC_PRIMITIVE_CNTL_0_D3D_VERTEX_ORDERING',
'A6XX_PC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART',
'A6XX_PC_PRIMITIVE_CNTL_0_PROVOKING_VTX_LAST',
'A6XX_PC_PRIMITIVE_CNTL_0_UNK3',
'A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__MASK',
'A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__SHIFT',
'A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__MASK',
'A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__SHIFT',
'A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__MASK',
'A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__SHIFT',
'A6XX_PC_PRIMITIVE_CNTL_5_LINELENGTHEN',
'A6XX_PC_PRIMITIVE_CNTL_5_UNK18',
'A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__MASK',
'A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__SHIFT',
'A6XX_PC_PS_CNTL_PRIMITIVEIDEN', 'A6XX_PC_RASTER_CNTL_DISCARD',
'A6XX_PC_RASTER_CNTL_STREAM__MASK',
'A6XX_PC_RASTER_CNTL_STREAM__SHIFT',
'A6XX_PC_SO_STREAM_CNTL_STREAM_ENABLE__MASK',
'A6XX_PC_SO_STREAM_CNTL_STREAM_ENABLE__SHIFT',
'A6XX_PC_TESS_CNTL_OUTPUT__MASK',
'A6XX_PC_TESS_CNTL_OUTPUT__SHIFT',
'A6XX_PC_TESS_CNTL_SPACING__MASK',
'A6XX_PC_TESS_CNTL_SPACING__SHIFT',
'A6XX_PC_VISIBILITY_OVERRIDE_OVERRIDE',
'A6XX_PC_VSTREAM_CONTROL_UNK0__MASK',
'A6XX_PC_VSTREAM_CONTROL_UNK0__SHIFT',
'A6XX_PC_VSTREAM_CONTROL_VSC_N__MASK',
'A6XX_PC_VSTREAM_CONTROL_VSC_N__SHIFT',
'A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__MASK',
'A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__SHIFT',
'A6XX_PC_VS_OUT_CNTL_CLIP_MASK__MASK',
'A6XX_PC_VS_OUT_CNTL_CLIP_MASK__SHIFT',
'A6XX_PC_VS_OUT_CNTL_LAYER', 'A6XX_PC_VS_OUT_CNTL_PRIMITIVE_ID',
'A6XX_PC_VS_OUT_CNTL_PSIZE', 'A6XX_PC_VS_OUT_CNTL_SHADINGRATE',
'A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__MASK',
'A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__SHIFT',
'A6XX_PC_VS_OUT_CNTL_VIEW', 'A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR',
'A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS',
'A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS_LPAC',
'A6XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_COLOR_TS',
'A6XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_DEPTH_TS',
'A6XX_RBBM_INT_0_MASK_CP_CCU_RESOLVE_TS',
'A6XX_RBBM_INT_0_MASK_CP_HW_ERROR', 'A6XX_RBBM_INT_0_MASK_CP_IB1',
'A6XX_RBBM_INT_0_MASK_CP_IB2',
'A6XX_RBBM_INT_0_MASK_CP_IPC_INTR_0',
'A6XX_RBBM_INT_0_MASK_CP_IPC_INTR_1',
'A6XX_RBBM_INT_0_MASK_CP_RB',
'A6XX_RBBM_INT_0_MASK_CP_RB_DONE_TS',
'A6XX_RBBM_INT_0_MASK_CP_SW',
'A6XX_RBBM_INT_0_MASK_CP_WT_DONE_TS',
'A6XX_RBBM_INT_0_MASK_DEBBUS_INTR_0',
'A6XX_RBBM_INT_0_MASK_DEBBUS_INTR_1',
'A6XX_RBBM_INT_0_MASK_ISDB_CPU_IRQ',
'A6XX_RBBM_INT_0_MASK_ISDB_UNDER_DEBUG',
'A6XX_RBBM_INT_0_MASK_PM4CPINTERRUPT',
'A6XX_RBBM_INT_0_MASK_PM4CPINTERRUPTLPAC',
'A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW',
'A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW',
'A6XX_RBBM_INT_0_MASK_RBBM_GPC_ERROR',
'A6XX_RBBM_INT_0_MASK_RBBM_GPU_IDLE',
'A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT',
'A6XX_RBBM_INT_0_MASK_SWFUSEVIOLATION',
'A6XX_RBBM_INT_0_MASK_TSBWRITEERROR',
'A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS',
'A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR',
'A6XX_RBBM_STATUS3_SMMU_STALLED_ON_FAULT',
'A6XX_RBBM_STATUS_A2D_BUSY', 'A6XX_RBBM_STATUS_CCU_BUSY',
'A6XX_RBBM_STATUS_COM_DCOM_BUSY',
'A6XX_RBBM_STATUS_CP_AHB_BUSY_CP_MASTER',
'A6XX_RBBM_STATUS_CP_AHB_BUSY_CX_MASTER',
'A6XX_RBBM_STATUS_CP_BUSY', 'A6XX_RBBM_STATUS_GFX_DBGC_BUSY',
'A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB',
'A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP',
'A6XX_RBBM_STATUS_HLSQ_BUSY', 'A6XX_RBBM_STATUS_LRZ_BUSY',
'A6XX_RBBM_STATUS_PC_DCALL_BUSY', 'A6XX_RBBM_STATUS_PC_VSD_BUSY',
'A6XX_RBBM_STATUS_RAS_BUSY', 'A6XX_RBBM_STATUS_RB_BUSY',
'A6XX_RBBM_STATUS_SP_BUSY', 'A6XX_RBBM_STATUS_TESS_BUSY',
'A6XX_RBBM_STATUS_TPL1_BUSY', 'A6XX_RBBM_STATUS_TSE_BUSY',
'A6XX_RBBM_STATUS_UCHE_BUSY', 'A6XX_RBBM_STATUS_VBIF_BUSY',
'A6XX_RBBM_STATUS_VFD_BUSY', 'A6XX_RBBM_STATUS_VPC_BUSY',
'A6XX_RBBM_STATUS_VSC_BUSY',
'A6XX_RBBM_WAIT_FOR_GPU_IDLE_CMD_WAIT_GPU_IDLE',
'A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__MASK',
'A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT',
'A6XX_RB_2D_BLIT_CNTL_D24S8', 'A6XX_RB_2D_BLIT_CNTL_IFMT__MASK',
'A6XX_RB_2D_BLIT_CNTL_IFMT__SHIFT',
'A6XX_RB_2D_BLIT_CNTL_MASK__MASK',
'A6XX_RB_2D_BLIT_CNTL_MASK__SHIFT',
'A6XX_RB_2D_BLIT_CNTL_OVERWRITEEN',
'A6XX_RB_2D_BLIT_CNTL_RASTER_MODE__MASK',
'A6XX_RB_2D_BLIT_CNTL_RASTER_MODE__SHIFT',
'A6XX_RB_2D_BLIT_CNTL_ROTATE__MASK',
'A6XX_RB_2D_BLIT_CNTL_ROTATE__SHIFT',
'A6XX_RB_2D_BLIT_CNTL_SCISSOR',
'A6XX_RB_2D_BLIT_CNTL_SOLID_COLOR',
'A6XX_RB_2D_BLIT_CNTL_UNK17__MASK',
'A6XX_RB_2D_BLIT_CNTL_UNK17__SHIFT', 'A6XX_RB_2D_BLIT_CNTL_UNK30',
'A6XX_RB_2D_BLIT_CNTL_UNK4__MASK',
'A6XX_RB_2D_BLIT_CNTL_UNK4__SHIFT',
'A6XX_RB_2D_DST_FLAGS_PITCH__MASK',
'A6XX_RB_2D_DST_FLAGS_PITCH__SHIFT',
'A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__MASK',
'A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__SHIFT',
'A6XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK',
'A6XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT',
'A6XX_RB_2D_DST_INFO_COLOR_SWAP__MASK',
'A6XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT',
'A6XX_RB_2D_DST_INFO_FILTER', 'A6XX_RB_2D_DST_INFO_FLAGS',
'A6XX_RB_2D_DST_INFO_SAMPLES_AVERAGE',
'A6XX_RB_2D_DST_INFO_SAMPLES__MASK',
'A6XX_RB_2D_DST_INFO_SAMPLES__SHIFT', 'A6XX_RB_2D_DST_INFO_SRGB',
'A6XX_RB_2D_DST_INFO_TILE_MODE__MASK',
'A6XX_RB_2D_DST_INFO_TILE_MODE__SHIFT',
'A6XX_RB_2D_DST_INFO_UNK17', 'A6XX_RB_2D_DST_INFO_UNK19',
'A6XX_RB_2D_DST_INFO_UNK20', 'A6XX_RB_2D_DST_INFO_UNK21',
'A6XX_RB_2D_DST_INFO_UNK22', 'A6XX_RB_2D_DST_INFO_UNK23__MASK',
'A6XX_RB_2D_DST_INFO_UNK23__SHIFT', 'A6XX_RB_2D_DST_INFO_UNK28',
'A6XX_RB_2D_DST_PITCH__MASK', 'A6XX_RB_2D_DST_PITCH__SHIFT',
'A6XX_RB_2D_DST_PLANE_PITCH__MASK',
'A6XX_RB_2D_DST_PLANE_PITCH__SHIFT',
'A6XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK',
'A6XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT',
'A6XX_RB_ALPHA_CONTROL_ALPHA_TEST',
'A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK',
'A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT',
'A6XX_RB_BIN_CONTROL2_BINH__MASK',
'A6XX_RB_BIN_CONTROL2_BINH__SHIFT',
'A6XX_RB_BIN_CONTROL2_BINW__MASK',
'A6XX_RB_BIN_CONTROL2_BINW__SHIFT',
'A6XX_RB_BIN_CONTROL_BINH__MASK',
'A6XX_RB_BIN_CONTROL_BINH__SHIFT',
'A6XX_RB_BIN_CONTROL_BINW__MASK',
'A6XX_RB_BIN_CONTROL_BINW__SHIFT',
'A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION__MASK',
'A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION__SHIFT',
'A6XX_RB_BIN_CONTROL_FORCE_LRZ_WRITE_DIS',
'A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK',
'A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT',
'A6XX_RB_BIN_CONTROL_RENDER_MODE__MASK',
'A6XX_RB_BIN_CONTROL_RENDER_MODE__SHIFT',
'A6XX_RB_BLEND_ALPHA_F32__MASK', 'A6XX_RB_BLEND_ALPHA_F32__SHIFT',
'A6XX_RB_BLEND_BLUE_F32__MASK', 'A6XX_RB_BLEND_BLUE_F32__SHIFT',
'A6XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE',
'A6XX_RB_BLEND_CNTL_ALPHA_TO_ONE',
'A6XX_RB_BLEND_CNTL_DUAL_COLOR_IN_ENABLE',
'A6XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK',
'A6XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT',
'A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND',
'A6XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK',
'A6XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT',
'A6XX_RB_BLEND_GREEN_F32__MASK', 'A6XX_RB_BLEND_GREEN_F32__SHIFT',
'A6XX_RB_BLEND_RED_F32__MASK', 'A6XX_RB_BLEND_RED_F32__SHIFT',
'A6XX_RB_BLIT_DST_ARRAY_PITCH__MASK',
'A6XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT',
'A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__MASK',
'A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__SHIFT',
'A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__MASK',
'A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__SHIFT',
'A6XX_RB_BLIT_DST_INFO_FLAGS',
'A6XX_RB_BLIT_DST_INFO_SAMPLES__MASK',
'A6XX_RB_BLIT_DST_INFO_SAMPLES__SHIFT',
'A6XX_RB_BLIT_DST_INFO_TILE_MODE__MASK',
'A6XX_RB_BLIT_DST_INFO_TILE_MODE__SHIFT',
'A6XX_RB_BLIT_DST_INFO_UNK15', 'A6XX_RB_BLIT_DST_PITCH__MASK',
'A6XX_RB_BLIT_DST_PITCH__SHIFT',
'A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__MASK',
'A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__SHIFT',
'A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__MASK',
'A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__SHIFT',
'A6XX_RB_BLIT_GMEM_MSAA_CNTL_SAMPLES__MASK',
'A6XX_RB_BLIT_GMEM_MSAA_CNTL_SAMPLES__SHIFT',
'A6XX_RB_BLIT_INFO_BUFFER_ID__MASK',
'A6XX_RB_BLIT_INFO_BUFFER_ID__SHIFT',
'A6XX_RB_BLIT_INFO_CLEAR_MASK__MASK',
'A6XX_RB_BLIT_INFO_CLEAR_MASK__SHIFT', 'A6XX_RB_BLIT_INFO_DEPTH',
'A6XX_RB_BLIT_INFO_GMEM', 'A6XX_RB_BLIT_INFO_LAST__MASK',
'A6XX_RB_BLIT_INFO_LAST__SHIFT', 'A6XX_RB_BLIT_INFO_SAMPLE_0',
'A6XX_RB_BLIT_INFO_UNK0', 'A6XX_RB_BLIT_SCISSOR_BR_X__MASK',
'A6XX_RB_BLIT_SCISSOR_BR_X__SHIFT',
'A6XX_RB_BLIT_SCISSOR_BR_Y__MASK',
'A6XX_RB_BLIT_SCISSOR_BR_Y__SHIFT',
'A6XX_RB_BLIT_SCISSOR_TL_X__MASK',
'A6XX_RB_BLIT_SCISSOR_TL_X__SHIFT',
'A6XX_RB_BLIT_SCISSOR_TL_Y__MASK',
'A6XX_RB_BLIT_SCISSOR_TL_Y__SHIFT',
'A6XX_RB_CCU_CNTL_COLOR_CACHE_SIZE__MASK',
'A6XX_RB_CCU_CNTL_COLOR_CACHE_SIZE__SHIFT',
'A6XX_RB_CCU_CNTL_COLOR_OFFSET_HI__MASK',
'A6XX_RB_CCU_CNTL_COLOR_OFFSET_HI__SHIFT',
'A6XX_RB_CCU_CNTL_COLOR_OFFSET__MASK',
'A6XX_RB_CCU_CNTL_COLOR_OFFSET__SHIFT',
'A6XX_RB_CCU_CNTL_CONCURRENT_RESOLVE',
'A6XX_RB_CCU_CNTL_DEPTH_CACHE_SIZE__MASK',
'A6XX_RB_CCU_CNTL_DEPTH_CACHE_SIZE__SHIFT',
'A6XX_RB_CCU_CNTL_DEPTH_OFFSET_HI__MASK',
'A6XX_RB_CCU_CNTL_DEPTH_OFFSET_HI__SHIFT',
'A6XX_RB_CCU_CNTL_DEPTH_OFFSET__MASK',
'A6XX_RB_CCU_CNTL_DEPTH_OFFSET__SHIFT',
'A6XX_RB_CCU_CNTL_GMEM_FAST_CLEAR_DISABLE',
'A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK',
'A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT',
'A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK',
'A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT',
'A6XX_RB_DEPTH_BUFFER_INFO_UNK3__MASK',
'A6XX_RB_DEPTH_BUFFER_INFO_UNK3__SHIFT',
'A6XX_RB_DEPTH_BUFFER_PITCH__MASK',
'A6XX_RB_DEPTH_BUFFER_PITCH__SHIFT',
'A6XX_RB_DEPTH_CNTL_ZFUNC__MASK',
'A6XX_RB_DEPTH_CNTL_ZFUNC__SHIFT',
'A6XX_RB_DEPTH_CNTL_Z_BOUNDS_ENABLE',
'A6XX_RB_DEPTH_CNTL_Z_CLAMP_ENABLE',
'A6XX_RB_DEPTH_CNTL_Z_READ_ENABLE',
'A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE',
'A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE',
'A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK',
'A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT',
'A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__MASK',
'A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__SHIFT',
'A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__MASK',
'A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__SHIFT',
'A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__MASK',
'A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__SHIFT',
'A6XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE',
'A6XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK',
'A6XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT',
'A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__MASK',
'A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__SHIFT',
'A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__MASK',
'A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__SHIFT',
'A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__MASK',
'A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__SHIFT',
'A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__MASK',
'A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__SHIFT',
'A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__MASK',
'A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__SHIFT',
'A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__MASK',
'A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__SHIFT',
'A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__MASK',
'A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__SHIFT',
'A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__MASK',
'A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__SHIFT',
'A6XX_RB_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE',
'A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK',
'A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_STENCILREF',
'A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z',
'A6XX_RB_FS_OUTPUT_CNTL1_MRT__MASK',
'A6XX_RB_FS_OUTPUT_CNTL1_MRT__SHIFT', 'A6XX_RB_LRZ_CNTL_ENABLE',
'A6XX_RB_MRT_ARRAY_PITCH__MASK', 'A6XX_RB_MRT_ARRAY_PITCH__SHIFT',
'A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK',
'A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT',
'A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK',
'A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT',
'A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK',
'A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT',
'A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK',
'A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT',
'A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK',
'A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT',
'A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK',
'A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT',
'A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK',
'A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT',
'A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK',
'A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT',
'A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK',
'A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT',
'A6XX_RB_MRT_BUF_INFO_UNK10', 'A6XX_RB_MRT_CONTROL_BLEND',
'A6XX_RB_MRT_CONTROL_BLEND2',
'A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK',
'A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT',
'A6XX_RB_MRT_CONTROL_ROP_CODE__MASK',
'A6XX_RB_MRT_CONTROL_ROP_CODE__SHIFT',
'A6XX_RB_MRT_CONTROL_ROP_ENABLE',
'A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK',
'A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT',
'A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__MASK',
'A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__SHIFT',
'A6XX_RB_MRT_PITCH__MASK', 'A6XX_RB_MRT_PITCH__SHIFT',
'A6XX_RB_NC_MODE_CNTL_AMSBC',
'A6XX_RB_NC_MODE_CNTL_LOWER_BIT__MASK',
'A6XX_RB_NC_MODE_CNTL_LOWER_BIT__SHIFT',
'A6XX_RB_NC_MODE_CNTL_MIN_ACCESS_LENGTH',
'A6XX_RB_NC_MODE_CNTL_MODE',
'A6XX_RB_NC_MODE_CNTL_RGB565_PREDICATOR',
'A6XX_RB_NC_MODE_CNTL_UNK12__MASK',
'A6XX_RB_NC_MODE_CNTL_UNK12__SHIFT',
'A6XX_RB_NC_MODE_CNTL_UPPER_BIT__MASK',
'A6XX_RB_NC_MODE_CNTL_UPPER_BIT__SHIFT',
'A6XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK',
'A6XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT',
'A6XX_RB_RAS_MSAA_CNTL_UNK2', 'A6XX_RB_RAS_MSAA_CNTL_UNK3',
'A6XX_RB_RENDER_CNTL_BINNING',
'A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE__MASK',
'A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE__SHIFT',
'A6XX_RB_RENDER_CNTL_CONSERVATIVERASEN',
'A6XX_RB_RENDER_CNTL_EARLYVIZOUTEN',
'A6XX_RB_RENDER_CNTL_FLAG_DEPTH',
'A6XX_RB_RENDER_CNTL_FLAG_MRTS__MASK',
'A6XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT',
'A6XX_RB_RENDER_CNTL_INNERCONSERVATIVERASEN',
'A6XX_RB_RENDER_CNTL_RASTER_DIRECTION__MASK',
'A6XX_RB_RENDER_CNTL_RASTER_DIRECTION__SHIFT',
'A6XX_RB_RENDER_CNTL_RASTER_MODE__MASK',
'A6XX_RB_RENDER_CNTL_RASTER_MODE__SHIFT',
'A6XX_RB_RENDER_CNTL_UNK8__MASK',
'A6XX_RB_RENDER_CNTL_UNK8__SHIFT',
'A6XX_RB_RENDER_COMPONENTS_RT0__MASK',
'A6XX_RB_RENDER_COMPONENTS_RT0__SHIFT',
'A6XX_RB_RENDER_COMPONENTS_RT1__MASK',
'A6XX_RB_RENDER_COMPONENTS_RT1__SHIFT',
'A6XX_RB_RENDER_COMPONENTS_RT2__MASK',
'A6XX_RB_RENDER_COMPONENTS_RT2__SHIFT',
'A6XX_RB_RENDER_COMPONENTS_RT3__MASK',
'A6XX_RB_RENDER_COMPONENTS_RT3__SHIFT',
'A6XX_RB_RENDER_COMPONENTS_RT4__MASK',
'A6XX_RB_RENDER_COMPONENTS_RT4__SHIFT',
'A6XX_RB_RENDER_COMPONENTS_RT5__MASK',
'A6XX_RB_RENDER_COMPONENTS_RT5__SHIFT',
'A6XX_RB_RENDER_COMPONENTS_RT6__MASK',
'A6XX_RB_RENDER_COMPONENTS_RT6__SHIFT',
'A6XX_RB_RENDER_COMPONENTS_RT7__MASK',
'A6XX_RB_RENDER_COMPONENTS_RT7__SHIFT',
'A6XX_RB_RENDER_CONTROL0_COORD_MASK__MASK',
'A6XX_RB_RENDER_CONTROL0_COORD_MASK__SHIFT',
'A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_CENTROID',
'A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_PIXEL',
'A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_SAMPLE',
'A6XX_RB_RENDER_CONTROL0_IJ_PERSP_CENTROID',
'A6XX_RB_RENDER_CONTROL0_IJ_PERSP_PIXEL',
'A6XX_RB_RENDER_CONTROL0_IJ_PERSP_SAMPLE',
'A6XX_RB_RENDER_CONTROL0_UNK10',
'A6XX_RB_RENDER_CONTROL1_CENTERRHW',
'A6XX_RB_RENDER_CONTROL1_FACENESS',
'A6XX_RB_RENDER_CONTROL1_FOVEATION',
'A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE__MASK',
'A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE__SHIFT',
'A6XX_RB_RENDER_CONTROL1_LINELENGTHEN',
'A6XX_RB_RENDER_CONTROL1_POSTDEPTHCOVERAGE',
'A6XX_RB_RENDER_CONTROL1_SAMPLEID',
'A6XX_RB_RENDER_CONTROL1_SAMPLEMASK',
'A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE',
'A6XX_RB_SAMPLE_CONFIG_LOCATION_ENABLE',
'A6XX_RB_SAMPLE_CONFIG_UNK0', 'A6XX_RB_SAMPLE_COUNT_CONTROL_COPY',
'A6XX_RB_SAMPLE_COUNT_CONTROL_DISABLE',
'A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK',
'A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT',
'A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK',
'A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT',
'A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK',
'A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT',
'A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK',
'A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT',
'A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK',
'A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT',
'A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK',
'A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT',
'A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK',
'A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT',
'A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK',
'A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT',
'A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK',
'A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT',
'A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK',
'A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT',
'A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK',
'A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT',
'A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK',
'A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT',
'A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK',
'A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT',
'A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK',
'A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT',
'A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK',
'A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT',
'A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK',
'A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT',
'A6XX_RB_SRGB_CNTL_SRGB_MRT0', 'A6XX_RB_SRGB_CNTL_SRGB_MRT1',
'A6XX_RB_SRGB_CNTL_SRGB_MRT2', 'A6XX_RB_SRGB_CNTL_SRGB_MRT3',
'A6XX_RB_SRGB_CNTL_SRGB_MRT4', 'A6XX_RB_SRGB_CNTL_SRGB_MRT5',
'A6XX_RB_SRGB_CNTL_SRGB_MRT6', 'A6XX_RB_SRGB_CNTL_SRGB_MRT7',
'A6XX_RB_STENCILMASK_BFMASK__MASK',
'A6XX_RB_STENCILMASK_BFMASK__SHIFT',
'A6XX_RB_STENCILMASK_MASK__MASK',
'A6XX_RB_STENCILMASK_MASK__SHIFT',
'A6XX_RB_STENCILREF_BFREF__MASK',
'A6XX_RB_STENCILREF_BFREF__SHIFT', 'A6XX_RB_STENCILREF_REF__MASK',
'A6XX_RB_STENCILREF_REF__SHIFT',
'A6XX_RB_STENCILWRMASK_BFWRMASK__MASK',
'A6XX_RB_STENCILWRMASK_BFWRMASK__SHIFT',
'A6XX_RB_STENCILWRMASK_WRMASK__MASK',
'A6XX_RB_STENCILWRMASK_WRMASK__SHIFT',
'A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK',
'A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT',
'A6XX_RB_STENCIL_BUFFER_PITCH__MASK',
'A6XX_RB_STENCIL_BUFFER_PITCH__SHIFT',
'A6XX_RB_STENCIL_CONTROL_FAIL_BF__MASK',
'A6XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT',
'A6XX_RB_STENCIL_CONTROL_FAIL__MASK',
'A6XX_RB_STENCIL_CONTROL_FAIL__SHIFT',
'A6XX_RB_STENCIL_CONTROL_FUNC_BF__MASK',
'A6XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT',
'A6XX_RB_STENCIL_CONTROL_FUNC__MASK',
'A6XX_RB_STENCIL_CONTROL_FUNC__SHIFT',
'A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE',
'A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF',
'A6XX_RB_STENCIL_CONTROL_STENCIL_READ',
'A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK',
'A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT',
'A6XX_RB_STENCIL_CONTROL_ZFAIL__MASK',
'A6XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT',
'A6XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK',
'A6XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT',
'A6XX_RB_STENCIL_CONTROL_ZPASS__MASK',
'A6XX_RB_STENCIL_CONTROL_ZPASS__SHIFT',
'A6XX_RB_STENCIL_INFO_SEPARATE_STENCIL',
'A6XX_RB_STENCIL_INFO_UNK1', 'A6XX_RB_UNKNOWN_88D0_UNK0__MASK',
'A6XX_RB_UNKNOWN_88D0_UNK0__SHIFT',
'A6XX_RB_UNKNOWN_88D0_UNK16__MASK',
'A6XX_RB_UNKNOWN_88D0_UNK16__SHIFT',
'A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK',
'A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT',
'A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__MASK',
'A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__SHIFT',
'A6XX_RB_WINDOW_OFFSET2_X__MASK',
'A6XX_RB_WINDOW_OFFSET2_X__SHIFT',
'A6XX_RB_WINDOW_OFFSET2_Y__MASK',
'A6XX_RB_WINDOW_OFFSET2_Y__SHIFT',
'A6XX_RB_WINDOW_OFFSET_X__MASK', 'A6XX_RB_WINDOW_OFFSET_X__SHIFT',
'A6XX_RB_WINDOW_OFFSET_Y__MASK', 'A6XX_RB_WINDOW_OFFSET_Y__SHIFT',
'A6XX_RB_Z_BOUNDS_MAX__MASK', 'A6XX_RB_Z_BOUNDS_MAX__SHIFT',
'A6XX_RB_Z_BOUNDS_MIN__MASK', 'A6XX_RB_Z_BOUNDS_MIN__SHIFT',
'A6XX_RB_Z_CLAMP_MAX__MASK', 'A6XX_RB_Z_CLAMP_MAX__SHIFT',
'A6XX_RB_Z_CLAMP_MIN__MASK', 'A6XX_RB_Z_CLAMP_MIN__SHIFT',
'A6XX_REDUCTION_MODE_AVERAGE', 'A6XX_REDUCTION_MODE_MAX',
'A6XX_REDUCTION_MODE_MIN',
'A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__MASK',
'A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__SHIFT',
'A6XX_SP_2D_DST_FORMAT_MASK__MASK',
'A6XX_SP_2D_DST_FORMAT_MASK__SHIFT', 'A6XX_SP_2D_DST_FORMAT_NORM',
'A6XX_SP_2D_DST_FORMAT_SINT', 'A6XX_SP_2D_DST_FORMAT_SRGB',
'A6XX_SP_2D_DST_FORMAT_UINT',
'A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK',
'A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT',
'A6XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK',
'A6XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT',
'A6XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE',
'A6XX_SP_BLEND_CNTL_DUAL_COLOR_IN_ENABLE',
'A6XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK',
'A6XX_SP_BLEND_CNTL_ENABLE_BLEND__SHIFT',
'A6XX_SP_BLEND_CNTL_UNK8', 'A6XX_SP_CB_BINDLESS_DATA',
'A6XX_SP_CB_BINDLESS_TAG', 'A6XX_SP_CB_LEGACY_DATA',
'A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK',
'A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT',
'A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK',
'A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT',
'A6XX_SP_CS_CNTL_0_LOCALIDREGID__MASK',
'A6XX_SP_CS_CNTL_0_LOCALIDREGID__SHIFT',
'A6XX_SP_CS_CNTL_0_WGIDCONSTID__MASK',
'A6XX_SP_CS_CNTL_0_WGIDCONSTID__SHIFT',
'A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID__MASK',
'A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID__SHIFT',
'A6XX_SP_CS_CNTL_0_WGSIZECONSTID__MASK',
'A6XX_SP_CS_CNTL_0_WGSIZECONSTID__SHIFT',
'A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__MASK',
'A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT',
'A6XX_SP_CS_CNTL_1_SINGLE_SP_CORE',
'A6XX_SP_CS_CNTL_1_THREADSIZE_SCALAR',
'A6XX_SP_CS_CNTL_1_THREADSIZE__MASK',
'A6XX_SP_CS_CNTL_1_THREADSIZE__SHIFT',
'A6XX_SP_CS_CONFIG_BINDLESS_IBO',
'A6XX_SP_CS_CONFIG_BINDLESS_SAMP',
'A6XX_SP_CS_CONFIG_BINDLESS_TEX',
'A6XX_SP_CS_CONFIG_BINDLESS_UBO', 'A6XX_SP_CS_CONFIG_ENABLED',
'A6XX_SP_CS_CONFIG_NIBO__MASK', 'A6XX_SP_CS_CONFIG_NIBO__SHIFT',
'A6XX_SP_CS_CONFIG_NSAMP__MASK', 'A6XX_SP_CS_CONFIG_NSAMP__SHIFT',
'A6XX_SP_CS_CONFIG_NTEX__MASK', 'A6XX_SP_CS_CONFIG_NTEX__SHIFT',
'A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK',
'A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT',
'A6XX_SP_CS_CTRL_REG0_EARLYPREAMBLE',
'A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK',
'A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT',
'A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK',
'A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT',
'A6XX_SP_CS_CTRL_REG0_MERGEDREGS',
'A6XX_SP_CS_CTRL_REG0_THREADMODE__MASK',
'A6XX_SP_CS_CTRL_REG0_THREADMODE__SHIFT',
'A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK',
'A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT',
'A6XX_SP_CS_CTRL_REG0_UNK13', 'A6XX_SP_CS_CTRL_REG0_UNK21',
'A6XX_SP_CS_CTRL_REG0_UNK22',
'A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK',
'A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT',
'A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK',
'A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT',
'A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK',
'A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT',
'A6XX_SP_CS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT',
'A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK',
'A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT',
'A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__MASK',
'A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__SHIFT',
'A6XX_SP_CS_UNKNOWN_A9B1_UNK5', 'A6XX_SP_CS_UNKNOWN_A9B1_UNK6',
'A6XX_SP_DS_CONFIG_BINDLESS_IBO',
'A6XX_SP_DS_CONFIG_BINDLESS_SAMP',
'A6XX_SP_DS_CONFIG_BINDLESS_TEX',
'A6XX_SP_DS_CONFIG_BINDLESS_UBO', 'A6XX_SP_DS_CONFIG_ENABLED',
'A6XX_SP_DS_CONFIG_NIBO__MASK', 'A6XX_SP_DS_CONFIG_NIBO__SHIFT',
'A6XX_SP_DS_CONFIG_NSAMP__MASK', 'A6XX_SP_DS_CONFIG_NSAMP__SHIFT',
'A6XX_SP_DS_CONFIG_NTEX__MASK', 'A6XX_SP_DS_CONFIG_NTEX__SHIFT',
'A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK',
'A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT',
'A6XX_SP_DS_CTRL_REG0_EARLYPREAMBLE',
'A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK',
'A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT',
'A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK',
'A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT',
'A6XX_SP_DS_CTRL_REG0_THREADMODE__MASK',
'A6XX_SP_DS_CTRL_REG0_THREADMODE__SHIFT',
'A6XX_SP_DS_CTRL_REG0_UNK13',
'A6XX_SP_DS_OUT_REG_A_COMPMASK__MASK',
'A6XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT',
'A6XX_SP_DS_OUT_REG_A_REGID__MASK',
'A6XX_SP_DS_OUT_REG_A_REGID__SHIFT',
'A6XX_SP_DS_OUT_REG_B_COMPMASK__MASK',
'A6XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT',
'A6XX_SP_DS_OUT_REG_B_REGID__MASK',
'A6XX_SP_DS_OUT_REG_B_REGID__SHIFT',
'A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__MASK',
'A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT',
'A6XX_SP_DS_PRIMITIVE_CNTL_OUT__MASK',
'A6XX_SP_DS_PRIMITIVE_CNTL_OUT__SHIFT',
'A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK',
'A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT',
'A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK',
'A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT',
'A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK',
'A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT',
'A6XX_SP_DS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT',
'A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK',
'A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT',
'A6XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK',
'A6XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT',
'A6XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK',
'A6XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT',
'A6XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK',
'A6XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT',
'A6XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK',
'A6XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT',
'A6XX_SP_FLOAT_CNTL_F16_NO_INF',
'A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__MASK',
'A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__SHIFT',
'A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__MASK',
'A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__SHIFT',
'A6XX_SP_FS_CONFIG_BINDLESS_IBO',
'A6XX_SP_FS_CONFIG_BINDLESS_SAMP',
'A6XX_SP_FS_CONFIG_BINDLESS_TEX',
'A6XX_SP_FS_CONFIG_BINDLESS_UBO', 'A6XX_SP_FS_CONFIG_ENABLED',
'A6XX_SP_FS_CONFIG_NIBO__MASK', 'A6XX_SP_FS_CONFIG_NIBO__SHIFT',
'A6XX_SP_FS_CONFIG_NSAMP__MASK', 'A6XX_SP_FS_CONFIG_NSAMP__SHIFT',
'A6XX_SP_FS_CONFIG_NTEX__MASK', 'A6XX_SP_FS_CONFIG_NTEX__SHIFT',
'A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK',
'A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT',
'A6XX_SP_FS_CTRL_REG0_EARLYPREAMBLE',
'A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK',
'A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT',
'A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK',
'A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT',
'A6XX_SP_FS_CTRL_REG0_LODPIXMASK',
'A6XX_SP_FS_CTRL_REG0_MERGEDREGS',
'A6XX_SP_FS_CTRL_REG0_PIXLODENABLE',
'A6XX_SP_FS_CTRL_REG0_THREADMODE__MASK',
'A6XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT',
'A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK',
'A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT',
'A6XX_SP_FS_CTRL_REG0_UNK13', 'A6XX_SP_FS_CTRL_REG0_UNK21',
'A6XX_SP_FS_CTRL_REG0_UNK24', 'A6XX_SP_FS_CTRL_REG0_UNK25',
'A6XX_SP_FS_CTRL_REG0_UNK27', 'A6XX_SP_FS_CTRL_REG0_VARYING',
'A6XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK',
'A6XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT',
'A6XX_SP_FS_MRT_REG_COLOR_SINT', 'A6XX_SP_FS_MRT_REG_COLOR_UINT',
'A6XX_SP_FS_MRT_REG_UNK10',
'A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__MASK',
'A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__SHIFT',
'A6XX_SP_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE',
'A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__MASK',
'A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__SHIFT',
'A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__MASK',
'A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__SHIFT',
'A6XX_SP_FS_OUTPUT_CNTL1_MRT__MASK',
'A6XX_SP_FS_OUTPUT_CNTL1_MRT__SHIFT',
'A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION',
'A6XX_SP_FS_OUTPUT_REG_REGID__MASK',
'A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT',
'A6XX_SP_FS_PREFETCH_CMD_BINDLESS',
'A6XX_SP_FS_PREFETCH_CMD_CMD__MASK',
'A6XX_SP_FS_PREFETCH_CMD_CMD__SHIFT',
'A6XX_SP_FS_PREFETCH_CMD_DST__MASK',
'A6XX_SP_FS_PREFETCH_CMD_DST__SHIFT',
'A6XX_SP_FS_PREFETCH_CMD_HALF',
'A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__MASK',
'A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__SHIFT',
'A6XX_SP_FS_PREFETCH_CMD_SRC__MASK',
'A6XX_SP_FS_PREFETCH_CMD_SRC__SHIFT',
'A6XX_SP_FS_PREFETCH_CMD_TEX_ID__MASK',
'A6XX_SP_FS_PREFETCH_CMD_TEX_ID__SHIFT',
'A6XX_SP_FS_PREFETCH_CMD_UNK27',
'A6XX_SP_FS_PREFETCH_CMD_WRMASK__MASK',
'A6XX_SP_FS_PREFETCH_CMD_WRMASK__SHIFT',
'A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID4COORD__MASK',
'A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID4COORD__SHIFT',
'A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID__MASK',
'A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID__SHIFT',
'A6XX_SP_FS_PREFETCH_CNTL_COUNT__MASK',
'A6XX_SP_FS_PREFETCH_CNTL_COUNT__SHIFT',
'A6XX_SP_FS_PREFETCH_CNTL_ENDOFQUAD',
'A6XX_SP_FS_PREFETCH_CNTL_IJ_WRITE_DISABLE',
'A6XX_SP_FS_PREFETCH_CNTL_WRITE_COLOR_TO_OUTPUT',
'A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK',
'A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT',
'A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK',
'A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT',
'A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK',
'A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT',
'A6XX_SP_FS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT',
'A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK',
'A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT',
'A6XX_SP_FS_RENDER_COMPONENTS_RT0__MASK',
'A6XX_SP_FS_RENDER_COMPONENTS_RT0__SHIFT',
'A6XX_SP_FS_RENDER_COMPONENTS_RT1__MASK',
'A6XX_SP_FS_RENDER_COMPONENTS_RT1__SHIFT',
'A6XX_SP_FS_RENDER_COMPONENTS_RT2__MASK',
'A6XX_SP_FS_RENDER_COMPONENTS_RT2__SHIFT',
'A6XX_SP_FS_RENDER_COMPONENTS_RT3__MASK',
'A6XX_SP_FS_RENDER_COMPONENTS_RT3__SHIFT',
'A6XX_SP_FS_RENDER_COMPONENTS_RT4__MASK',
'A6XX_SP_FS_RENDER_COMPONENTS_RT4__SHIFT',
'A6XX_SP_FS_RENDER_COMPONENTS_RT5__MASK',
'A6XX_SP_FS_RENDER_COMPONENTS_RT5__SHIFT',
'A6XX_SP_FS_RENDER_COMPONENTS_RT6__MASK',
'A6XX_SP_FS_RENDER_COMPONENTS_RT6__SHIFT',
'A6XX_SP_FS_RENDER_COMPONENTS_RT7__MASK',
'A6XX_SP_FS_RENDER_COMPONENTS_RT7__SHIFT',
'A6XX_SP_GS_CONFIG_BINDLESS_IBO',
'A6XX_SP_GS_CONFIG_BINDLESS_SAMP',
'A6XX_SP_GS_CONFIG_BINDLESS_TEX',
'A6XX_SP_GS_CONFIG_BINDLESS_UBO', 'A6XX_SP_GS_CONFIG_ENABLED',
'A6XX_SP_GS_CONFIG_NIBO__MASK', 'A6XX_SP_GS_CONFIG_NIBO__SHIFT',
'A6XX_SP_GS_CONFIG_NSAMP__MASK', 'A6XX_SP_GS_CONFIG_NSAMP__SHIFT',
'A6XX_SP_GS_CONFIG_NTEX__MASK', 'A6XX_SP_GS_CONFIG_NTEX__SHIFT',
'A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK',
'A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT',
'A6XX_SP_GS_CTRL_REG0_EARLYPREAMBLE',
'A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK',
'A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT',
'A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK',
'A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT',
'A6XX_SP_GS_CTRL_REG0_THREADMODE__MASK',
'A6XX_SP_GS_CTRL_REG0_THREADMODE__SHIFT',
'A6XX_SP_GS_CTRL_REG0_UNK13',
'A6XX_SP_GS_OUT_REG_A_COMPMASK__MASK',
'A6XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT',
'A6XX_SP_GS_OUT_REG_A_REGID__MASK',
'A6XX_SP_GS_OUT_REG_A_REGID__SHIFT',
'A6XX_SP_GS_OUT_REG_B_COMPMASK__MASK',
'A6XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT',
'A6XX_SP_GS_OUT_REG_B_REGID__MASK',
'A6XX_SP_GS_OUT_REG_B_REGID__SHIFT',
'A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__MASK',
'A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT',
'A6XX_SP_GS_PRIMITIVE_CNTL_OUT__MASK',
'A6XX_SP_GS_PRIMITIVE_CNTL_OUT__SHIFT',
'A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK',
'A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT',
'A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK',
'A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT',
'A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK',
'A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT',
'A6XX_SP_GS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT',
'A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK',
'A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT',
'A6XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK',
'A6XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT',
'A6XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK',
'A6XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT',
'A6XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK',
'A6XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT',
'A6XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK',
'A6XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT',
'A6XX_SP_HS_CONFIG_BINDLESS_IBO',
'A6XX_SP_HS_CONFIG_BINDLESS_SAMP',
'A6XX_SP_HS_CONFIG_BINDLESS_TEX',
'A6XX_SP_HS_CONFIG_BINDLESS_UBO', 'A6XX_SP_HS_CONFIG_ENABLED',
'A6XX_SP_HS_CONFIG_NIBO__MASK', 'A6XX_SP_HS_CONFIG_NIBO__SHIFT',
'A6XX_SP_HS_CONFIG_NSAMP__MASK', 'A6XX_SP_HS_CONFIG_NSAMP__SHIFT',
'A6XX_SP_HS_CONFIG_NTEX__MASK', 'A6XX_SP_HS_CONFIG_NTEX__SHIFT',
'A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK',
'A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT',
'A6XX_SP_HS_CTRL_REG0_EARLYPREAMBLE',
'A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK',
'A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT',
'A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK',
'A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT',
'A6XX_SP_HS_CTRL_REG0_THREADMODE__MASK',
'A6XX_SP_HS_CTRL_REG0_THREADMODE__SHIFT',
'A6XX_SP_HS_CTRL_REG0_UNK13',
'A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK',
'A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT',
'A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK',
'A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT',
'A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK',
'A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT',
'A6XX_SP_HS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT',
'A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK',
'A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT',
'A6XX_SP_INST_DATA', 'A6XX_SP_INST_TAG', 'A6XX_SP_LB_0_DATA',
'A6XX_SP_LB_1_DATA', 'A6XX_SP_LB_2_DATA', 'A6XX_SP_LB_3_DATA',
'A6XX_SP_LB_4_DATA', 'A6XX_SP_LB_5_DATA', 'A6XX_SP_LB_6_DATA',
'A6XX_SP_LB_7_DATA',
'A6XX_SP_MODE_CONTROL_CONSTANT_DEMOTION_ENABLE',
'A6XX_SP_MODE_CONTROL_ISAMMODE__MASK',
'A6XX_SP_MODE_CONTROL_ISAMMODE__SHIFT',
'A6XX_SP_MODE_CONTROL_SHARED_CONSTS_ENABLE',
'A6XX_SP_PERFCTR_ENABLE_CS', 'A6XX_SP_PERFCTR_ENABLE_DS',
'A6XX_SP_PERFCTR_ENABLE_FS', 'A6XX_SP_PERFCTR_ENABLE_GS',
'A6XX_SP_PERFCTR_ENABLE_HS', 'A6XX_SP_PERFCTR_ENABLE_VS',
'A6XX_SP_PS_2D_SRC_FLAGS_PITCH__MASK',
'A6XX_SP_PS_2D_SRC_FLAGS_PITCH__SHIFT',
'A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK',
'A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT',
'A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK',
'A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT',
'A6XX_SP_PS_2D_SRC_INFO_FILTER', 'A6XX_SP_PS_2D_SRC_INFO_FLAGS',
'A6XX_SP_PS_2D_SRC_INFO_SAMPLES_AVERAGE',
'A6XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK',
'A6XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT',
'A6XX_SP_PS_2D_SRC_INFO_SRGB',
'A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK',
'A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT',
'A6XX_SP_PS_2D_SRC_INFO_UNK17', 'A6XX_SP_PS_2D_SRC_INFO_UNK19',
'A6XX_SP_PS_2D_SRC_INFO_UNK20', 'A6XX_SP_PS_2D_SRC_INFO_UNK21',
'A6XX_SP_PS_2D_SRC_INFO_UNK22',
'A6XX_SP_PS_2D_SRC_INFO_UNK23__MASK',
'A6XX_SP_PS_2D_SRC_INFO_UNK23__SHIFT',
'A6XX_SP_PS_2D_SRC_INFO_UNK28',
'A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK',
'A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT',
'A6XX_SP_PS_2D_SRC_PITCH_UNK0__MASK',
'A6XX_SP_PS_2D_SRC_PITCH_UNK0__SHIFT',
'A6XX_SP_PS_2D_SRC_PLANE_PITCH__MASK',
'A6XX_SP_PS_2D_SRC_PLANE_PITCH__SHIFT',
'A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK',
'A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT',
'A6XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK',
'A6XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT', 'A6XX_SP_SMO_TAG',
'A6XX_SP_SRGB_CNTL_SRGB_MRT0', 'A6XX_SP_SRGB_CNTL_SRGB_MRT1',
'A6XX_SP_SRGB_CNTL_SRGB_MRT2', 'A6XX_SP_SRGB_CNTL_SRGB_MRT3',
'A6XX_SP_SRGB_CNTL_SRGB_MRT4', 'A6XX_SP_SRGB_CNTL_SRGB_MRT5',
'A6XX_SP_SRGB_CNTL_SRGB_MRT6', 'A6XX_SP_SRGB_CNTL_SRGB_MRT7',
'A6XX_SP_STATE_DATA', 'A6XX_SP_TMO_UMO_TAG',
'A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE',
'A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__MASK',
'A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT',
'A6XX_SP_TP_MODE_CNTL_ISAMMODE__MASK',
'A6XX_SP_TP_MODE_CNTL_ISAMMODE__SHIFT',
'A6XX_SP_TP_MODE_CNTL_UNK3__MASK',
'A6XX_SP_TP_MODE_CNTL_UNK3__SHIFT',
'A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK',
'A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT',
'A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__MASK',
'A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__SHIFT',
'A6XX_SP_TP_SAMPLE_CONFIG_LOCATION_ENABLE',
'A6XX_SP_TP_SAMPLE_CONFIG_UNK0',
'A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK',
'A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT',
'A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK',
'A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT',
'A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK',
'A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT',
'A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK',
'A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT',
'A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK',
'A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT',
'A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK',
'A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT',
'A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK',
'A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT',
'A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK',
'A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT',
'A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK',
'A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT',
'A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK',
'A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT',
'A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK',
'A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT',
'A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK',
'A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT',
'A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK',
'A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT',
'A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK',
'A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT',
'A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK',
'A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT',
'A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK',
'A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT',
'A6XX_SP_TP_WINDOW_OFFSET_X__MASK',
'A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT',
'A6XX_SP_TP_WINDOW_OFFSET_Y__MASK',
'A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT', 'A6XX_SP_UAV_DATA',
'A6XX_SP_VS_CONFIG_BINDLESS_IBO',
'A6XX_SP_VS_CONFIG_BINDLESS_SAMP',
'A6XX_SP_VS_CONFIG_BINDLESS_TEX',
'A6XX_SP_VS_CONFIG_BINDLESS_UBO', 'A6XX_SP_VS_CONFIG_ENABLED',
'A6XX_SP_VS_CONFIG_NIBO__MASK', 'A6XX_SP_VS_CONFIG_NIBO__SHIFT',
'A6XX_SP_VS_CONFIG_NSAMP__MASK', 'A6XX_SP_VS_CONFIG_NSAMP__SHIFT',
'A6XX_SP_VS_CONFIG_NTEX__MASK', 'A6XX_SP_VS_CONFIG_NTEX__SHIFT',
'A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK',
'A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT',
'A6XX_SP_VS_CTRL_REG0_EARLYPREAMBLE',
'A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK',
'A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT',
'A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK',
'A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT',
'A6XX_SP_VS_CTRL_REG0_MERGEDREGS',
'A6XX_SP_VS_CTRL_REG0_THREADMODE__MASK',
'A6XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT',
'A6XX_SP_VS_CTRL_REG0_UNK13',
'A6XX_SP_VS_OUT_REG_A_COMPMASK__MASK',
'A6XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT',
'A6XX_SP_VS_OUT_REG_A_REGID__MASK',
'A6XX_SP_VS_OUT_REG_A_REGID__SHIFT',
'A6XX_SP_VS_OUT_REG_B_COMPMASK__MASK',
'A6XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT',
'A6XX_SP_VS_OUT_REG_B_REGID__MASK',
'A6XX_SP_VS_OUT_REG_B_REGID__SHIFT',
'A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__MASK',
'A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT',
'A6XX_SP_VS_PRIMITIVE_CNTL_OUT__MASK',
'A6XX_SP_VS_PRIMITIVE_CNTL_OUT__SHIFT',
'A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK',
'A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT',
'A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK',
'A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT',
'A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK',
'A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT',
'A6XX_SP_VS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT',
'A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK',
'A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT',
'A6XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK',
'A6XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT',
'A6XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK',
'A6XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT',
'A6XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK',
'A6XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT',
'A6XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK',
'A6XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT',
'A6XX_SP_WINDOW_OFFSET_X__MASK', 'A6XX_SP_WINDOW_OFFSET_X__SHIFT',
'A6XX_SP_WINDOW_OFFSET_Y__MASK', 'A6XX_SP_WINDOW_OFFSET_Y__SHIFT',
'A6XX_TEX_1D', 'A6XX_TEX_2D', 'A6XX_TEX_3D', 'A6XX_TEX_ANISO',
'A6XX_TEX_ANISO_1', 'A6XX_TEX_ANISO_16', 'A6XX_TEX_ANISO_2',
'A6XX_TEX_ANISO_4', 'A6XX_TEX_ANISO_8', 'A6XX_TEX_BUFFER',
'A6XX_TEX_CLAMP_TO_BORDER', 'A6XX_TEX_CLAMP_TO_EDGE',
'A6XX_TEX_CONST_0_CHROMA_MIDPOINT_X',
'A6XX_TEX_CONST_0_CHROMA_MIDPOINT_Y',
'A6XX_TEX_CONST_0_FMT__MASK', 'A6XX_TEX_CONST_0_FMT__SHIFT',
'A6XX_TEX_CONST_0_MIPLVLS__MASK',
'A6XX_TEX_CONST_0_MIPLVLS__SHIFT',
'A6XX_TEX_CONST_0_SAMPLES__MASK',
'A6XX_TEX_CONST_0_SAMPLES__SHIFT', 'A6XX_TEX_CONST_0_SRGB',
'A6XX_TEX_CONST_0_SWAP__MASK', 'A6XX_TEX_CONST_0_SWAP__SHIFT',
'A6XX_TEX_CONST_0_SWIZ_W__MASK', 'A6XX_TEX_CONST_0_SWIZ_W__SHIFT',
'A6XX_TEX_CONST_0_SWIZ_X__MASK', 'A6XX_TEX_CONST_0_SWIZ_X__SHIFT',
'A6XX_TEX_CONST_0_SWIZ_Y__MASK', 'A6XX_TEX_CONST_0_SWIZ_Y__SHIFT',
'A6XX_TEX_CONST_0_SWIZ_Z__MASK', 'A6XX_TEX_CONST_0_SWIZ_Z__SHIFT',
'A6XX_TEX_CONST_0_TILE_MODE__MASK',
'A6XX_TEX_CONST_0_TILE_MODE__SHIFT',
'A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__MASK',
'A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__SHIFT',
'A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__MASK',
'A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__SHIFT',
'A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__MASK',
'A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__SHIFT',
'A6XX_TEX_CONST_1_HEIGHT__MASK', 'A6XX_TEX_CONST_1_HEIGHT__SHIFT',
'A6XX_TEX_CONST_1_WIDTH__MASK', 'A6XX_TEX_CONST_1_WIDTH__SHIFT',
'A6XX_TEX_CONST_2_PITCHALIGN__MASK',
'A6XX_TEX_CONST_2_PITCHALIGN__SHIFT',
'A6XX_TEX_CONST_2_PITCH__MASK', 'A6XX_TEX_CONST_2_PITCH__SHIFT',
'A6XX_TEX_CONST_2_STARTOFFSETTEXELS__MASK',
'A6XX_TEX_CONST_2_STARTOFFSETTEXELS__SHIFT',
'A6XX_TEX_CONST_2_STRUCTSIZETEXELS__MASK',
'A6XX_TEX_CONST_2_STRUCTSIZETEXELS__SHIFT',
'A6XX_TEX_CONST_2_TYPE__MASK', 'A6XX_TEX_CONST_2_TYPE__SHIFT',
'A6XX_TEX_CONST_3_ARRAY_PITCH__MASK',
'A6XX_TEX_CONST_3_ARRAY_PITCH__SHIFT', 'A6XX_TEX_CONST_3_FLAG',
'A6XX_TEX_CONST_3_MIN_LAYERSZ__MASK',
'A6XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT',
'A6XX_TEX_CONST_3_TILE_ALL', 'A6XX_TEX_CONST_4_BASE_LO__MASK',
'A6XX_TEX_CONST_4_BASE_LO__SHIFT',
'A6XX_TEX_CONST_5_BASE_HI__MASK',
'A6XX_TEX_CONST_5_BASE_HI__SHIFT', 'A6XX_TEX_CONST_5_DEPTH__MASK',
'A6XX_TEX_CONST_5_DEPTH__SHIFT',
'A6XX_TEX_CONST_6_MIN_LOD_CLAMP__MASK',
'A6XX_TEX_CONST_6_MIN_LOD_CLAMP__SHIFT',
'A6XX_TEX_CONST_6_PLANE_PITCH__MASK',
'A6XX_TEX_CONST_6_PLANE_PITCH__SHIFT',
'A6XX_TEX_CONST_7_FLAG_LO__MASK',
'A6XX_TEX_CONST_7_FLAG_LO__SHIFT',
'A6XX_TEX_CONST_8_FLAG_HI__MASK',
'A6XX_TEX_CONST_8_FLAG_HI__SHIFT',
'A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__MASK',
'A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT',
'A6XX_TEX_CUBE', 'A6XX_TEX_CUBIC', 'A6XX_TEX_LINEAR',
'A6XX_TEX_MIRROR_CLAMP', 'A6XX_TEX_MIRROR_REPEAT',
'A6XX_TEX_NEAREST', 'A6XX_TEX_ONE', 'A6XX_TEX_REPEAT',
'A6XX_TEX_SAMP_0_ANISO__MASK', 'A6XX_TEX_SAMP_0_ANISO__SHIFT',
'A6XX_TEX_SAMP_0_LOD_BIAS__MASK',
'A6XX_TEX_SAMP_0_LOD_BIAS__SHIFT',
'A6XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR',
'A6XX_TEX_SAMP_0_WRAP_R__MASK', 'A6XX_TEX_SAMP_0_WRAP_R__SHIFT',
'A6XX_TEX_SAMP_0_WRAP_S__MASK', 'A6XX_TEX_SAMP_0_WRAP_S__SHIFT',
'A6XX_TEX_SAMP_0_WRAP_T__MASK', 'A6XX_TEX_SAMP_0_WRAP_T__SHIFT',
'A6XX_TEX_SAMP_0_XY_MAG__MASK', 'A6XX_TEX_SAMP_0_XY_MAG__SHIFT',
'A6XX_TEX_SAMP_0_XY_MIN__MASK', 'A6XX_TEX_SAMP_0_XY_MIN__SHIFT',
'A6XX_TEX_SAMP_1_CLAMPENABLE',
'A6XX_TEX_SAMP_1_COMPARE_FUNC__MASK',
'A6XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT',
'A6XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF',
'A6XX_TEX_SAMP_1_MAX_LOD__MASK', 'A6XX_TEX_SAMP_1_MAX_LOD__SHIFT',
'A6XX_TEX_SAMP_1_MIN_LOD__MASK', 'A6XX_TEX_SAMP_1_MIN_LOD__SHIFT',
'A6XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR',
'A6XX_TEX_SAMP_1_UNNORM_COORDS', 'A6XX_TEX_SAMP_2_BCOLOR__MASK',
'A6XX_TEX_SAMP_2_BCOLOR__SHIFT', 'A6XX_TEX_SAMP_2_CHROMA_LINEAR',
'A6XX_TEX_SAMP_2_REDUCTION_MODE__MASK',
'A6XX_TEX_SAMP_2_REDUCTION_MODE__SHIFT', 'A6XX_TEX_W',
'A6XX_TEX_X', 'A6XX_TEX_Y', 'A6XX_TEX_Z', 'A6XX_TEX_ZERO',
'A6XX_TP0_MIPMAP_BASE_DATA', 'A6XX_TP0_SMO_DATA',
'A6XX_TP0_TMO_DATA', 'A6XX_TP1_MIPMAP_BASE_DATA',
'A6XX_TP1_SMO_DATA', 'A6XX_TP1_TMO_DATA',
'A6XX_TPL1_DBG_ECO_CNTL1_UBWC_WORKAROUND',
'A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__MASK',
'A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__SHIFT',
'A6XX_TPL1_NC_MODE_CNTL_MIN_ACCESS_LENGTH',
'A6XX_TPL1_NC_MODE_CNTL_MODE',
'A6XX_TPL1_NC_MODE_CNTL_UNK6__MASK',
'A6XX_TPL1_NC_MODE_CNTL_UNK6__SHIFT',
'A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__MASK',
'A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__SHIFT',
'A6XX_UBO_0_BASE_LO__MASK', 'A6XX_UBO_0_BASE_LO__SHIFT',
'A6XX_UBO_1_BASE_HI__MASK', 'A6XX_UBO_1_BASE_HI__SHIFT',
'A6XX_UBO_1_SIZE__MASK', 'A6XX_UBO_1_SIZE__SHIFT',
'A6XX_UCHE_CLIENT_PF_PERFSEL__MASK',
'A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT',
'A6XX_VBIF_CLKON_FORCE_ON_TESTBUS',
'A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__MASK',
'A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__SHIFT',
'A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__MASK',
'A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__SHIFT',
'A6XX_VFD_ADD_OFFSET_INSTANCE', 'A6XX_VFD_ADD_OFFSET_VERTEX',
'A6XX_VFD_CONTROL_0_DECODE_CNT__MASK',
'A6XX_VFD_CONTROL_0_DECODE_CNT__SHIFT',
'A6XX_VFD_CONTROL_0_FETCH_CNT__MASK',
'A6XX_VFD_CONTROL_0_FETCH_CNT__SHIFT',
'A6XX_VFD_CONTROL_1_REGID4INST__MASK',
'A6XX_VFD_CONTROL_1_REGID4INST__SHIFT',
'A6XX_VFD_CONTROL_1_REGID4PRIMID__MASK',
'A6XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT',
'A6XX_VFD_CONTROL_1_REGID4VIEWID__MASK',
'A6XX_VFD_CONTROL_1_REGID4VIEWID__SHIFT',
'A6XX_VFD_CONTROL_1_REGID4VTX__MASK',
'A6XX_VFD_CONTROL_1_REGID4VTX__SHIFT',
'A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID__MASK',
'A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID__SHIFT',
'A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__MASK',
'A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__SHIFT',
'A6XX_VFD_CONTROL_3_REGID_DSPRIMID__MASK',
'A6XX_VFD_CONTROL_3_REGID_DSPRIMID__SHIFT',
'A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID__MASK',
'A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID__SHIFT',
'A6XX_VFD_CONTROL_3_REGID_TESSX__MASK',
'A6XX_VFD_CONTROL_3_REGID_TESSX__SHIFT',
'A6XX_VFD_CONTROL_3_REGID_TESSY__MASK',
'A6XX_VFD_CONTROL_3_REGID_TESSY__SHIFT',
'A6XX_VFD_CONTROL_4_UNK0__MASK', 'A6XX_VFD_CONTROL_4_UNK0__SHIFT',
'A6XX_VFD_CONTROL_5_REGID_GSHEADER__MASK',
'A6XX_VFD_CONTROL_5_REGID_GSHEADER__SHIFT',
'A6XX_VFD_CONTROL_5_UNK8__MASK', 'A6XX_VFD_CONTROL_5_UNK8__SHIFT',
'A6XX_VFD_CONTROL_6_PRIMID4PSEN', 'A6XX_VFD_DECODE_INSTR_FLOAT',
'A6XX_VFD_DECODE_INSTR_FORMAT__MASK',
'A6XX_VFD_DECODE_INSTR_FORMAT__SHIFT',
'A6XX_VFD_DECODE_INSTR_IDX__MASK',
'A6XX_VFD_DECODE_INSTR_IDX__SHIFT',
'A6XX_VFD_DECODE_INSTR_INSTANCED',
'A6XX_VFD_DECODE_INSTR_OFFSET__MASK',
'A6XX_VFD_DECODE_INSTR_OFFSET__SHIFT',
'A6XX_VFD_DECODE_INSTR_SWAP__MASK',
'A6XX_VFD_DECODE_INSTR_SWAP__SHIFT',
'A6XX_VFD_DECODE_INSTR_UNK30',
'A6XX_VFD_DEST_CNTL_INSTR_REGID__MASK',
'A6XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT',
'A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK',
'A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT',
'A6XX_VFD_MODE_CNTL_RENDER_MODE__MASK',
'A6XX_VFD_MODE_CNTL_RENDER_MODE__SHIFT',
'A6XX_VFD_MULTIVIEW_CNTL_DISABLEMULTIPOS',
'A6XX_VFD_MULTIVIEW_CNTL_ENABLE',
'A6XX_VFD_MULTIVIEW_CNTL_VIEWS__MASK',
'A6XX_VFD_MULTIVIEW_CNTL_VIEWS__SHIFT',
'A6XX_VPC_CNTL_0_NUMNONPOSVAR__MASK',
'A6XX_VPC_CNTL_0_NUMNONPOSVAR__SHIFT',
'A6XX_VPC_CNTL_0_PRIMIDLOC__MASK',
'A6XX_VPC_CNTL_0_PRIMIDLOC__SHIFT', 'A6XX_VPC_CNTL_0_VARYING',
'A6XX_VPC_CNTL_0_VIEWIDLOC__MASK',
'A6XX_VPC_CNTL_0_VIEWIDLOC__SHIFT',
'A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK',
'A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT',
'A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK',
'A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT',
'A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__MASK',
'A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__SHIFT',
'A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__MASK',
'A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__SHIFT',
'A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__MASK',
'A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__SHIFT',
'A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_MASK__MASK',
'A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_MASK__SHIFT',
'A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__MASK',
'A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__SHIFT',
'A6XX_VPC_DS_LAYER_CNTL_SHADINGRATELOC__MASK',
'A6XX_VPC_DS_LAYER_CNTL_SHADINGRATELOC__SHIFT',
'A6XX_VPC_DS_LAYER_CNTL_V2_LAYERLOC__MASK',
'A6XX_VPC_DS_LAYER_CNTL_V2_LAYERLOC__SHIFT',
'A6XX_VPC_DS_LAYER_CNTL_V2_SHADINGRATELOC__MASK',
'A6XX_VPC_DS_LAYER_CNTL_V2_SHADINGRATELOC__SHIFT',
'A6XX_VPC_DS_LAYER_CNTL_V2_VIEWLOC__MASK',
'A6XX_VPC_DS_LAYER_CNTL_V2_VIEWLOC__SHIFT',
'A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__MASK',
'A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__SHIFT',
'A6XX_VPC_DS_PACK_EXTRAPOS__MASK',
'A6XX_VPC_DS_PACK_EXTRAPOS__SHIFT',
'A6XX_VPC_DS_PACK_POSITIONLOC__MASK',
'A6XX_VPC_DS_PACK_POSITIONLOC__SHIFT',
'A6XX_VPC_DS_PACK_PSIZELOC__MASK',
'A6XX_VPC_DS_PACK_PSIZELOC__SHIFT',
'A6XX_VPC_DS_PACK_STRIDE_IN_VPC__MASK',
'A6XX_VPC_DS_PACK_STRIDE_IN_VPC__SHIFT',
'A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK',
'A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT',
'A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK',
'A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT',
'A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__MASK',
'A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__SHIFT',
'A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__MASK',
'A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__SHIFT',
'A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__MASK',
'A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__SHIFT',
'A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_MASK__MASK',
'A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_MASK__SHIFT',
'A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__MASK',
'A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__SHIFT',
'A6XX_VPC_GS_LAYER_CNTL_SHADINGRATELOC__MASK',
'A6XX_VPC_GS_LAYER_CNTL_SHADINGRATELOC__SHIFT',
'A6XX_VPC_GS_LAYER_CNTL_V2_LAYERLOC__MASK',
'A6XX_VPC_GS_LAYER_CNTL_V2_LAYERLOC__SHIFT',
'A6XX_VPC_GS_LAYER_CNTL_V2_SHADINGRATELOC__MASK',
'A6XX_VPC_GS_LAYER_CNTL_V2_SHADINGRATELOC__SHIFT',
'A6XX_VPC_GS_LAYER_CNTL_V2_VIEWLOC__MASK',
'A6XX_VPC_GS_LAYER_CNTL_V2_VIEWLOC__SHIFT',
'A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__MASK',
'A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__SHIFT',
'A6XX_VPC_GS_PACK_EXTRAPOS__MASK',
'A6XX_VPC_GS_PACK_EXTRAPOS__SHIFT',
'A6XX_VPC_GS_PACK_POSITIONLOC__MASK',
'A6XX_VPC_GS_PACK_POSITIONLOC__SHIFT',
'A6XX_VPC_GS_PACK_PSIZELOC__MASK',
'A6XX_VPC_GS_PACK_PSIZELOC__SHIFT',
'A6XX_VPC_GS_PACK_STRIDE_IN_VPC__MASK',
'A6XX_VPC_GS_PACK_STRIDE_IN_VPC__SHIFT',
'A6XX_VPC_GS_PARAM_LINELENGTHLOC__MASK',
'A6XX_VPC_GS_PARAM_LINELENGTHLOC__SHIFT',
'A6XX_VPC_POINT_COORD_INVERT_INVERT',
'A6XX_VPC_POLYGON_MODE_MODE__MASK',
'A6XX_VPC_POLYGON_MODE_MODE__SHIFT',
'A6XX_VPC_SO_CNTL_ADDR__MASK', 'A6XX_VPC_SO_CNTL_ADDR__SHIFT',
'A6XX_VPC_SO_CNTL_RESET', 'A6XX_VPC_SO_DISABLE_DISABLE',
'A6XX_VPC_SO_PROG_A_BUF__MASK', 'A6XX_VPC_SO_PROG_A_BUF__SHIFT',
'A6XX_VPC_SO_PROG_A_EN', 'A6XX_VPC_SO_PROG_A_OFF__MASK',
'A6XX_VPC_SO_PROG_A_OFF__SHIFT', 'A6XX_VPC_SO_PROG_B_BUF__MASK',
'A6XX_VPC_SO_PROG_B_BUF__SHIFT', 'A6XX_VPC_SO_PROG_B_EN',
'A6XX_VPC_SO_PROG_B_OFF__MASK', 'A6XX_VPC_SO_PROG_B_OFF__SHIFT',
'A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__MASK',
'A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__SHIFT',
'A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__MASK',
'A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__SHIFT',
'A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__MASK',
'A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__SHIFT',
'A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__MASK',
'A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__SHIFT',
'A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__MASK',
'A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__SHIFT',
'A6XX_VPC_UNKNOWN_9107_RASTER_DISCARD',
'A6XX_VPC_UNKNOWN_9107_UNK2',
'A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK',
'A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT',
'A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK',
'A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT',
'A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__MASK',
'A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__SHIFT',
'A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__MASK',
'A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__SHIFT',
'A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__MASK',
'A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__SHIFT',
'A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_MASK__MASK',
'A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_MASK__SHIFT',
'A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__MASK',
'A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__SHIFT',
'A6XX_VPC_VS_LAYER_CNTL_SHADINGRATELOC__MASK',
'A6XX_VPC_VS_LAYER_CNTL_SHADINGRATELOC__SHIFT',
'A6XX_VPC_VS_LAYER_CNTL_V2_LAYERLOC__MASK',
'A6XX_VPC_VS_LAYER_CNTL_V2_LAYERLOC__SHIFT',
'A6XX_VPC_VS_LAYER_CNTL_V2_SHADINGRATELOC__MASK',
'A6XX_VPC_VS_LAYER_CNTL_V2_SHADINGRATELOC__SHIFT',
'A6XX_VPC_VS_LAYER_CNTL_V2_VIEWLOC__MASK',
'A6XX_VPC_VS_LAYER_CNTL_V2_VIEWLOC__SHIFT',
'A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__MASK',
'A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__SHIFT',
'A6XX_VPC_VS_PACK_EXTRAPOS__MASK',
'A6XX_VPC_VS_PACK_EXTRAPOS__SHIFT',
'A6XX_VPC_VS_PACK_POSITIONLOC__MASK',
'A6XX_VPC_VS_PACK_POSITIONLOC__SHIFT',
'A6XX_VPC_VS_PACK_PSIZELOC__MASK',
'A6XX_VPC_VS_PACK_PSIZELOC__SHIFT',
'A6XX_VPC_VS_PACK_STRIDE_IN_VPC__MASK',
'A6XX_VPC_VS_PACK_STRIDE_IN_VPC__SHIFT',
'A6XX_VSC_BIN_COUNT_NX__MASK', 'A6XX_VSC_BIN_COUNT_NX__SHIFT',
'A6XX_VSC_BIN_COUNT_NY__MASK', 'A6XX_VSC_BIN_COUNT_NY__SHIFT',
'A6XX_VSC_BIN_SIZE_HEIGHT__MASK',
'A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT',
'A6XX_VSC_BIN_SIZE_WIDTH__MASK', 'A6XX_VSC_BIN_SIZE_WIDTH__SHIFT',
'A6XX_VSC_PIPE_CONFIG_REG_H__MASK',
'A6XX_VSC_PIPE_CONFIG_REG_H__SHIFT',
'A6XX_VSC_PIPE_CONFIG_REG_W__MASK',
'A6XX_VSC_PIPE_CONFIG_REG_W__SHIFT',
'A6XX_VSC_PIPE_CONFIG_REG_X__MASK',
'A6XX_VSC_PIPE_CONFIG_REG_X__SHIFT',
'A6XX_VSC_PIPE_CONFIG_REG_Y__MASK',
'A6XX_VSC_PIPE_CONFIG_REG_Y__SHIFT', 'A6XX_XML', 'A7XX',
'A7XX_CLUSTER_FE', 'A7XX_CLUSTER_GRAS', 'A7XX_CLUSTER_NONE',
'A7XX_CLUSTER_PC_VS', 'A7XX_CLUSTER_PS', 'A7XX_CLUSTER_SP_PS',
'A7XX_CLUSTER_SP_VS', 'A7XX_CLUSTER_VPC_PS',
'A7XX_CP_APERTURE_CNTL_CD_CLUSTER__MASK',
'A7XX_CP_APERTURE_CNTL_CD_CLUSTER__SHIFT',
'A7XX_CP_APERTURE_CNTL_CD_CONTEXT__MASK',
'A7XX_CP_APERTURE_CNTL_CD_CONTEXT__SHIFT',
'A7XX_CP_APERTURE_CNTL_CD_PIPE__MASK',
'A7XX_CP_APERTURE_CNTL_CD_PIPE__SHIFT',
'A7XX_CP_APERTURE_CNTL_HOST_CLUSTER__MASK',
'A7XX_CP_APERTURE_CNTL_HOST_CLUSTER__SHIFT',
'A7XX_CP_APERTURE_CNTL_HOST_CONTEXT__MASK',
'A7XX_CP_APERTURE_CNTL_HOST_CONTEXT__SHIFT',
'A7XX_CP_APERTURE_CNTL_HOST_PIPE__MASK',
'A7XX_CP_APERTURE_CNTL_HOST_PIPE__SHIFT',
'A7XX_CX_MISC_SW_FUSE_VALUE_FASTBLEND',
'A7XX_CX_MISC_SW_FUSE_VALUE_LPAC',
'A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING', 'A7XX_DBGBUS_CCHE_0',
'A7XX_DBGBUS_CCHE_1', 'A7XX_DBGBUS_CCHE_2', 'A7XX_DBGBUS_CCU_0',
'A7XX_DBGBUS_CCU_1', 'A7XX_DBGBUS_CCU_2', 'A7XX_DBGBUS_CCU_3',
'A7XX_DBGBUS_CCU_4', 'A7XX_DBGBUS_CCU_5', 'A7XX_DBGBUS_CGC_CORE',
'A7XX_DBGBUS_CGC_SUBCORE', 'A7XX_DBGBUS_COM_0',
'A7XX_DBGBUS_CP_0_0', 'A7XX_DBGBUS_CP_0_1', 'A7XX_DBGBUS_CX',
'A7XX_DBGBUS_DBGC', 'A7XX_DBGBUS_GBIF_CX', 'A7XX_DBGBUS_GBIF_GX',
'A7XX_DBGBUS_GMU_CX', 'A7XX_DBGBUS_GMU_GX', 'A7XX_DBGBUS_GPC_BR',
'A7XX_DBGBUS_GPC_BV', 'A7XX_DBGBUS_HLSQ',
'A7XX_DBGBUS_HLSQ_DP_STR_0', 'A7XX_DBGBUS_HLSQ_DP_STR_1',
'A7XX_DBGBUS_HLSQ_DP_STR_2', 'A7XX_DBGBUS_HLSQ_DP_STR_3',
'A7XX_DBGBUS_HLSQ_DP_STR_4', 'A7XX_DBGBUS_HLSQ_DP_STR_5',
'A7XX_DBGBUS_HLSQ_SPTP', 'A7XX_DBGBUS_LARC', 'A7XX_DBGBUS_LRZ_BR',
'A7XX_DBGBUS_LRZ_BV', 'A7XX_DBGBUS_PC_BR', 'A7XX_DBGBUS_PC_BV',
'A7XX_DBGBUS_RAS_BR', 'A7XX_DBGBUS_RAS_BV', 'A7XX_DBGBUS_RBBM',
'A7XX_DBGBUS_RB_0', 'A7XX_DBGBUS_RB_1', 'A7XX_DBGBUS_RB_2',
'A7XX_DBGBUS_RB_3', 'A7XX_DBGBUS_RB_4', 'A7XX_DBGBUS_RB_5',
'A7XX_DBGBUS_TESS_BR', 'A7XX_DBGBUS_TESS_BV', 'A7XX_DBGBUS_TP_0',
'A7XX_DBGBUS_TP_1', 'A7XX_DBGBUS_TP_10', 'A7XX_DBGBUS_TP_11',
'A7XX_DBGBUS_TP_2', 'A7XX_DBGBUS_TP_3', 'A7XX_DBGBUS_TP_4',
'A7XX_DBGBUS_TP_5', 'A7XX_DBGBUS_TP_6', 'A7XX_DBGBUS_TP_7',
'A7XX_DBGBUS_TP_8', 'A7XX_DBGBUS_TP_9', 'A7XX_DBGBUS_TSE_BR',
'A7XX_DBGBUS_TSE_BV', 'A7XX_DBGBUS_UCHE_0', 'A7XX_DBGBUS_UCHE_1',
'A7XX_DBGBUS_UCHE_WRAPPER', 'A7XX_DBGBUS_UFC_0',
'A7XX_DBGBUS_UFC_1', 'A7XX_DBGBUS_UFC_DSTR_0',
'A7XX_DBGBUS_UFC_DSTR_1', 'A7XX_DBGBUS_UFC_DSTR_2',
'A7XX_DBGBUS_USPTP_0', 'A7XX_DBGBUS_USPTP_1',
'A7XX_DBGBUS_USPTP_10', 'A7XX_DBGBUS_USPTP_11',
'A7XX_DBGBUS_USPTP_2', 'A7XX_DBGBUS_USPTP_3',
'A7XX_DBGBUS_USPTP_4', 'A7XX_DBGBUS_USPTP_5',
'A7XX_DBGBUS_USPTP_6', 'A7XX_DBGBUS_USPTP_7',
'A7XX_DBGBUS_USPTP_8', 'A7XX_DBGBUS_USPTP_9', 'A7XX_DBGBUS_USP_0',
'A7XX_DBGBUS_USP_1', 'A7XX_DBGBUS_USP_2', 'A7XX_DBGBUS_USP_3',
'A7XX_DBGBUS_USP_4', 'A7XX_DBGBUS_USP_5', 'A7XX_DBGBUS_VFDP_BR',
'A7XX_DBGBUS_VFDP_BV', 'A7XX_DBGBUS_VFD_BR_0',
'A7XX_DBGBUS_VFD_BR_1', 'A7XX_DBGBUS_VFD_BR_2',
'A7XX_DBGBUS_VFD_BR_3', 'A7XX_DBGBUS_VFD_BR_4',
'A7XX_DBGBUS_VFD_BR_5', 'A7XX_DBGBUS_VFD_BR_6',
'A7XX_DBGBUS_VFD_BR_7', 'A7XX_DBGBUS_VFD_BV_0',
'A7XX_DBGBUS_VFD_BV_1', 'A7XX_DBGBUS_VFD_BV_2',
'A7XX_DBGBUS_VFD_BV_3', 'A7XX_DBGBUS_VPC_BR',
'A7XX_DBGBUS_VPC_BV', 'A7XX_DBGBUS_VPC_DSTR_0',
'A7XX_DBGBUS_VPC_DSTR_1', 'A7XX_DBGBUS_VPC_DSTR_2',
'A7XX_DBGBUS_VSC', 'A7XX_GRAS_LRZ_CLEAR_DEPTH_F32__MASK',
'A7XX_GRAS_LRZ_CLEAR_DEPTH_F32__SHIFT',
'A7XX_GRAS_LRZ_CNTL2_DISABLE_ON_WRONG_DIR',
'A7XX_GRAS_LRZ_CNTL2_FC_ENABLE',
'A7XX_GRAS_LRZ_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK',
'A7XX_GRAS_LRZ_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT',
'A7XX_GRAS_LRZ_DEPTH_BUFFER_INFO_UNK3',
'A7XX_GRAS_SU_RENDER_CNTL_BINNING', 'A7XX_HLSQ_BACKEND_META',
'A7XX_HLSQ_BV_BE_META', 'A7XX_HLSQ_CHUNK_CPS_RAM',
'A7XX_HLSQ_CHUNK_CPS_RAM_TAG', 'A7XX_HLSQ_CHUNK_CVS_RAM',
'A7XX_HLSQ_CHUNK_CVS_RAM_TAG',
'A7XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK',
'A7XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT',
'A7XX_HLSQ_CONTROL_2_REG_CENTERRHW__MASK',
'A7XX_HLSQ_CONTROL_2_REG_CENTERRHW__SHIFT',
'A7XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK',
'A7XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT',
'A7XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK',
'A7XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT',
'A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK',
'A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT',
'A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK',
'A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT',
'A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK',
'A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT',
'A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK',
'A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT',
'A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK',
'A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT',
'A7XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK',
'A7XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT',
'A7XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK',
'A7XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT',
'A7XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK',
'A7XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT',
'A7XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK',
'A7XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT',
'A7XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__MASK',
'A7XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__SHIFT',
'A7XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__MASK',
'A7XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__SHIFT',
'A7XX_HLSQ_CPS_BE_CTXT_BUF_RAM_TAG', 'A7XX_HLSQ_CPS_MISC_RAM',
'A7XX_HLSQ_CPS_MISC_RAM_1', 'A7XX_HLSQ_CPS_MISC_RAM_TAG',
'A7XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__MASK',
'A7XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT',
'A7XX_HLSQ_CS_CNTL_1_THREADSIZE__MASK',
'A7XX_HLSQ_CS_CNTL_1_THREADSIZE__SHIFT',
'A7XX_HLSQ_CS_CNTL_1_UNK11', 'A7XX_HLSQ_CS_CNTL_1_UNK22',
'A7XX_HLSQ_CS_CNTL_1_UNK26', 'A7XX_HLSQ_CS_CNTL_1_YALIGN__MASK',
'A7XX_HLSQ_CS_CNTL_1_YALIGN__SHIFT',
'A7XX_HLSQ_CS_CNTL_CONSTLEN__MASK',
'A7XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT', 'A7XX_HLSQ_CS_CNTL_ENABLED',
'A7XX_HLSQ_CS_CNTL_READ_IMM_SHARED_CONSTS',
'A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEX__MASK',
'A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEX__SHIFT',
'A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEY__MASK',
'A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEY__SHIFT',
'A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEZ__MASK',
'A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEZ__SHIFT',
'A7XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK',
'A7XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT',
'A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK',
'A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT',
'A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK',
'A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT',
'A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK',
'A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT',
'A7XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK',
'A7XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT',
'A7XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK',
'A7XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT',
'A7XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK',
'A7XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT',
'A7XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK',
'A7XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT',
'A7XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK',
'A7XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT',
'A7XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK',
'A7XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT',
'A7XX_HLSQ_CVS_BE_CTXT_BUF_RAM_TAG', 'A7XX_HLSQ_CVS_MISC_RAM',
'A7XX_HLSQ_CVS_MISC_RAM_TAG', 'A7XX_HLSQ_DATAPATH_DSTR_META',
'A7XX_HLSQ_DATAPATH_META',
'A7XX_HLSQ_DISPATCH_CMD_STATE_ID__MASK',
'A7XX_HLSQ_DISPATCH_CMD_STATE_ID__SHIFT', 'A7XX_HLSQ_DP',
'A7XX_HLSQ_DP_STR', 'A7XX_HLSQ_DRAW_CMD_STATE_ID__MASK',
'A7XX_HLSQ_DRAW_CMD_STATE_ID__SHIFT',
'A7XX_HLSQ_DS_CNTL_CONSTLEN__MASK',
'A7XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT', 'A7XX_HLSQ_DS_CNTL_ENABLED',
'A7XX_HLSQ_DS_CNTL_READ_IMM_SHARED_CONSTS',
'A7XX_HLSQ_EVENT_CMD_EVENT__MASK',
'A7XX_HLSQ_EVENT_CMD_EVENT__SHIFT',
'A7XX_HLSQ_EVENT_CMD_STATE_ID__MASK',
'A7XX_HLSQ_EVENT_CMD_STATE_ID__SHIFT', 'A7XX_HLSQ_FRONTEND_META',
'A7XX_HLSQ_FS_CNTL_0_THREADSIZE__MASK',
'A7XX_HLSQ_FS_CNTL_0_THREADSIZE__SHIFT',
'A7XX_HLSQ_FS_CNTL_0_UNK2__MASK',
'A7XX_HLSQ_FS_CNTL_0_UNK2__SHIFT', 'A7XX_HLSQ_FS_CNTL_0_VARYINGS',
'A7XX_HLSQ_FS_CNTL_CONSTLEN__MASK',
'A7XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT', 'A7XX_HLSQ_FS_CNTL_ENABLED',
'A7XX_HLSQ_FS_CNTL_READ_IMM_SHARED_CONSTS',
'A7XX_HLSQ_FS_UNKNOWN_A9AA_CONSTS_LOAD_DISABLE',
'A7XX_HLSQ_GFX_CPS_BE_CTXT_BUF_RAM',
'A7XX_HLSQ_GFX_CPS_CONST_RAM', 'A7XX_HLSQ_GFX_CPS_CONST_RAM_TAG',
'A7XX_HLSQ_GFX_CVS_BE_CTXT_BUF_RAM',
'A7XX_HLSQ_GFX_CVS_CONST_RAM', 'A7XX_HLSQ_GFX_CVS_CONST_RAM_TAG',
'A7XX_HLSQ_GFX_LOCAL_MISC_RAM',
'A7XX_HLSQ_GFX_LOCAL_MISC_RAM_TAG',
'A7XX_HLSQ_GS_CNTL_CONSTLEN__MASK',
'A7XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT', 'A7XX_HLSQ_GS_CNTL_ENABLED',
'A7XX_HLSQ_GS_CNTL_READ_IMM_SHARED_CONSTS',
'A7XX_HLSQ_HS_CNTL_CONSTLEN__MASK',
'A7XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT', 'A7XX_HLSQ_HS_CNTL_ENABLED',
'A7XX_HLSQ_HS_CNTL_READ_IMM_SHARED_CONSTS',
'A7XX_HLSQ_ICB_CPS_CB_BASE_TAG', 'A7XX_HLSQ_ICB_CVS_CB_BASE_TAG',
'A7XX_HLSQ_INDIRECT_META', 'A7XX_HLSQ_INST_RAM',
'A7XX_HLSQ_INST_RAM_1', 'A7XX_HLSQ_INST_RAM_2',
'A7XX_HLSQ_INST_RAM_TAG',
'A7XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__MASK',
'A7XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__SHIFT',
'A7XX_HLSQ_INVALIDATE_CMD_CS_IBO',
'A7XX_HLSQ_INVALIDATE_CMD_CS_STATE',
'A7XX_HLSQ_INVALIDATE_CMD_DS_STATE',
'A7XX_HLSQ_INVALIDATE_CMD_FS_STATE',
'A7XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__MASK',
'A7XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__SHIFT',
'A7XX_HLSQ_INVALIDATE_CMD_GFX_IBO',
'A7XX_HLSQ_INVALIDATE_CMD_GS_STATE',
'A7XX_HLSQ_INVALIDATE_CMD_HS_STATE',
'A7XX_HLSQ_INVALIDATE_CMD_VS_STATE', 'A7XX_HLSQ_L2STC_INFO_CMD',
'A7XX_HLSQ_L2STC_TAG_RAM', 'A7XX_HLSQ_STATE',
'A7XX_HLSQ_STPROC_META',
'A7XX_HLSQ_UNKNOWN_A9AE_SYSVAL_REGS_COUNT__MASK',
'A7XX_HLSQ_UNKNOWN_A9AE_SYSVAL_REGS_COUNT__SHIFT',
'A7XX_HLSQ_UNKNOWN_A9AE_UNK8', 'A7XX_HLSQ_UNKNOWN_A9AE_UNK9',
'A7XX_HLSQ_VS_CNTL_CONSTLEN__MASK',
'A7XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT', 'A7XX_HLSQ_VS_CNTL_ENABLED',
'A7XX_HLSQ_VS_CNTL_READ_IMM_SHARED_CONSTS',
'A7XX_PC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__MASK',
'A7XX_PC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__SHIFT',
'A7XX_PC_POLYGON_MODE_MODE__MASK',
'A7XX_PC_POLYGON_MODE_MODE__SHIFT', 'A7XX_PC_RASTER_CNTL_DISCARD',
'A7XX_PC_RASTER_CNTL_STREAM__MASK',
'A7XX_PC_RASTER_CNTL_STREAM__SHIFT',
'A7XX_PC_RASTER_CNTL_V2_DISCARD',
'A7XX_PC_RASTER_CNTL_V2_STREAM__MASK',
'A7XX_PC_RASTER_CNTL_V2_STREAM__SHIFT', 'A7XX_PERF_BYPC_FULL',
'A7XX_PERF_BYPC_FULL_CCHE_STALL', 'A7XX_PERF_BYPC_VHUB_STALL',
'A7XX_PERF_BYPD_FULL', 'A7XX_PERF_BYPD_FULL_GBIF_STALL',
'A7XX_PERF_CCHE_BANK_REQ0', 'A7XX_PERF_CCHE_BANK_REQ1',
'A7XX_PERF_CCHE_BANK_REQ10', 'A7XX_PERF_CCHE_BANK_REQ11',
'A7XX_PERF_CCHE_BANK_REQ12', 'A7XX_PERF_CCHE_BANK_REQ13',
'A7XX_PERF_CCHE_BANK_REQ14', 'A7XX_PERF_CCHE_BANK_REQ15',
'A7XX_PERF_CCHE_BANK_REQ2', 'A7XX_PERF_CCHE_BANK_REQ3',
'A7XX_PERF_CCHE_BANK_REQ4', 'A7XX_PERF_CCHE_BANK_REQ5',
'A7XX_PERF_CCHE_BANK_REQ6', 'A7XX_PERF_CCHE_BANK_REQ7',
'A7XX_PERF_CCHE_BANK_REQ8', 'A7XX_PERF_CCHE_BANK_REQ9',
'A7XX_PERF_CCHE_BUSY_CYCLES', 'A7XX_PERF_CCHE_DBANK_CONFLICT',
'A7XX_PERF_CCHE_DPH_QUEUE_FULL', 'A7XX_PERF_CCHE_GBANK_REQ0',
'A7XX_PERF_CCHE_GBANK_REQ1', 'A7XX_PERF_CCHE_GBANK_REQ2',
'A7XX_PERF_CCHE_GBANK_REQ3',
'A7XX_PERF_CCHE_GMEM0_LOCAL_RD_REQUEST',
'A7XX_PERF_CCHE_GMEM0_LOCAL_WR_REQUEST',
'A7XX_PERF_CCHE_GMEM0_REMOTE_RD_REQUEST',
'A7XX_PERF_CCHE_GMEM0_REMOTE_WR_REQUEST',
'A7XX_PERF_CCHE_GMEM1_LOCAL_RD_REQUEST',
'A7XX_PERF_CCHE_GMEM1_LOCAL_WR_REQUEST',
'A7XX_PERF_CCHE_GMEM1_REMOTE_RD_REQUEST',
'A7XX_PERF_CCHE_GMEM1_REMOTE_WR_REQUEST',
'A7XX_PERF_CCHE_GMEM_READ_BEATS_SP',
'A7XX_PERF_CCHE_GMEM_READ_BEATS_TP',
'A7XX_PERF_CCHE_GMEM_READ_BEATS_VFD',
'A7XX_PERF_CCHE_GMEM_READ_BEATS_VPC',
'A7XX_PERF_CCHE_OPH_QUEUE_FULL', 'A7XX_PERF_CCHE_RAM_READ_REQ',
'A7XX_PERF_CCHE_RAM_WRITE_REQ',
'A7XX_PERF_CCHE_READ_REQUESTS_GMEM',
'A7XX_PERF_CCHE_READ_REQUESTS_LRZ',
'A7XX_PERF_CCHE_READ_REQUESTS_SP_GBIF',
'A7XX_PERF_CCHE_READ_REQUESTS_SP_GMEM',
'A7XX_PERF_CCHE_READ_REQUESTS_SP_TOTAL',
'A7XX_PERF_CCHE_READ_REQUESTS_SP_UBWC',
'A7XX_PERF_CCHE_READ_REQUESTS_TP_GBIF',
'A7XX_PERF_CCHE_READ_REQUESTS_TP_GMEM',
'A7XX_PERF_CCHE_READ_REQUESTS_TP_TOTAL',
'A7XX_PERF_CCHE_READ_REQUESTS_TP_UBWC',
'A7XX_PERF_CCHE_READ_REQUESTS_VFD_TOTAL',
'A7XX_PERF_CCHE_READ_REQUESTS_VPC',
'A7XX_PERF_CCHE_READ_REQUEST_VFD_GBIF',
'A7XX_PERF_CCHE_READ_REQUEST_VFD_GMEM',
'A7XX_PERF_CCHE_STALL_CYCLES_TP',
'A7XX_PERF_CCHE_STALL_CYCLES_UCHE',
'A7XX_PERF_CCHE_TPH_CONFLICT_CL', 'A7XX_PERF_CCHE_TPH_EXT_FULL',
'A7XX_PERF_CCHE_TPH_QUEUE_FULL', 'A7XX_PERF_CCHE_TPH_REF_FULL',
'A7XX_PERF_CCHE_TPH_VICTIM_FULL',
'A7XX_PERF_CCHE_UCHE_LATENCY_CYCLES',
'A7XX_PERF_CCHE_UCHE_LATENCY_SAMPLES',
'A7XX_PERF_CCHE_UCHE_READ_BEATS_CH0',
'A7XX_PERF_CCHE_UCHE_READ_BEATS_CH1',
'A7XX_PERF_CCHE_UCHE_READ_BEATS_LRZ',
'A7XX_PERF_CCHE_UCHE_READ_BEATS_SP',
'A7XX_PERF_CCHE_UCHE_READ_BEATS_TP',
'A7XX_PERF_CCHE_UCHE_READ_BEATS_VFD',
'A7XX_PERF_CCHE_UCHE_READ_BEATS_VPC',
'A7XX_PERF_CCHE_UCHE_STALL_WRITE_DATA',
'A7XX_PERF_CCHE_WACK_QUEUE_FULL',
'A7XX_PERF_CCHE_WRITE_REQUESTS_GMEM',
'A7XX_PERF_CCHE_WRITE_REQUESTS_LRZ',
'A7XX_PERF_CCHE_WRITE_REQUESTS_SP', 'A7XX_PERF_CCU_2D_RD_REQ',
'A7XX_PERF_CCU_2D_WR_REQ', 'A7XX_PERF_CCU_BUSY_CYCLES',
'A7XX_PERF_CCU_COLOR_BLOCKS', 'A7XX_PERF_CCU_COLOR_BLOCK_HIT',
'A7XX_PERF_CCU_COLOR_EVB_STALL',
'A7XX_PERF_CCU_COLOR_RENDER_CONCURRENT',
'A7XX_PERF_CCU_COLOR_RESOLVE_AFTER_RENDER',
'A7XX_PERF_CCU_COLOR_RESOLVE_DROPPED',
'A7XX_PERF_CCU_DEPTH_BLOCKS', 'A7XX_PERF_CCU_DEPTH_BLOCK_HIT',
'A7XX_PERF_CCU_DEPTH_RENDER_CONCURRENT',
'A7XX_PERF_CCU_DEPTH_RESOLVE_AFTER_RENDER',
'A7XX_PERF_CCU_DEPTH_RESOLVE_DROPPED',
'A7XX_PERF_CCU_FULL_SURFACE_RESOLVE_CYCLES',
'A7XX_PERF_CCU_GMEM_COLOR_READ_4AA',
'A7XX_PERF_CCU_GMEM_COLOR_READ_4AA_FULL',
'A7XX_PERF_CCU_GMEM_EXTRA_DEPTH_READ', 'A7XX_PERF_CCU_GMEM_READ',
'A7XX_PERF_CCU_GMEM_WRITE', 'A7XX_PERF_CCU_NEVER_COUNT',
'A7XX_PERF_CCU_PARTIAL_BLOCK_READ',
'A7XX_PERF_CCU_RENDER_OVERLAP_CRE_C',
'A7XX_PERF_CCU_RENDER_OVERLAP_CRE_Z',
'A7XX_PERF_CCU_RENDER_OVERLAP_FULL_SURFACE_RESOLVE',
'A7XX_PERF_CCU_RENDER_STALL_BY_CRE_C',
'A7XX_PERF_CCU_RENDER_STALL_BY_CRE_Z',
'A7XX_PERF_CCU_RESERVED_100', 'A7XX_PERF_CCU_RESERVED_101',
'A7XX_PERF_CCU_RESERVED_102', 'A7XX_PERF_CCU_RESERVED_103',
'A7XX_PERF_CCU_RESERVED_104', 'A7XX_PERF_CCU_RESERVED_105',
'A7XX_PERF_CCU_RESERVED_106', 'A7XX_PERF_CCU_RESERVED_107',
'A7XX_PERF_CCU_RESERVED_108', 'A7XX_PERF_CCU_RESERVED_109',
'A7XX_PERF_CCU_RESERVED_110', 'A7XX_PERF_CCU_RESERVED_111',
'A7XX_PERF_CCU_RESERVED_112', 'A7XX_PERF_CCU_RESERVED_113',
'A7XX_PERF_CCU_RESERVED_114', 'A7XX_PERF_CCU_RESERVED_115',
'A7XX_PERF_CCU_RESERVED_116', 'A7XX_PERF_CCU_RESERVED_117',
'A7XX_PERF_CCU_RESERVED_118', 'A7XX_PERF_CCU_RESERVED_119',
'A7XX_PERF_CCU_RESERVED_120', 'A7XX_PERF_CCU_RESERVED_121',
'A7XX_PERF_CCU_RESERVED_122', 'A7XX_PERF_CCU_RESERVED_123',
'A7XX_PERF_CCU_RESERVED_124', 'A7XX_PERF_CCU_RESERVED_125',
'A7XX_PERF_CCU_RESERVED_126', 'A7XX_PERF_CCU_RESERVED_127',
'A7XX_PERF_CCU_RESERVED_32', 'A7XX_PERF_CCU_RESERVED_33',
'A7XX_PERF_CCU_RESERVED_34', 'A7XX_PERF_CCU_RESERVED_35',
'A7XX_PERF_CCU_RESERVED_36', 'A7XX_PERF_CCU_RESERVED_37',
'A7XX_PERF_CCU_RESERVED_38', 'A7XX_PERF_CCU_RESERVED_39',
'A7XX_PERF_CCU_RESERVED_40', 'A7XX_PERF_CCU_RESERVED_41',
'A7XX_PERF_CCU_RESERVED_42', 'A7XX_PERF_CCU_RESERVED_43',
'A7XX_PERF_CCU_RESERVED_44', 'A7XX_PERF_CCU_RESERVED_45',
'A7XX_PERF_CCU_RESERVED_46', 'A7XX_PERF_CCU_RESERVED_47',
'A7XX_PERF_CCU_RESERVED_48', 'A7XX_PERF_CCU_RESERVED_49',
'A7XX_PERF_CCU_RESERVED_50', 'A7XX_PERF_CCU_RESERVED_51',
'A7XX_PERF_CCU_RESERVED_52', 'A7XX_PERF_CCU_RESERVED_53',
'A7XX_PERF_CCU_RESERVED_54', 'A7XX_PERF_CCU_RESERVED_55',
'A7XX_PERF_CCU_RESERVED_56', 'A7XX_PERF_CCU_RESERVED_57',
'A7XX_PERF_CCU_RESERVED_58', 'A7XX_PERF_CCU_RESERVED_59',
'A7XX_PERF_CCU_RESERVED_60', 'A7XX_PERF_CCU_RESERVED_61',
'A7XX_PERF_CCU_RESERVED_62', 'A7XX_PERF_CCU_RESERVED_63',
'A7XX_PERF_CCU_RESERVED_78', 'A7XX_PERF_CCU_RESERVED_79',
'A7XX_PERF_CCU_RESERVED_80', 'A7XX_PERF_CCU_RESERVED_81',
'A7XX_PERF_CCU_RESERVED_82', 'A7XX_PERF_CCU_RESERVED_83',
'A7XX_PERF_CCU_RESERVED_84', 'A7XX_PERF_CCU_RESERVED_85',
'A7XX_PERF_CCU_RESERVED_86', 'A7XX_PERF_CCU_RESERVED_87',
'A7XX_PERF_CCU_RESERVED_88', 'A7XX_PERF_CCU_RESERVED_89',
'A7XX_PERF_CCU_RESERVED_90', 'A7XX_PERF_CCU_RESERVED_91',
'A7XX_PERF_CCU_RESERVED_92', 'A7XX_PERF_CCU_RESERVED_93',
'A7XX_PERF_CCU_RESERVED_94', 'A7XX_PERF_CCU_RESERVED_95',
'A7XX_PERF_CCU_RESERVED_96', 'A7XX_PERF_CCU_RESERVED_97',
'A7XX_PERF_CCU_RESERVED_98', 'A7XX_PERF_CCU_RESERVED_99',
'A7XX_PERF_CCU_STALL_BY_FULL_SURFACE_RESOLVE',
'A7XX_PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN',
'A7XX_PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN',
'A7XX_PERF_CCU_UBWC_COLOR_BLOCKS_CONCURRENT',
'A7XX_PERF_CCU_UBWC_DEPTH_BLOCKS_CONCURRENT',
'A7XX_PERF_CMPDECMP_CDP_FILTER_HIT',
'A7XX_PERF_CMPDECMP_CDP_FILTER_MISS',
'A7XX_PERF_CMPDECMP_COLOR_READ_FLAG0_COUNT',
'A7XX_PERF_CMPDECMP_COLOR_READ_FLAG1_COUNT',
'A7XX_PERF_CMPDECMP_COLOR_READ_FLAG2_COUNT',
'A7XX_PERF_CMPDECMP_COLOR_READ_FLAG3_COUNT',
'A7XX_PERF_CMPDECMP_COLOR_READ_FLAG4_COUNT',
'A7XX_PERF_CMPDECMP_COLOR_READ_FLAG5_COUNT',
'A7XX_PERF_CMPDECMP_COLOR_READ_FLAG6_COUNT',
'A7XX_PERF_CMPDECMP_COLOR_READ_FLAG8_COUNT',
'A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT',
'A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT',
'A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT',
'A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT',
'A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT',
'A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT',
'A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT',
'A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT',
'A7XX_PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT',
'A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG0_COUNT',
'A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG1_COUNT',
'A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG2_COUNT',
'A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG3_COUNT',
'A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG4_COUNT',
'A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG5_COUNT',
'A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG6_COUNT',
'A7XX_PERF_CMPDECMP_DEPTH_READ_FLAG8_COUNT',
'A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT',
'A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT',
'A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT',
'A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT',
'A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT',
'A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT',
'A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT',
'A7XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT',
'A7XX_PERF_CMPDECMP_NEVER_COUNT',
'A7XX_PERF_CMPDECMP_STALL_CYCLES_ARB',
'A7XX_PERF_CMPDECMP_VBIF_LATENCY_CYCLES',
'A7XX_PERF_CMPDECMP_VBIF_LATENCY_SAMPLES',
'A7XX_PERF_CMPDECMP_VBIF_READ_DATA',
'A7XX_PERF_CMPDECMP_VBIF_READ_DATA_CCU',
'A7XX_PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0',
'A7XX_PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1',
'A7XX_PERF_CMPDECMP_VBIF_READ_REQUEST',
'A7XX_PERF_CMPDECMP_VBIF_WRITE_DATA',
'A7XX_PERF_CMPDECMP_VBIF_WRITE_DATA_CCU',
'A7XX_PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE',
'A7XX_PERF_CMPDECMP_VBIF_WRITE_REQUEST',
'A7XX_PERF_CP_AHB_STALL_SQE_GMU',
'A7XX_PERF_CP_AHB_STALL_SQE_RD_OTHER',
'A7XX_PERF_CP_AHB_STALL_SQE_WR_OTHER',
'A7XX_PERF_CP_AHB_WR_STALL_PRE_DRAWS',
'A7XX_PERF_CP_ALWAYS_COUNT', 'A7XX_PERF_CP_AQE_NUM_AS_CHUNKS',
'A7XX_PERF_CP_AQE_NUM_MS_CHUNKS', 'A7XX_PERF_CP_AQE_SQE_STALL',
'A7XX_PERF_CP_BUSY_CYCLES', 'A7XX_PERF_CP_BUSY_GFX_CORE_IDLE',
'A7XX_PERF_CP_CACHE_FLUSH', 'A7XX_PERF_CP_CLUSTER_FE_S_EMPTY',
'A7XX_PERF_CP_CLUSTER_FE_S_FULL',
'A7XX_PERF_CP_CLUSTER_FE_US_FULL',
'A7XX_PERF_CP_CLUSTER_FE_U_EMPTY',
'A7XX_PERF_CP_CLUSTER_GRAS_EMPTY',
'A7XX_PERF_CP_CLUSTER_GRAS_FULL', 'A7XX_PERF_CP_CLUSTER_PS_EMPTY',
'A7XX_PERF_CP_CLUSTER_PS_FULL',
'A7XX_PERF_CP_CLUSTER_SP_PS_EMPTY',
'A7XX_PERF_CP_CLUSTER_SP_PS_FULL',
'A7XX_PERF_CP_CLUSTER_SP_VS_EMPTY',
'A7XX_PERF_CP_CLUSTER_SP_VS_FULL',
'A7XX_PERF_CP_CLUSTER_VPC_PS_EMPTY',
'A7XX_PERF_CP_CLUSTER_VPC_PS_FULL',
'A7XX_PERF_CP_CLUSTER_VPC_US_EMPTY',
'A7XX_PERF_CP_CLUSTER_VPC_US_FULL',
'A7XX_PERF_CP_CLUSTER_VPC_VS_EMPTY',
'A7XX_PERF_CP_CLUSTER_VPC_VS_FULL', 'A7XX_PERF_CP_CONTEXT_DONE',
'A7XX_PERF_CP_DCACHE_HITS', 'A7XX_PERF_CP_DCACHE_MISSES',
'A7XX_PERF_CP_DCACHE_STALLS',
'A7XX_PERF_CP_DEAD_DRAWS_IN_BIN_RENDER',
'A7XX_PERF_CP_ICACHE_HITS', 'A7XX_PERF_CP_ICACHE_MISSES',
'A7XX_PERF_CP_ICACHE_STALL', 'A7XX_PERF_CP_ISR_CYCLES',
'A7XX_PERF_CP_LONG_PREEMPTIONS',
'A7XX_PERF_CP_MEMORY_POOL_ABOVE_THRESH',
'A7XX_PERF_CP_MEMORY_POOL_BELOW_THRESH',
'A7XX_PERF_CP_MEMORY_POOL_EMPTY',
'A7XX_PERF_CP_MEMORY_POOL_SYNC_STALL', 'A7XX_PERF_CP_MODE_SWITCH',
'A7XX_PERF_CP_NEVER_COUNT', 'A7XX_PERF_CP_NUM_PREEMPTIONS',
'A7XX_PERF_CP_OUTPUT_BLOCKED', 'A7XX_PERF_CP_PM4_DATA',
'A7XX_PERF_CP_PM4_HEADERS',
'A7XX_PERF_CP_PREDICATED_DRAWS_KILLED',
'A7XX_PERF_CP_PREEMPTION_REACTION_DELAY',
'A7XX_PERF_CP_PREEMPTION_SWITCH_IN_TIME',
'A7XX_PERF_CP_PREEMPTION_SWITCH_OUT_TIME',
'A7XX_PERF_CP_SQE_AQE_STARVE',
'A7XX_PERF_CP_SQE_CTXT_REG_BUNCH_EXEC',
'A7XX_PERF_CP_SQE_DRAW_EXEC', 'A7XX_PERF_CP_SQE_EXEC_PROFILED',
'A7XX_PERF_CP_SQE_IDLE', 'A7XX_PERF_CP_SQE_INSTR_COUNTER',
'A7XX_PERF_CP_SQE_I_CACHE_STARVE',
'A7XX_PERF_CP_SQE_LOAD_STATE_EXEC',
'A7XX_PERF_CP_SQE_MD8_STALL_CYCLES',
'A7XX_PERF_CP_SQE_MESH_EXEC_CYCLES',
'A7XX_PERF_CP_SQE_MRB_STARVE', 'A7XX_PERF_CP_SQE_PIPE_OUT_STALL',
'A7XX_PERF_CP_SQE_PM4_STARVE_FSDT',
'A7XX_PERF_CP_SQE_PM4_STARVE_IB1',
'A7XX_PERF_CP_SQE_PM4_STARVE_IB2',
'A7XX_PERF_CP_SQE_PM4_STARVE_IB3',
'A7XX_PERF_CP_SQE_PM4_STARVE_RB',
'A7XX_PERF_CP_SQE_PM4_STARVE_SDS',
'A7XX_PERF_CP_SQE_PM4_WFI_STALL', 'A7XX_PERF_CP_SQE_RRB_STARVE',
'A7XX_PERF_CP_SQE_SAVE_SDS_STATE', 'A7XX_PERF_CP_SQE_SYNC_STALL',
'A7XX_PERF_CP_SQE_SYS_WFI_STALL', 'A7XX_PERF_CP_SQE_T4_EXEC',
'A7XX_PERF_CP_SQE_VSD_STARVE',
'A7XX_PERF_CP_S_SKEW_BUFFER_ABOVE_THRESH',
'A7XX_PERF_CP_S_SKEW_BUFFER_FULL', 'A7XX_PERF_CP_VBIF_READ_BEATS',
'A7XX_PERF_CP_VBIF_WRITE_BEATS', 'A7XX_PERF_CP_VSD_DECODE_STARVE',
'A7XX_PERF_CP_WAIT_ON_OTHER_PIPE', 'A7XX_PERF_CP_ZPASS_DONE',
'A7XX_PERF_CRE_CONCURRENT_RESOLVE_EVENTS',
'A7XX_PERF_CRE_DROPPED_CLEAR_EVENTS',
'A7XX_PERF_CRE_DR_UFC_PREFTCH_REQUESTS',
'A7XX_PERF_CRE_LRZ_ST_BLOCKS_CONCURRENT',
'A7XX_PERF_CRE_RESOLVE_CDP_PREFETCH_REQUESTS',
'A7XX_PERF_CRE_RESOLVE_EVENTS',
'A7XX_PERF_CRE_RESOLVE_UFC_PREFETCH_REQUESTS',
'A7XX_PERF_CRE_SP_UFC_PREFETCH_REQUESTS',
'A7XX_PERF_CRE_ST_BLOCKS_CONCURRENT',
'A7XX_PERF_DHUB_PTABLE_FULL',
'A7XX_PERF_GBIF_AXI0_READ_DATA_BEATS_TOTAL',
'A7XX_PERF_GBIF_AXI0_READ_REQUESTS_TOTAL',
'A7XX_PERF_GBIF_AXI0_WRITE_DATA_BEATS_TOTAL',
'A7XX_PERF_GBIF_AXI0_WRITE_REQUESTS_TOTAL',
'A7XX_PERF_GBIF_AXI1_READ_DATA_BEATS_TOTAL',
'A7XX_PERF_GBIF_AXI1_READ_REQUESTS_TOTAL',
'A7XX_PERF_GBIF_AXI1_WRITE_DATA_BEATS_TOTAL',
'A7XX_PERF_GBIF_AXI1_WRITE_REQUESTS_TOTAL',
'A7XX_PERF_GBIF_AXI_ALL_WRITE_DATA_HELD_OFF',
'A7XX_PERF_GBIF_AXI_CH0_REQUEST_HELD_OFF',
'A7XX_PERF_GBIF_AXI_CH0_WRITE_DATA_HELD_OFF',
'A7XX_PERF_GBIF_AXI_CH1_REQUEST_HELD_OFF',
'A7XX_PERF_GBIF_AXI_CH1_WRITE_DATA_HELD_OFF',
'A7XX_PERF_GBIF_AXI_REQUEST_HELD_OFF',
'A7XX_PERF_GBIF_CYCLES_CH0_HELD_OFF_RD_ALL',
'A7XX_PERF_GBIF_CYCLES_CH0_HELD_OFF_WR_ALL',
'A7XX_PERF_GBIF_CYCLES_CH1_HELD_OFF_RD_ALL',
'A7XX_PERF_GBIF_CYCLES_CH1_HELD_OFF_WR_ALL',
'A7XX_PERF_GBIF_NEVER_COUNT',
'A7XX_PERF_GBIF_READ_AND_WRITE_BEAT_ALL_CHANNELS',
'A7XX_PERF_GBIF_READ_BEAT_ALL_CHANNELS',
'A7XX_PERF_GBIF_RESERVED_1', 'A7XX_PERF_GBIF_RESERVED_100',
'A7XX_PERF_GBIF_RESERVED_101', 'A7XX_PERF_GBIF_RESERVED_102',
'A7XX_PERF_GBIF_RESERVED_103', 'A7XX_PERF_GBIF_RESERVED_104',
'A7XX_PERF_GBIF_RESERVED_105', 'A7XX_PERF_GBIF_RESERVED_106',
'A7XX_PERF_GBIF_RESERVED_107', 'A7XX_PERF_GBIF_RESERVED_108',
'A7XX_PERF_GBIF_RESERVED_109', 'A7XX_PERF_GBIF_RESERVED_110',
'A7XX_PERF_GBIF_RESERVED_111', 'A7XX_PERF_GBIF_RESERVED_112',
'A7XX_PERF_GBIF_RESERVED_113', 'A7XX_PERF_GBIF_RESERVED_114',
'A7XX_PERF_GBIF_RESERVED_115', 'A7XX_PERF_GBIF_RESERVED_116',
'A7XX_PERF_GBIF_RESERVED_117', 'A7XX_PERF_GBIF_RESERVED_118',
'A7XX_PERF_GBIF_RESERVED_119', 'A7XX_PERF_GBIF_RESERVED_12',
'A7XX_PERF_GBIF_RESERVED_120', 'A7XX_PERF_GBIF_RESERVED_121',
'A7XX_PERF_GBIF_RESERVED_122', 'A7XX_PERF_GBIF_RESERVED_123',
'A7XX_PERF_GBIF_RESERVED_124', 'A7XX_PERF_GBIF_RESERVED_125',
'A7XX_PERF_GBIF_RESERVED_126', 'A7XX_PERF_GBIF_RESERVED_127',
'A7XX_PERF_GBIF_RESERVED_128', 'A7XX_PERF_GBIF_RESERVED_129',
'A7XX_PERF_GBIF_RESERVED_13', 'A7XX_PERF_GBIF_RESERVED_130',
'A7XX_PERF_GBIF_RESERVED_131', 'A7XX_PERF_GBIF_RESERVED_132',
'A7XX_PERF_GBIF_RESERVED_133', 'A7XX_PERF_GBIF_RESERVED_134',
'A7XX_PERF_GBIF_RESERVED_135', 'A7XX_PERF_GBIF_RESERVED_136',
'A7XX_PERF_GBIF_RESERVED_137', 'A7XX_PERF_GBIF_RESERVED_138',
'A7XX_PERF_GBIF_RESERVED_139', 'A7XX_PERF_GBIF_RESERVED_14',
'A7XX_PERF_GBIF_RESERVED_140', 'A7XX_PERF_GBIF_RESERVED_141',
'A7XX_PERF_GBIF_RESERVED_142', 'A7XX_PERF_GBIF_RESERVED_143',
'A7XX_PERF_GBIF_RESERVED_144', 'A7XX_PERF_GBIF_RESERVED_145',
'A7XX_PERF_GBIF_RESERVED_146', 'A7XX_PERF_GBIF_RESERVED_147',
'A7XX_PERF_GBIF_RESERVED_148', 'A7XX_PERF_GBIF_RESERVED_149',
'A7XX_PERF_GBIF_RESERVED_15', 'A7XX_PERF_GBIF_RESERVED_150',
'A7XX_PERF_GBIF_RESERVED_151', 'A7XX_PERF_GBIF_RESERVED_152',
'A7XX_PERF_GBIF_RESERVED_153', 'A7XX_PERF_GBIF_RESERVED_154',
'A7XX_PERF_GBIF_RESERVED_155', 'A7XX_PERF_GBIF_RESERVED_156',
'A7XX_PERF_GBIF_RESERVED_16', 'A7XX_PERF_GBIF_RESERVED_17',
'A7XX_PERF_GBIF_RESERVED_18', 'A7XX_PERF_GBIF_RESERVED_19',
'A7XX_PERF_GBIF_RESERVED_2', 'A7XX_PERF_GBIF_RESERVED_20',
'A7XX_PERF_GBIF_RESERVED_21', 'A7XX_PERF_GBIF_RESERVED_24',
'A7XX_PERF_GBIF_RESERVED_25', 'A7XX_PERF_GBIF_RESERVED_26',
'A7XX_PERF_GBIF_RESERVED_27', 'A7XX_PERF_GBIF_RESERVED_28',
'A7XX_PERF_GBIF_RESERVED_29', 'A7XX_PERF_GBIF_RESERVED_3',
'A7XX_PERF_GBIF_RESERVED_30', 'A7XX_PERF_GBIF_RESERVED_31',
'A7XX_PERF_GBIF_RESERVED_32', 'A7XX_PERF_GBIF_RESERVED_33',
'A7XX_PERF_GBIF_RESERVED_36', 'A7XX_PERF_GBIF_RESERVED_37',
'A7XX_PERF_GBIF_RESERVED_38', 'A7XX_PERF_GBIF_RESERVED_39',
'A7XX_PERF_GBIF_RESERVED_4', 'A7XX_PERF_GBIF_RESERVED_40',
'A7XX_PERF_GBIF_RESERVED_41', 'A7XX_PERF_GBIF_RESERVED_42',
'A7XX_PERF_GBIF_RESERVED_43', 'A7XX_PERF_GBIF_RESERVED_44',
'A7XX_PERF_GBIF_RESERVED_45', 'A7XX_PERF_GBIF_RESERVED_48',
'A7XX_PERF_GBIF_RESERVED_49', 'A7XX_PERF_GBIF_RESERVED_5',
'A7XX_PERF_GBIF_RESERVED_50', 'A7XX_PERF_GBIF_RESERVED_51',
'A7XX_PERF_GBIF_RESERVED_52', 'A7XX_PERF_GBIF_RESERVED_53',
'A7XX_PERF_GBIF_RESERVED_54', 'A7XX_PERF_GBIF_RESERVED_55',
'A7XX_PERF_GBIF_RESERVED_56', 'A7XX_PERF_GBIF_RESERVED_57',
'A7XX_PERF_GBIF_RESERVED_58', 'A7XX_PERF_GBIF_RESERVED_59',
'A7XX_PERF_GBIF_RESERVED_6', 'A7XX_PERF_GBIF_RESERVED_60',
'A7XX_PERF_GBIF_RESERVED_61', 'A7XX_PERF_GBIF_RESERVED_62',
'A7XX_PERF_GBIF_RESERVED_63', 'A7XX_PERF_GBIF_RESERVED_64',
'A7XX_PERF_GBIF_RESERVED_65', 'A7XX_PERF_GBIF_RESERVED_66',
'A7XX_PERF_GBIF_RESERVED_67', 'A7XX_PERF_GBIF_RESERVED_7',
'A7XX_PERF_GBIF_RESERVED_78', 'A7XX_PERF_GBIF_RESERVED_79',
'A7XX_PERF_GBIF_RESERVED_8', 'A7XX_PERF_GBIF_RESERVED_80',
'A7XX_PERF_GBIF_RESERVED_81', 'A7XX_PERF_GBIF_RESERVED_82',
'A7XX_PERF_GBIF_RESERVED_83', 'A7XX_PERF_GBIF_RESERVED_84',
'A7XX_PERF_GBIF_RESERVED_85', 'A7XX_PERF_GBIF_RESERVED_86',
'A7XX_PERF_GBIF_RESERVED_87', 'A7XX_PERF_GBIF_RESERVED_88',
'A7XX_PERF_GBIF_RESERVED_89', 'A7XX_PERF_GBIF_RESERVED_9',
'A7XX_PERF_GBIF_RESERVED_90', 'A7XX_PERF_GBIF_RESERVED_91',
'A7XX_PERF_GBIF_RESERVED_92', 'A7XX_PERF_GBIF_RESERVED_93',
'A7XX_PERF_GBIF_RESERVED_94', 'A7XX_PERF_GBIF_RESERVED_95',
'A7XX_PERF_GBIF_RESERVED_96', 'A7XX_PERF_GBIF_RESERVED_97',
'A7XX_PERF_GBIF_RESERVED_98', 'A7XX_PERF_GBIF_RESERVED_99',
'A7XX_PERF_GBIF_RSC0_REQUESTS_TOTAL',
'A7XX_PERF_GBIF_RSC1_REQUESTS_TOTAL',
'A7XX_PERF_GBIF_WRITE_BEAT_ALL_CHANNELS',
'A7XX_PERF_HLSQ_BUSY_CYCLES', 'A7XX_PERF_HLSQ_BV2LPAC_SWITCH_CNT',
'A7XX_PERF_HLSQ_BV2LPAC_SWITCH_CYC',
'A7XX_PERF_HLSQ_BV_CONST_BUF_FULL_BLOCK_CPI',
'A7XX_PERF_HLSQ_BV_CTXT_BUF_FULL_BLOCK_CPI',
'A7XX_PERF_HLSQ_BV_DATA_WAIT_PROGRAMMING',
'A7XX_PERF_HLSQ_BV_DEREF_CYCLES',
'A7XX_PERF_HLSQ_BV_DES_BUF_FULL_BLOCK_CPI',
'A7XX_PERF_HLSQ_BV_INS_BUF_FULL_BLOCK_CPI',
'A7XX_PERF_HLSQ_BV_S2W_CYCLES', 'A7XX_PERF_HLSQ_BV_S2W_CYCLES_SP',
'A7XX_PERF_HLSQ_BV_STALL_CYCLES', 'A7XX_PERF_HLSQ_BV_WAIT_FS_S2W',
'A7XX_PERF_HLSQ_COMPUTE_DRAWCALLS',
'A7XX_PERF_HLSQ_DUAL_FS_PROG_ACTIVE',
'A7XX_PERF_HLSQ_DUAL_VS_PROG_ACTIVE',
'A7XX_PERF_HLSQ_FS_BATCH_COUNT_ZERO',
'A7XX_PERF_HLSQ_FS_CONST_BUF_FULL_BLOCK_CPI',
'A7XX_PERF_HLSQ_FS_CTXT_BUF_FULL_BLOCK_CPI',
'A7XX_PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING',
'A7XX_PERF_HLSQ_FS_DEREF_CYCLES',
'A7XX_PERF_HLSQ_FS_DES_BUF_FULL_BLOCK_CPI',
'A7XX_PERF_HLSQ_FS_INS_BUF_FULL_BLOCK_CPI',
'A7XX_PERF_HLSQ_FS_S2W_CYCLES', 'A7XX_PERF_HLSQ_FS_S2W_CYCLES_SP',
'A7XX_PERF_HLSQ_FS_STALL_CYCLES', 'A7XX_PERF_HLSQ_FS_STARVING_SP',
'A7XX_PERF_HLSQ_FS_WAIT_SAME_VS_S2W',
'A7XX_PERF_HLSQ_FS_WAIT_VS_S2W',
'A7XX_PERF_HLSQ_L2STC_BANK0_REPLACEMENT',
'A7XX_PERF_HLSQ_L2STC_BANK1_REPLACEMENT',
'A7XX_PERF_HLSQ_L2STC_BANK2_REPLACEMENT',
'A7XX_PERF_HLSQ_L2STC_BANK3_REPLACEMENT',
'A7XX_PERF_HLSQ_L2STC_LATENCY_COUNT',
'A7XX_PERF_HLSQ_L2STC_LATENCY_CYCLES',
'A7XX_PERF_HLSQ_L2STC_REQ_HLSQ',
'A7XX_PERF_HLSQ_L2STC_REQ_HLSQ_HIT',
'A7XX_PERF_HLSQ_L2STC_REQ_INS_HLSQ',
'A7XX_PERF_HLSQ_L2STC_REQ_INS_HLSQ_HIT',
'A7XX_PERF_HLSQ_L2STC_REQ_INS_SP',
'A7XX_PERF_HLSQ_L2STC_REQ_INS_SP_HIT',
'A7XX_PERF_HLSQ_L2STC_REQ_SP', 'A7XX_PERF_HLSQ_L2STC_REQ_SP_HIT',
'A7XX_PERF_HLSQ_L2STC_REQ_UCHE',
'A7XX_PERF_HLSQ_L2STC_STALL_SP_MISS_REQ',
'A7XX_PERF_HLSQ_LPAC2BV_SWITCH_CNT',
'A7XX_PERF_HLSQ_LPAC2BV_SWITCH_CYC',
'A7XX_PERF_HLSQ_LPAC_DEREF_CYCLES',
'A7XX_PERF_HLSQ_LPAC_S2W_CYCLES',
'A7XX_PERF_HLSQ_LPAC_S2W_CYCLES_SP',
'A7XX_PERF_HLSQ_LPAC_STALL_CYCLES',
'A7XX_PERF_HLSQ_LPAC_WAIT_VS_S2W',
'A7XX_PERF_HLSQ_MISS_RETURN_STALL_BY_S2W',
'A7XX_PERF_HLSQ_NEVER_COUNT', 'A7XX_PERF_HLSQ_PRIMITIVE_COUNT',
'A7XX_PERF_HLSQ_RESERVED_19', 'A7XX_PERF_HLSQ_RESERVED_20',
'A7XX_PERF_HLSQ_RESERVED_37', 'A7XX_PERF_HLSQ_RESERVED_7',
'A7XX_PERF_HLSQ_RESERVED_8', 'A7XX_PERF_HLSQ_RESERVED_9',
'A7XX_PERF_HLSQ_S2W_STALL_BY_MISS_RETURN',
'A7XX_PERF_HLSQ_SPTROC_STCHE_MISS_INC_BV',
'A7XX_PERF_HLSQ_SPTROC_STCHE_MISS_INC_FS',
'A7XX_PERF_HLSQ_SPTROC_STCHE_MISS_INC_LPAC',
'A7XX_PERF_HLSQ_SPTROC_STCHE_MISS_INC_VS',
'A7XX_PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_BV',
'A7XX_PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_FS',
'A7XX_PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_LPAC',
'A7XX_PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_VS',
'A7XX_PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE',
'A7XX_PERF_HLSQ_STALL_CYCLES_SP_STATE',
'A7XX_PERF_HLSQ_STALL_CYCLES_UCHE',
'A7XX_PERF_HLSQ_STALL_CYCLES_VPC_BE',
'A7XX_PERF_HLSQ_STPROC_DPS_RUN_COUNT',
'A7XX_PERF_HLSQ_STPROC_DPS_RUN_CYCLE',
'A7XX_PERF_HLSQ_STPROC_L0_INS_HIT',
'A7XX_PERF_HLSQ_STPROC_L0_INS_LATENCY_COUNT',
'A7XX_PERF_HLSQ_STPROC_L0_INS_LATENCY_CYCLE',
'A7XX_PERF_HLSQ_STPROC_L0_INS_MISS',
'A7XX_PERF_HLSQ_STPROC_L0_STALL_INS_RD',
'A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXTS_BV',
'A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXTS_FS',
'A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXTS_LPAC',
'A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXTS_VS',
'A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_BV',
'A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_FS',
'A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_LPAC',
'A7XX_PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_VS',
'A7XX_PERF_HLSQ_UCHE_LATENCY_COUNT',
'A7XX_PERF_HLSQ_UCHE_LATENCY_CYCLES',
'A7XX_PERF_HLSQ_VSBR_DEREF_CYCLES',
'A7XX_PERF_HLSQ_VSBR_S2W_CYCLES',
'A7XX_PERF_HLSQ_VSBR_S2W_CYCLES_SP',
'A7XX_PERF_HLSQ_VSBR_STALL_CYCLES',
'A7XX_PERF_HLSQ_VSBR_WAIT_FS_S2W',
'A7XX_PERF_HLSQ_VSDP_BR_QUERY_BUSY',
'A7XX_PERF_HLSQ_VSDP_BR_QUERY_FAIL',
'A7XX_PERF_HLSQ_VSDP_BR_QUERY_REQ',
'A7XX_PERF_HLSQ_VSDP_BR_QUERY_REQ_WHEN_BV_PENDING',
'A7XX_PERF_HLSQ_VSDP_BV2BR_SWITCH_CYC',
'A7XX_PERF_HLSQ_VSDP_BV_QUERY_BUSY',
'A7XX_PERF_HLSQ_VSDP_BV_QUERY_FAIL',
'A7XX_PERF_HLSQ_VSDP_BV_QUERY_REQ',
'A7XX_PERF_HLSQ_VS_BATCH_COUNT_ZERO',
'A7XX_PERF_HLSQ_VS_CONST_BUF_FULL_BLOCK_CPI',
'A7XX_PERF_HLSQ_VS_CTXT_BUF_FULL_BLOCK_CPI',
'A7XX_PERF_HLSQ_VS_DATA_WAIT_PROGRAMMING',
'A7XX_PERF_HLSQ_VS_DES_BUF_FULL_BLOCK_CPI',
'A7XX_PERF_HLSQ_VS_INS_BUF_FULL_BLOCK_CPI',
'A7XX_PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE',
'A7XX_PERF_HLSQ_WAVE_PENDING_NO_QUAD',
'A7XX_PERF_LRZ_BUSY_CYCLES', 'A7XX_PERF_LRZ_FEEDBACK_ACCEPT',
'A7XX_PERF_LRZ_FEEDBACK_DISCARD', 'A7XX_PERF_LRZ_FEEDBACK_STALL',
'A7XX_PERF_LRZ_FULL_8X8_TILES', 'A7XX_PERF_LRZ_LRZ_READ',
'A7XX_PERF_LRZ_LRZ_WRITE', 'A7XX_PERF_LRZ_MERGE_CACHE_UPDATING',
'A7XX_PERF_LRZ_NEVER_COUNT', 'A7XX_PERF_LRZ_NUM_FLOCK',
'A7XX_PERF_LRZ_PARTIAL_8X8_TILES',
'A7XX_PERF_LRZ_PRIM_KILLED_BY_LRZ',
'A7XX_PERF_LRZ_PRIM_KILLED_BY_MASKGEN',
'A7XX_PERF_LRZ_RAS_MASK_TRANS', 'A7XX_PERF_LRZ_READ_LATENCY',
'A7XX_PERF_LRZ_STALL_CYCLES_FLAG_ACR',
'A7XX_PERF_LRZ_STALL_CYCLES_HLSQ_BATCH',
'A7XX_PERF_LRZ_STALL_CYCLES_MVC', 'A7XX_PERF_LRZ_STALL_CYCLES_RB',
'A7XX_PERF_LRZ_STALL_CYCLES_RB_BPLANE',
'A7XX_PERF_LRZ_STALL_CYCLES_RB_ZPLANE',
'A7XX_PERF_LRZ_STALL_CYCLES_UCHE',
'A7XX_PERF_LRZ_STALL_CYCLES_VPC_BE',
'A7XX_PERF_LRZ_STALL_CYCLES_VSC',
'A7XX_PERF_LRZ_STARVE_CYCLES_RAS', 'A7XX_PERF_LRZ_TILE_KILLED',
'A7XX_PERF_LRZ_TILE_KILLED_BY_IMAGE_VRS',
'A7XX_PERF_LRZ_TILE_KILLED_BY_Z', 'A7XX_PERF_LRZ_TOTAL_PIXEL',
'A7XX_PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ',
'A7XX_PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ',
'A7XX_PERF_PC_NEVER_COUNT', 'A7XX_PERF_PC_RESERVED_51',
'A7XX_PERF_PC_RESERVED_52', 'A7XX_PERF_PC_RESERVED_53',
'A7XX_PERF_PC_RESERVED_54', 'A7XX_PERF_PC_RESERVED_55',
'A7XX_PERF_PC_RESERVED_56', 'A7XX_PERF_PC_RESERVED_57',
'A7XX_PERF_PC_RESERVED_58', 'A7XX_PERF_PC_RESERVED_59',
'A7XX_PERF_PC_S_BUSY_CYCLES', 'A7XX_PERF_PC_S_DS_INVOCATIONS',
'A7XX_PERF_PC_S_DS_PRIMITIVES', 'A7XX_PERF_PC_S_GS_INVOCATIONS',
'A7XX_PERF_PC_S_HS_INVOCATIONS', 'A7XX_PERF_PC_S_IA_PRIMITIVES',
'A7XX_PERF_PC_S_IA_VERTICES', 'A7XX_PERF_PC_S_MESH_VS_WAVES',
'A7XX_PERF_PC_S_STALL_CYCLES_TESS',
'A7XX_PERF_PC_S_STALL_CYCLES_VFD',
'A7XX_PERF_PC_S_STALL_CYCLES_VFD_ONLY',
'A7XX_PERF_PC_S_STALL_CYCLES_VPC_FE',
'A7XX_PERF_PC_S_STALL_CYCLES_VPC_ONLY',
'A7XX_PERF_PC_S_TESS_BUSY_CYCLES',
'A7XX_PERF_PC_S_TESS_FACTOR_TRANS',
'A7XX_PERF_PC_S_TESS_PC_UV_PATCHES',
'A7XX_PERF_PC_S_TESS_PC_UV_TRANS',
'A7XX_PERF_PC_S_TESS_PID_ACTIVE',
'A7XX_PERF_PC_S_TESS_PRIM_GEN_ACTIVE',
'A7XX_PERF_PC_S_TESS_SETUP_ACTIVE',
'A7XX_PERF_PC_S_TESS_STALL_CYCLES_PC',
'A7XX_PERF_PC_S_TESS_STARVE_CYCLES_PC',
'A7XX_PERF_PC_S_TESS_WORKING_CYCLES',
'A7XX_PERF_PC_S_VERTEX_HITS', 'A7XX_PERF_PC_S_VPC_PRIMITIVES',
'A7XX_PERF_PC_S_VS_INVOCATIONS', 'A7XX_PERF_PC_S_WORKING_CYCLES',
'A7XX_PERF_PC_US_2D_DRAWCALLS', 'A7XX_PERF_PC_US_3D_DRAWCALLS',
'A7XX_PERF_PC_US_BR2BV_SWITCH',
'A7XX_PERF_PC_US_BR_STALLS_BV_WORKLOAD',
'A7XX_PERF_PC_US_BUSY_CYCLES', 'A7XX_PERF_PC_US_BV2BR_SWITCH',
'A7XX_PERF_PC_US_BV_STALLED_BY_ATTR',
'A7XX_PERF_PC_US_BV_STALLED_BY_UCHE_FEEDBACK',
'A7XX_PERF_PC_US_BV_STALLS_BR_WORKLOAD',
'A7XX_PERF_PC_US_BV_STARVED_BY_RARB', 'A7XX_PERF_PC_US_DEAD_PRIM',
'A7XX_PERF_PC_US_DP0_INPUT_STALLS',
'A7XX_PERF_PC_US_DP0_LIVE_PRIM', 'A7XX_PERF_PC_US_DP0_RARB_FULL',
'A7XX_PERF_PC_US_DP1_INPUT_STALLS',
'A7XX_PERF_PC_US_DP1_LIVE_PRIM', 'A7XX_PERF_PC_US_DP1_RARB_FULL',
'A7XX_PERF_PC_US_INSTANCES', 'A7XX_PERF_PC_US_MESH_DEAD_DRAWS',
'A7XX_PERF_PC_US_MESH_DEAD_PRIM', 'A7XX_PERF_PC_US_MESH_DRAWS',
'A7XX_PERF_PC_US_MESH_LIVE_PRIM',
'A7XX_PERF_PC_US_MESH_MVIS_EN_DRAWS',
'A7XX_PERF_PC_US_MESH_PA_EN_PRIM',
'A7XX_PERF_PC_US_NON_DRAWCALL_GLOBAL_EVENTS',
'A7XX_PERF_PC_US_PASS1_TF_STALL_CYCLES',
'A7XX_PERF_PC_US_PASSPAIR_STALL',
'A7XX_PERF_PC_US_PREDRAW_STALLS',
'A7XX_PERF_PC_US_SLICE_LIVE_PRIM',
'A7XX_PERF_PC_US_STALL_CYCLES_COMPUTE_GFX',
'A7XX_PERF_PC_US_STALL_CYCLES_GFX_COMPUTE',
'A7XX_PERF_PC_US_STALL_CYCLES_PC_S',
'A7XX_PERF_PC_US_STALL_CYCLES_UCHE0',
'A7XX_PERF_PC_US_STALL_CYCLES_UCHE1',
'A7XX_PERF_PC_US_STARVE_CYCLES_DI',
'A7XX_PERF_PC_US_STARVE_CYCLES_FOR_INDEX',
'A7XX_PERF_PC_US_STARVE_CYCLES_FOR_MVIS_STREAM',
'A7XX_PERF_PC_US_STARVE_CYCLES_FOR_TF',
'A7XX_PERF_PC_US_STARVE_CYCLES_FOR_VIZ_STREAM',
'A7XX_PERF_PC_US_STARVE_CYCLES_PREDRAW',
'A7XX_PERF_PC_US_UCHE_0_TRANS', 'A7XX_PERF_PC_US_UCHE_1_TRANS',
'A7XX_PERF_PC_US_UCHE_OUTSTANDING_TRANS',
'A7XX_PERF_PC_US_VIS_STREAMS_LOADED',
'A7XX_PERF_PC_US_VPC_PRIM_COUNT_STALLS_BR',
'A7XX_PERF_PC_US_VPC_PRIM_COUNT_STALLS_BV',
'A7XX_PERF_PC_US_VSD_RARB_DVIZ_FULL',
'A7XX_PERF_PC_US_VSD_RARB_PVIZ_FULL',
'A7XX_PERF_PC_US_VSD_RARB_TVIZ_FULL',
'A7XX_PERF_PC_US_WORKING_CYCLES', 'A7XX_PERF_RAS_8X4_TILES',
'A7XX_PERF_RAS_BLOCKS', 'A7XX_PERF_RAS_BUSY_CYCLES',
'A7XX_PERF_RAS_FALSE_PARTIAL_STILE',
'A7XX_PERF_RAS_FULLY_COVERED_8X4_TILES',
'A7XX_PERF_RAS_FULLY_COVERED_SUPER_TILES',
'A7XX_PERF_RAS_LRZ_INTF_WORKING_CYCLES',
'A7XX_PERF_RAS_MASKGEN_ACTIVE', 'A7XX_PERF_RAS_NEVER_COUNT',
'A7XX_PERF_RAS_PRIM_KILLED_INVISILBE',
'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_0_WORKING_CC_L2',
'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_10_WORKING_CC_L2',
'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_11_WORKING_CC_L2',
'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_12_WORKING_CC_L2',
'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_13_WORKING_CC_L2',
'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_14_WORKING_CC_L2',
'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_15_WORKING_CC_L2',
'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_1_WORKING_CC_L2',
'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_2_WORKING_CC_L2',
'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_3_WORKING_CC_L2',
'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_4_WORKING_CC_L2',
'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_5_WORKING_CC_L2',
'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_6_WORKING_CC_L2',
'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_7_WORKING_CC_L2',
'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_8_WORKING_CC_L2',
'A7XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_9_WORKING_CC_L2',
'A7XX_PERF_RAS_SLICE_BLOCK_EMPTY',
'A7XX_PERF_RAS_SLICE_BLOCK_NONEMTPY',
'A7XX_PERF_RAS_STALL_CYCLES_LRZ',
'A7XX_PERF_RAS_STARVE_CYCLES_TSE',
'A7XX_PERF_RAS_SUPERTILE_ACTIVE_CYCLES',
'A7XX_PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES',
'A7XX_PERF_RAS_SUPER_TILES', 'A7XX_PERF_RBBM_NEVER_COUNT',
'A7XX_PERF_RBBM_S_HLSQ_BUSY', 'A7XX_PERF_RBBM_S_PC_BUSY',
'A7XX_PERF_RBBM_S_RAS_BUSY', 'A7XX_PERF_RBBM_S_TESS_BUSY',
'A7XX_PERF_RBBM_S_TSEBE_BUSY', 'A7XX_PERF_RBBM_S_TSEFE_BUSY',
'A7XX_PERF_RBBM_US_ALWAYS_COUNT', 'A7XX_PERF_RBBM_US_ALWAYS_ON',
'A7XX_PERF_RBBM_US_COM_BUSY', 'A7XX_PERF_RBBM_US_DCOM_BUSY',
'A7XX_PERF_RBBM_US_HLSQ_BUSY', 'A7XX_PERF_RBBM_US_PC_BUSY',
'A7XX_PERF_RBBM_US_STATUS_MASKED', 'A7XX_PERF_RBBM_US_UCHE_BUSY',
'A7XX_PERF_RBBM_US_VBIF_BUSY', 'A7XX_PERF_RBBM_US_VSC_BUSY',
'A7XX_PERF_RB_2D_ALIVE_CYCLES',
'A7XX_PERF_RB_2D_STARVE_CYCLES_SP',
'A7XX_PERF_RB_2D_VALID_PIXELS', 'A7XX_PERF_RB_3D_PIXELS',
'A7XX_PERF_RB_BLENDED_FP16_COMPONENTS',
'A7XX_PERF_RB_BLENDED_FP32_COMPONENTS',
'A7XX_PERF_RB_BLENDED_FXP_COMPONENTS',
'A7XX_PERF_RB_BLENDER_WORKING_CYCLES', 'A7XX_PERF_RB_BUSY_CYCLES',
'A7XX_PERF_RB_COLOR_PIX_TILES',
'A7XX_PERF_RB_CPROC_WORKING_CYCLES', 'A7XX_PERF_RB_C_READ',
'A7XX_PERF_RB_C_WRITE', 'A7XX_PERF_RB_EARLY_Z_ARB3_GRANT',
'A7XX_PERF_RB_EARLY_Z_SKIP_GRANT', 'A7XX_PERF_RB_HLSQ_ACTIVE',
'A7XX_PERF_RB_LATE_Z_ARB3_GRANT', 'A7XX_PERF_RB_NEVER_COUNT',
'A7XX_PERF_RB_PS_INVOCATIONS',
'A7XX_PERF_RB_SAMPLER_WORKING_CYCLES',
'A7XX_PERF_RB_STALL_CYCLES_CCU',
'A7XX_PERF_RB_STALL_CYCLES_CCU_COLOR_READ',
'A7XX_PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE',
'A7XX_PERF_RB_STALL_CYCLES_CCU_DEPTH_READ',
'A7XX_PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE',
'A7XX_PERF_RB_STALL_CYCLES_FIFO0_FULL',
'A7XX_PERF_RB_STALL_CYCLES_FIFO1_FULL',
'A7XX_PERF_RB_STALL_CYCLES_FIFO2_FULL',
'A7XX_PERF_RB_STALL_CYCLES_HLSQ',
'A7XX_PERF_RB_STALL_CYCLES_VPC_BE',
'A7XX_PERF_RB_STARVE_CYCLES_BARY_PLANE',
'A7XX_PERF_RB_STARVE_CYCLES_CCU',
'A7XX_PERF_RB_STARVE_CYCLES_LRZ_TILE',
'A7XX_PERF_RB_STARVE_CYCLES_SP',
'A7XX_PERF_RB_STARVE_CYCLES_Z_PLANE', 'A7XX_PERF_RB_S_FAIL',
'A7XX_PERF_RB_TOTAL_PASS', 'A7XX_PERF_RB_VRS_1X1_QUADS',
'A7XX_PERF_RB_VRS_1X2_QUADS', 'A7XX_PERF_RB_VRS_2X1_QUADS',
'A7XX_PERF_RB_VRS_2X2_QUADS', 'A7XX_PERF_RB_VRS_2X4_QUADS',
'A7XX_PERF_RB_VRS_4X2_QUADS', 'A7XX_PERF_RB_VRS_4X4_QUADS',
'A7XX_PERF_RB_ZPROC_WORKING_CYCLES', 'A7XX_PERF_RB_Z_FAIL',
'A7XX_PERF_RB_Z_PASS', 'A7XX_PERF_RB_Z_READ',
'A7XX_PERF_RB_Z_WORKLOAD', 'A7XX_PERF_RB_Z_WRITE',
'A7XX_PERF_SP_ADDR_LOCK_COUNT',
'A7XX_PERF_SP_ALU_DATA_FORWARDING_CYCLES',
'A7XX_PERF_SP_ALU_GPR_READ_CYCLES',
'A7XX_PERF_SP_ALU_WORKING_CYCLES', 'A7XX_PERF_SP_ANY_EU_WORKING',
'A7XX_PERF_SP_ANY_EU_WORKING_CS_STAGE',
'A7XX_PERF_SP_ANY_EU_WORKING_FS_STAGE',
'A7XX_PERF_SP_ANY_EU_WORKING_LPAC',
'A7XX_PERF_SP_ANY_EU_WORKING_VS_STAGE',
'A7XX_PERF_SP_BARY_FP32_INSTRUCTIONS',
'A7XX_PERF_SP_BRANCH_INS_COUNT',
'A7XX_PERF_SP_BRANCH_INS_DIVERGENCY_COUNT',
'A7XX_PERF_SP_BRANCH_NOT_TAKEN', 'A7XX_PERF_SP_BRANCH_TAKEN',
'A7XX_PERF_SP_BUSY_CYCLES', 'A7XX_PERF_SP_BYPASS_BUSY_CYCLES',
'A7XX_PERF_SP_CCHE_NONUAV_TOTAL_DUALQUAD',
'A7XX_PERF_SP_CCHE_NONUAV_TOTAL_REQ',
'A7XX_PERF_SP_CCHE_UAV_TOTAL_DUALQUAD',
'A7XX_PERF_SP_CCHE_UAV_TOTAL_REQ', 'A7XX_PERF_SP_CS_INSTRUCTIONS',
'A7XX_PERF_SP_CS_INVOCATIONS',
'A7XX_PERF_SP_DISPATCHER_WORKING_CYCLES',
'A7XX_PERF_SP_DS_INSTRUCTIONS', 'A7XX_PERF_SP_EFU_WORKING_CYCLES',
'A7XX_PERF_SP_EWAVE_CONTEXTS',
'A7XX_PERF_SP_EWAVE_CONTEXT_CYCLES',
'A7XX_PERF_SP_EXECUTABLE_WAVES', 'A7XX_PERF_SP_EXPORT_RB_TRANS',
'A7XX_PERF_SP_EXPORT_VPC_TRANS',
'A7XX_PERF_SP_FLOW_CONTROL_WORKING_CYCLES',
'A7XX_PERF_SP_FS_INSTRUCTIONS', 'A7XX_PERF_SP_FS_OOO_WAVE_ACC',
'A7XX_PERF_SP_FS_STAGE_1X_WAVES',
'A7XX_PERF_SP_FS_STAGE_2X_WAVES',
'A7XX_PERF_SP_FS_STAGE_BARY_INSTRUCTIONS',
'A7XX_PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS',
'A7XX_PERF_SP_FS_STAGE_DURATION_CYCLES',
'A7XX_PERF_SP_FS_STAGE_EFU_INSTRUCTIONS',
'A7XX_PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS',
'A7XX_PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS',
'A7XX_PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS',
'A7XX_PERF_SP_FS_STAGE_PI_TEX_INSTRUCTION',
'A7XX_PERF_SP_FS_STAGE_TEX_INSTRUCTIONS',
'A7XX_PERF_SP_FS_STAGE_WAVE_CYCLES',
'A7XX_PERF_SP_FS_STAGE_WAVE_SAMPLES',
'A7XX_PERF_SP_FS_WAVE_REQ_PENDING',
'A7XX_PERF_SP_FULL_ALU_ADD_INSTRUCTIONS',
'A7XX_PERF_SP_FULL_ALU_MAD_INSTRUCTIONS',
'A7XX_PERF_SP_FULL_ALU_MUL_INSTRUCTIONS',
'A7XX_PERF_SP_GM_ATOMICS', 'A7XX_PERF_SP_GM_LOAD_INSTRUCTIONS',
'A7XX_PERF_SP_GM_LOAD_LATENCY_CYCLES',
'A7XX_PERF_SP_GM_LOAD_LATENCY_SAMPLES',
'A7XX_PERF_SP_GM_STORE_INSTRUCTIONS', 'A7XX_PERF_SP_GPR_READ',
'A7XX_PERF_SP_GPR_READ_BANK', 'A7XX_PERF_SP_GPR_READ_CONFLICT',
'A7XX_PERF_SP_GPR_READ_PREFETCH', 'A7XX_PERF_SP_GPR_WRITE',
'A7XX_PERF_SP_GPR_WRITE_BANK', 'A7XX_PERF_SP_GPR_WRITE_CONFLICT',
'A7XX_PERF_SP_GS_INSTRUCTIONS',
'A7XX_PERF_SP_HALF_ALU_ADD_INSTRUCTIONS',
'A7XX_PERF_SP_HALF_ALU_MAD_INSTRUCTIONS',
'A7XX_PERF_SP_HALF_ALU_MUL_INSTRUCTIONS',
'A7XX_PERF_SP_HS_INSTRUCTIONS', 'A7XX_PERF_SP_ICL1_MISSES',
'A7XX_PERF_SP_ICL1_MISS_FETCH_CYCLES',
'A7XX_PERF_SP_ICL1_REQUESTS', 'A7XX_PERF_SP_LB_ALU_READ_CONS',
'A7XX_PERF_SP_LB_LDST_RW_LM',
'A7XX_PERF_SP_LB_LDST_RW_LM_BLOCKED',
'A7XX_PERF_SP_LB_LDST_WRITE_CONS',
'A7XX_PERF_SP_LB_LDST_WRITE_CONS_BLOCKED',
'A7XX_PERF_SP_LB_NONUAV_TOTAL_DUALQUAD',
'A7XX_PERF_SP_LB_NONUAV_TOTAL_REQ',
'A7XX_PERF_SP_LB_READ_ALU_BLOCK_OTHER',
'A7XX_PERF_SP_LB_READ_XFER_ALU',
'A7XX_PERF_SP_LB_WRITE_VPC_BLOCK_OTHER',
'A7XX_PERF_SP_LB_WRITE_XFER_VPC', 'A7XX_PERF_SP_LM_ATOMICS',
'A7XX_PERF_SP_LM_BANK_CONFLICTS', 'A7XX_PERF_SP_LM_FULL_CYCLES',
'A7XX_PERF_SP_LM_LOAD_INSTRUCTIONS',
'A7XX_PERF_SP_LM_STORE_INSTRUCTIONS',
'A7XX_PERF_SP_LM_WORKING_CYCLES',
'A7XX_PERF_SP_LOAD_CONTROL_WORKING_CYCLES',
'A7XX_PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP',
'A7XX_PERF_SP_LPAC_BUSY_CYCLES', 'A7XX_PERF_SP_LPAC_DRAWCALLS',
'A7XX_PERF_SP_LPAC_INSTRUCTIONS',
'A7XX_PERF_SP_LPAC_WAVE_REQ_PENDING', 'A7XX_PERF_SP_NEVER_COUNT',
'A7XX_PERF_SP_NON_EXECUTION_CYCLES',
'A7XX_PERF_SP_NON_EXECUTION_LS_CYCLES',
'A7XX_PERF_SP_OUTPUT_3D_PIXELS',
'A7XX_PERF_SP_PGPR_ALLOC_CONTEXTS', 'A7XX_PERF_SP_PIXELS',
'A7XX_PERF_SP_PIXELS_KILLED', 'A7XX_PERF_SP_PI_WORKING_CYCLES',
'A7XX_PERF_SP_PREDICT_INS_COUNT',
'A7XX_PERF_SP_PREDICT_INS_DIVERGENCY_COUNT',
'A7XX_PERF_SP_PREDICT_NOT_TAKEN', 'A7XX_PERF_SP_PREDICT_TAKEN',
'A7XX_PERF_SP_QUADS', 'A7XX_PERF_SP_RAY_QUERY_INSTRUCTIONS',
'A7XX_PERF_SP_RBRT_KICKOFF_DQUADS',
'A7XX_PERF_SP_RBRT_KICKOFF_FIBERS', 'A7XX_PERF_SP_RESERVED_86',
'A7XX_PERF_SP_RTU_BUSY_CYCLES',
'A7XX_PERF_SP_RTU_BVH_FETCH_LATENCY_CYCLES',
'A7XX_PERF_SP_RTU_BVH_FETCH_LATENCY_SAMPLES',
'A7XX_PERF_SP_RTU_L0_HITS', 'A7XX_PERF_SP_RTU_L0_HIT_ON_MISS',
'A7XX_PERF_SP_RTU_L0_MISSES',
'A7XX_PERF_SP_RTU_OPERAND_FETCH_STALL_CYCLES_INS_FIFO',
'A7XX_PERF_SP_RTU_OPERAND_FETCH_STALL_CYCLES_L0',
'A7XX_PERF_SP_RTU_RAY_BOX_INTERSECTIONS',
'A7XX_PERF_SP_RTU_RAY_TRIANGLE_INTERSECTIONS',
'A7XX_PERF_SP_RTU_STALL_CYCLES_L0DATA',
'A7XX_PERF_SP_RTU_STALL_CYCLES_L0D_IDX_QUEUE',
'A7XX_PERF_SP_RTU_STALL_CYCLES_L0_HIT_QUEUE',
'A7XX_PERF_SP_RTU_STALL_CYCLES_L0_MISS_QUEUE',
'A7XX_PERF_SP_RTU_STALL_CYCLES_MRG_CNT',
'A7XX_PERF_SP_RTU_STALL_CYCLES_REPLACE_CNT',
'A7XX_PERF_SP_RTU_STALL_CYCLES_UCHE',
'A7XX_PERF_SP_RTU_STALL_CYCLES_WAVE_QUEUE',
'A7XX_PERF_SP_SCH_STALL_CYCLES_RTU',
'A7XX_PERF_SP_SEQUENCER_WORKING_CYCLES',
'A7XX_PERF_SP_STALL_CYCLES_RB', 'A7XX_PERF_SP_STALL_CYCLES_TP',
'A7XX_PERF_SP_STALL_CYCLES_UCHE',
'A7XX_PERF_SP_STALL_CYCLES_VPC_BE',
'A7XX_PERF_SP_STARVE_CYCLES_HLSQ',
'A7XX_PERF_SP_STCHE_MISS_INC_BV',
'A7XX_PERF_SP_STCHE_MISS_INC_FS',
'A7XX_PERF_SP_STCHE_MISS_INC_LPAC',
'A7XX_PERF_SP_STCHE_MISS_INC_VS',
'A7XX_PERF_SP_TEXTURE_FETCH_LATENCY_CYCLES',
'A7XX_PERF_SP_TEXTURE_FETCH_LATENCY_SAMPLES',
'A7XX_PERF_SP_TEX_CONTROL_WORKING_CYCLES',
'A7XX_PERF_SP_UCHE_READ_TRANS', 'A7XX_PERF_SP_UCHE_WRITE_TRANS',
'A7XX_PERF_SP_VGPR_ACTIVE_CONTEXTS',
'A7XX_PERF_SP_VGPR_ALLOC_CONTEXTS',
'A7XX_PERF_SP_VS_INSTRUCTIONS',
'A7XX_PERF_SP_VS_STAGE_DURATION_CYCLES',
'A7XX_PERF_SP_VS_STAGE_EFU_INSTRUCTIONS',
'A7XX_PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS',
'A7XX_PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS',
'A7XX_PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS',
'A7XX_PERF_SP_VS_STAGE_TEX_INSTRUCTIONS',
'A7XX_PERF_SP_VS_STAGE_WAVE_CYCLES',
'A7XX_PERF_SP_VS_STAGE_WAVE_SAMPLES',
'A7XX_PERF_SP_VS_WAVE_REQ_PENDING',
'A7XX_PERF_SP_WAVE_ALU_CYCLES', 'A7XX_PERF_SP_WAVE_CONTEXTS',
'A7XX_PERF_SP_WAVE_CONTEXT_CYCLES',
'A7XX_PERF_SP_WAVE_CSP_CYCLES', 'A7XX_PERF_SP_WAVE_CTRL_CYCLES',
'A7XX_PERF_SP_WAVE_EFU_CYCLES', 'A7XX_PERF_SP_WAVE_EMIT_CYCLES',
'A7XX_PERF_SP_WAVE_END_CYCLES', 'A7XX_PERF_SP_WAVE_FETCH_CYCLES',
'A7XX_PERF_SP_WAVE_HWAVE_SYNC',
'A7XX_PERF_SP_WAVE_HWAVE_WAIT_CYCLES',
'A7XX_PERF_SP_WAVE_IDLE_CYCLES', 'A7XX_PERF_SP_WAVE_INPUT_CYCLES',
'A7XX_PERF_SP_WAVE_INT_CYCLES', 'A7XX_PERF_SP_WAVE_JOIN_CYCLES',
'A7XX_PERF_SP_WAVE_LOAD_CYCLES',
'A7XX_PERF_SP_WAVE_LONG_SYNC_CYCLES',
'A7XX_PERF_SP_WAVE_NOP_CYCLES', 'A7XX_PERF_SP_WAVE_OUTPUT_CYCLES',
'A7XX_PERF_SP_WAVE_SHORT_SYNC_CYCLES',
'A7XX_PERF_SP_WAVE_SPLIT_CNT', 'A7XX_PERF_SP_WAVE_WAIT_CYCLES',
'A7XX_PERF_SP_WORKING_EU', 'A7XX_PERF_SP_WORKING_EU_CS_STAGE',
'A7XX_PERF_SP_WORKING_EU_FS_STAGE',
'A7XX_PERF_SP_WORKING_EU_VS_STAGE',
'A7XX_PERF_TP_2D_FILTER_WORKLOAD_16BIT',
'A7XX_PERF_TP_2D_FILTER_WORKLOAD_32BIT',
'A7XX_PERF_TP_2D_OUTPUT_PIXELS',
'A7XX_PERF_TP_2D_OUTPUT_PIXELS_BILINEAR',
'A7XX_PERF_TP_2D_OUTPUT_PIXELS_POINT',
'A7XX_PERF_TP_BACKEND_WORKING_CYCLES', 'A7XX_PERF_TP_BUSY_CYCLES',
'A7XX_PERF_TP_DIVERGENT_QUADS_RECEIVED',
'A7XX_PERF_TP_FILTER_POINT_FP16',
'A7XX_PERF_TP_FILTER_POINT_FP32',
'A7XX_PERF_TP_FILTER_WORKLOAD_16BIT',
'A7XX_PERF_TP_FILTER_WORKLOAD_32BIT',
'A7XX_PERF_TP_FLAG_CACHE_MISSES',
'A7XX_PERF_TP_FLAG_CACHE_REQUESTS',
'A7XX_PERF_TP_FLAG_FIFO_DELAY_CYCLES',
'A7XX_PERF_TP_FLAG_FIFO_DELAY_SAMPLES',
'A7XX_PERF_TP_FORMAT_DECOMP_BILINEAR',
'A7XX_PERF_TP_FORMAT_DECOMP_POINT',
'A7XX_PERF_TP_FRONTEND_WORKING_CYCLES',
'A7XX_PERF_TP_L1_5_CACHE_WORKING_CYCLES',
'A7XX_PERF_TP_L1_5_COMPRESS_REQS',
'A7XX_PERF_TP_L1_5_L2_COMPRESS_MISS',
'A7XX_PERF_TP_L1_5_L2_REQUESTS',
'A7XX_PERF_TP_L1_5_MISS_LATENCY_CYCLES',
'A7XX_PERF_TP_L1_5_MISS_LATENCY_TRANS',
'A7XX_PERF_TP_L1_BANK_CONFLICT',
'A7XX_PERF_TP_L1_CACHELINE_MISSES',
'A7XX_PERF_TP_L1_CACHELINE_REQUESTS',
'A7XX_PERF_TP_L1_DATA_WRITE_WORKING_CYCLES',
'A7XX_PERF_TP_L1_MISSES_ASTC_1TILE',
'A7XX_PERF_TP_L1_MISSES_ASTC_2TILE',
'A7XX_PERF_TP_L1_MISSES_ASTC_4TILE',
'A7XX_PERF_TP_L1_TAG_WORKING_CYCLES',
'A7XX_PERF_TP_LATENCY_CYCLES', 'A7XX_PERF_TP_LATENCY_FIFO_FULL',
'A7XX_PERF_TP_LATENCY_TRANS', 'A7XX_PERF_TP_NEVER_COUNT',
'A7XX_PERF_TP_OUTPUT_PIXELS', 'A7XX_PERF_TP_OUTPUT_PIXELS_ANISO',
'A7XX_PERF_TP_OUTPUT_PIXELS_BILINEAR',
'A7XX_PERF_TP_OUTPUT_PIXELS_MIP',
'A7XX_PERF_TP_OUTPUT_PIXELS_POINT',
'A7XX_PERF_TP_OUTPUT_PIXELS_ZERO_LOD',
'A7XX_PERF_TP_PACKED_POINT_BOTH_VALID_FP16',
'A7XX_PERF_TP_PACKED_POINT_BOTH_VALID_FP32',
'A7XX_PERF_TP_PACKED_POINT_SINGLE_VALID_FP16',
'A7XX_PERF_TP_PACKED_POINT_SINGLE_VALID_FP32',
'A7XX_PERF_TP_PRE_L1_DECOM_WORKING_CYCLES',
'A7XX_PERF_TP_PRT_NON_RESIDENT_EVENTS', 'A7XX_PERF_TP_QUADS_1D',
'A7XX_PERF_TP_QUADS_2D', 'A7XX_PERF_TP_QUADS_3D',
'A7XX_PERF_TP_QUADS_ARRAY', 'A7XX_PERF_TP_QUADS_BUFFER',
'A7XX_PERF_TP_QUADS_CONSTANT_MULTIPLIED',
'A7XX_PERF_TP_QUADS_CUBE', 'A7XX_PERF_TP_QUADS_GRADIENT',
'A7XX_PERF_TP_QUADS_OFFSET', 'A7XX_PERF_TP_QUADS_RECEIVED',
'A7XX_PERF_TP_QUADS_SHADOW', 'A7XX_PERF_TP_RESERVED_100',
'A7XX_PERF_TP_RESERVED_101', 'A7XX_PERF_TP_RESERVED_102',
'A7XX_PERF_TP_RESERVED_103', 'A7XX_PERF_TP_RESERVED_104',
'A7XX_PERF_TP_RESERVED_105', 'A7XX_PERF_TP_RESERVED_106',
'A7XX_PERF_TP_RESERVED_107', 'A7XX_PERF_TP_RESERVED_108',
'A7XX_PERF_TP_RESERVED_109', 'A7XX_PERF_TP_RESERVED_110',
'A7XX_PERF_TP_RESERVED_111', 'A7XX_PERF_TP_RESERVED_112',
'A7XX_PERF_TP_RESERVED_113', 'A7XX_PERF_TP_RESERVED_114',
'A7XX_PERF_TP_RESERVED_115', 'A7XX_PERF_TP_RESERVED_116',
'A7XX_PERF_TP_RESERVED_117', 'A7XX_PERF_TP_RESERVED_118',
'A7XX_PERF_TP_RESERVED_119', 'A7XX_PERF_TP_RESERVED_120',
'A7XX_PERF_TP_RESERVED_121', 'A7XX_PERF_TP_RESERVED_122',
'A7XX_PERF_TP_RESERVED_123', 'A7XX_PERF_TP_RESERVED_124',
'A7XX_PERF_TP_RESERVED_125', 'A7XX_PERF_TP_RESERVED_126',
'A7XX_PERF_TP_RESERVED_127', 'A7XX_PERF_TP_RESERVED_62',
'A7XX_PERF_TP_RESERVED_63', 'A7XX_PERF_TP_RESERVED_64',
'A7XX_PERF_TP_RESERVED_65', 'A7XX_PERF_TP_RESERVED_66',
'A7XX_PERF_TP_RESERVED_67', 'A7XX_PERF_TP_RESERVED_68',
'A7XX_PERF_TP_RESERVED_69', 'A7XX_PERF_TP_RESERVED_70',
'A7XX_PERF_TP_RESERVED_71', 'A7XX_PERF_TP_RESERVED_72',
'A7XX_PERF_TP_RESERVED_73', 'A7XX_PERF_TP_RESERVED_74',
'A7XX_PERF_TP_RESERVED_75', 'A7XX_PERF_TP_RESERVED_76',
'A7XX_PERF_TP_RESERVED_77', 'A7XX_PERF_TP_RESERVED_78',
'A7XX_PERF_TP_RESERVED_79', 'A7XX_PERF_TP_RESERVED_80',
'A7XX_PERF_TP_RESERVED_81', 'A7XX_PERF_TP_RESERVED_82',
'A7XX_PERF_TP_RESERVED_83', 'A7XX_PERF_TP_RESERVED_84',
'A7XX_PERF_TP_RESERVED_85', 'A7XX_PERF_TP_RESERVED_86',
'A7XX_PERF_TP_RESERVED_87', 'A7XX_PERF_TP_RESERVED_88',
'A7XX_PERF_TP_RESERVED_89', 'A7XX_PERF_TP_RESERVED_90',
'A7XX_PERF_TP_RESERVED_91', 'A7XX_PERF_TP_RESERVED_92',
'A7XX_PERF_TP_RESERVED_93', 'A7XX_PERF_TP_RESERVED_94',
'A7XX_PERF_TP_RESERVED_95', 'A7XX_PERF_TP_RESERVED_96',
'A7XX_PERF_TP_RESERVED_97', 'A7XX_PERF_TP_RESERVED_98',
'A7XX_PERF_TP_RESERVED_99', 'A7XX_PERF_TP_SP_TP_TRANS',
'A7XX_PERF_TP_STALL_CYCLES_UCHE', 'A7XX_PERF_TP_STALL_CYCLES_UFC',
'A7XX_PERF_TP_STARVE_CYCLES_SP',
'A7XX_PERF_TP_STARVE_CYCLES_UCHE', 'A7XX_PERF_TP_TPA2TPC_TRANS',
'A7XX_PERF_TP_TP_SP_TRANS', 'A7XX_PERF_TSE_BE_2D_ALIVE_CYCLES',
'A7XX_PERF_TSE_BE_2D_INPUT_PRIM',
'A7XX_PERF_TSE_BE_BR_STALLS_DUETO_BV_CLIP',
'A7XX_PERF_TSE_BE_BR_STALLS_DUETO_BV_POLY',
'A7XX_PERF_TSE_BE_BUSY_CYCLES',
'A7XX_PERF_TSE_BE_BV_STALLS_DUETO_BR',
'A7XX_PERF_TSE_BE_BV_STALLS_DUETO_BR_CLIP',
'A7XX_PERF_TSE_BE_BV_STALLS_DUETO_BR_POLY',
'A7XX_PERF_TSE_BE_CINVOCATION', 'A7XX_PERF_TSE_BE_CLIPPED_PRIM',
'A7XX_PERF_TSE_BE_CLIPPING_CYCLES',
'A7XX_PERF_TSE_BE_CLIP_PLANES', 'A7XX_PERF_TSE_BE_CPRIMITIVES',
'A7XX_PERF_TSE_BE_EARLY_CULL_CLIPPED_PRIM',
'A7XX_PERF_TSE_BE_EMPTY_BBOX_KILLED_PRIM',
'A7XX_PERF_TSE_BE_EXCLUDED_PRIM',
'A7XX_PERF_TSE_BE_FACENESS_CULLED_PRIM',
'A7XX_PERF_TSE_BE_ILLEGAL_BOUNDING_BOX_PRIM',
'A7XX_PERF_TSE_BE_INPUT_NULL_PRIM', 'A7XX_PERF_TSE_BE_INPUT_PRIM',
'A7XX_PERF_TSE_BE_OUTPUT_NULL_PRIM',
'A7XX_PERF_TSE_BE_OUTPUT_VISIBLE_PRIM',
'A7XX_PERF_TSE_BE_ST1_VP_PARAMS_CACHE_MISS',
'A7XX_PERF_TSE_BE_ST2_SCISSOR_VP_PARAMS_CACHE_MISS',
'A7XX_PERF_TSE_BE_ST2_VPORT_VP_PARAMS_CACHE_MISS',
'A7XX_PERF_TSE_BE_STALL_CYCLES_LRZ_BARYPLANE',
'A7XX_PERF_TSE_BE_STALL_CYCLES_LRZ_PRIM',
'A7XX_PERF_TSE_BE_STALL_CYCLES_LRZ_ZPLANE',
'A7XX_PERF_TSE_BE_STALL_CYCLES_RAS',
'A7XX_PERF_TSE_BE_STARVE_CYCLES_PC',
'A7XX_PERF_TSE_BE_TRIVAL_REJ_PRIM',
'A7XX_PERF_TSE_BE_VP_OUT_IS_NAN',
'A7XX_PERF_TSE_BE_ZERO_AREA_PRIM',
'A7XX_PERF_TSE_BE_ZERO_PIXEL_PRIM',
'A7XX_PERF_TSE_FE_BR_STALLS_DUETO_BV_CLIP',
'A7XX_PERF_TSE_FE_BR_STALLS_DUETO_BV_POLY',
'A7XX_PERF_TSE_FE_BUSY_CYCLES',
'A7XX_PERF_TSE_FE_BV_STALLS_DUETO_BR',
'A7XX_PERF_TSE_FE_BV_STALLS_DUETO_BR_CLIP',
'A7XX_PERF_TSE_FE_BV_STALLS_DUETO_BR_POLY',
'A7XX_PERF_TSE_FE_CINVOCATION', 'A7XX_PERF_TSE_FE_CLIP_PLANES',
'A7XX_PERF_TSE_FE_CPRIMITIVES',
'A7XX_PERF_TSE_FE_EARLY_CULL_CLIPPED_PRIM',
'A7XX_PERF_TSE_FE_EMPTY_BBOX_KILLED_PRIM',
'A7XX_PERF_TSE_FE_EXCLUDED_PRIM',
'A7XX_PERF_TSE_FE_FACENESS_CULLED_PRIM',
'A7XX_PERF_TSE_FE_ILLEGAL_BOUNDING_BOX_PRIM',
'A7XX_PERF_TSE_FE_INPUT_NULL_PRIM', 'A7XX_PERF_TSE_FE_INPUT_PRIM',
'A7XX_PERF_TSE_FE_OUTPUT_NULL_PRIM',
'A7XX_PERF_TSE_FE_OUTPUT_VISIBLE_PRIM',
'A7XX_PERF_TSE_FE_ST1_VP_PARAMS_CACHE_MISS',
'A7XX_PERF_TSE_FE_ST2_SCISSOR_VP_PARAMS_CACHE_MISS',
'A7XX_PERF_TSE_FE_ST2_VPORT_VP_PARAMS_CACHE_MISS',
'A7XX_PERF_TSE_FE_STALL_CYCLES_VPC_US',
'A7XX_PERF_TSE_FE_STARVE_CYCLES_PC',
'A7XX_PERF_TSE_FE_TRIVAL_REJ_PRIM',
'A7XX_PERF_TSE_FE_VP_OUT_IS_NAN',
'A7XX_PERF_TSE_FE_ZERO_AREA_PRIM',
'A7XX_PERF_TSE_FE_ZERO_PIXEL_PRIM', 'A7XX_PERF_TSE_NEVER_COUNT',
'A7XX_PERF_UCHE_ARBITER_STALL_CYCLES_VBIF',
'A7XX_PERF_UCHE_BANK_REQ0', 'A7XX_PERF_UCHE_BANK_REQ1',
'A7XX_PERF_UCHE_BANK_REQ2', 'A7XX_PERF_UCHE_BANK_REQ3',
'A7XX_PERF_UCHE_BANK_REQ4', 'A7XX_PERF_UCHE_BANK_REQ5',
'A7XX_PERF_UCHE_BANK_REQ6', 'A7XX_PERF_UCHE_BANK_REQ7',
'A7XX_PERF_UCHE_BUSY_CYCLES',
'A7XX_PERF_UCHE_CCHE_DPH_CMDPOOL_FULL',
'A7XX_PERF_UCHE_CCHE_DPH_IO_QUEUE_FULL',
'A7XX_PERF_UCHE_CCHE_TPH_QUEUE_FULL',
'A7XX_PERF_UCHE_DBANK_CONFLICT_CL_CCHE',
'A7XX_PERF_UCHE_DBANK_CONFLICT_CL_OTHER_CLIENTS',
'A7XX_PERF_UCHE_DCMP_LATENCY_CYCLES',
'A7XX_PERF_UCHE_DCMP_LATENCY_SAMPLES', 'A7XX_PERF_UCHE_EVICTS',
'A7XX_PERF_UCHE_EVICTS_LRZ', 'A7XX_PERF_UCHE_EVICTS_SP',
'A7XX_PERF_UCHE_GMEM_READ_BEATS',
'A7XX_PERF_UCHE_GMEM_WRITE_BEATS',
'A7XX_PERF_UCHE_LONG_LINE_ALL_EVICTS',
'A7XX_PERF_UCHE_LONG_LINE_PARTIAL_EVICTS',
'A7XX_PERF_UCHE_NEVER_COUNT', 'A7XX_PERF_UCHE_RAM_READ_REQ',
'A7XX_PERF_UCHE_RAM_WRITE_REQ',
'A7XX_PERF_UCHE_READ_REQUESTS_HLSQ',
'A7XX_PERF_UCHE_READ_REQUESTS_LRZ',
'A7XX_PERF_UCHE_READ_REQUESTS_PC',
'A7XX_PERF_UCHE_READ_REQUESTS_SP',
'A7XX_PERF_UCHE_READ_REQUESTS_TP',
'A7XX_PERF_UCHE_READ_REQUESTS_TP_GBIF',
'A7XX_PERF_UCHE_READ_REQUESTS_TP_GMEM',
'A7XX_PERF_UCHE_READ_REQUESTS_TP_UBWC',
'A7XX_PERF_UCHE_READ_REQUESTS_VFD',
'A7XX_PERF_UCHE_READ_REQUESTS_VFD_BYPASS_BR',
'A7XX_PERF_UCHE_READ_REQUESTS_VFD_BYPASS_BV',
'A7XX_PERF_UCHE_READ_REQUESTS_VPC',
'A7XX_PERF_UCHE_READ_REQUESTS_VPCUS',
'A7XX_PERF_UCHE_RESERVED_100', 'A7XX_PERF_UCHE_RESERVED_101',
'A7XX_PERF_UCHE_RESERVED_102', 'A7XX_PERF_UCHE_RESERVED_103',
'A7XX_PERF_UCHE_RESERVED_104', 'A7XX_PERF_UCHE_RESERVED_105',
'A7XX_PERF_UCHE_RESERVED_106', 'A7XX_PERF_UCHE_RESERVED_107',
'A7XX_PERF_UCHE_RESERVED_108', 'A7XX_PERF_UCHE_RESERVED_109',
'A7XX_PERF_UCHE_RESERVED_110', 'A7XX_PERF_UCHE_RESERVED_111',
'A7XX_PERF_UCHE_RESERVED_112', 'A7XX_PERF_UCHE_RESERVED_113',
'A7XX_PERF_UCHE_RESERVED_114', 'A7XX_PERF_UCHE_RESERVED_115',
'A7XX_PERF_UCHE_RESERVED_116', 'A7XX_PERF_UCHE_RESERVED_117',
'A7XX_PERF_UCHE_RESERVED_118', 'A7XX_PERF_UCHE_RESERVED_119',
'A7XX_PERF_UCHE_RESERVED_120', 'A7XX_PERF_UCHE_RESERVED_121',
'A7XX_PERF_UCHE_RESERVED_122', 'A7XX_PERF_UCHE_RESERVED_123',
'A7XX_PERF_UCHE_RESERVED_124', 'A7XX_PERF_UCHE_RESERVED_125',
'A7XX_PERF_UCHE_RESERVED_126', 'A7XX_PERF_UCHE_RESERVED_127',
'A7XX_PERF_UCHE_RESERVED_75', 'A7XX_PERF_UCHE_RESERVED_76',
'A7XX_PERF_UCHE_RESERVED_77', 'A7XX_PERF_UCHE_RESERVED_78',
'A7XX_PERF_UCHE_RESERVED_79', 'A7XX_PERF_UCHE_RESERVED_80',
'A7XX_PERF_UCHE_RESERVED_81', 'A7XX_PERF_UCHE_RESERVED_82',
'A7XX_PERF_UCHE_RESERVED_83', 'A7XX_PERF_UCHE_RESERVED_84',
'A7XX_PERF_UCHE_RESERVED_85', 'A7XX_PERF_UCHE_RESERVED_86',
'A7XX_PERF_UCHE_RESERVED_87', 'A7XX_PERF_UCHE_RESERVED_88',
'A7XX_PERF_UCHE_RESERVED_89', 'A7XX_PERF_UCHE_RESERVED_90',
'A7XX_PERF_UCHE_RESERVED_91', 'A7XX_PERF_UCHE_RESERVED_92',
'A7XX_PERF_UCHE_RESERVED_93', 'A7XX_PERF_UCHE_RESERVED_94',
'A7XX_PERF_UCHE_RESERVED_95', 'A7XX_PERF_UCHE_RESERVED_96',
'A7XX_PERF_UCHE_RESERVED_97', 'A7XX_PERF_UCHE_RESERVED_98',
'A7XX_PERF_UCHE_RESERVED_99',
'A7XX_PERF_UCHE_STALL_CYCLES_ARBITER',
'A7XX_PERF_UCHE_STALL_CYCLES_DECMP',
'A7XX_PERF_UCHE_STARVED_CYCLES_VBIF_DECMP',
'A7XX_PERF_UCHE_TPH_CONFLICT_CL_CCHE',
'A7XX_PERF_UCHE_TPH_CONFLICT_CL_OTHER',
'A7XX_PERF_UCHE_TPH_EXT_FULL', 'A7XX_PERF_UCHE_TPH_REF_FULL',
'A7XX_PERF_UCHE_TPH_VICTIM_FULL',
'A7XX_PERF_UCHE_UBWC_READ_BEATS',
'A7XX_PERF_UCHE_UBWC_WRITE_BEATS',
'A7XX_PERF_UCHE_VBIF_LATENCY_CYCLES',
'A7XX_PERF_UCHE_VBIF_LATENCY_SAMPLES',
'A7XX_PERF_UCHE_VBIF_READ_BEATS_CH0',
'A7XX_PERF_UCHE_VBIF_READ_BEATS_CH1',
'A7XX_PERF_UCHE_VBIF_READ_BEATS_HLSQ',
'A7XX_PERF_UCHE_VBIF_READ_BEATS_LRZ',
'A7XX_PERF_UCHE_VBIF_READ_BEATS_PC',
'A7XX_PERF_UCHE_VBIF_READ_BEATS_SP',
'A7XX_PERF_UCHE_VBIF_READ_BEATS_TP',
'A7XX_PERF_UCHE_VBIF_READ_BEATS_VFD',
'A7XX_PERF_UCHE_VBIF_READ_BEATS_VPC',
'A7XX_PERF_UCHE_VBIF_STALL_WRITE_DATA',
'A7XX_PERF_UCHE_VBIF_WRITE_BEATS_CH0',
'A7XX_PERF_UCHE_VBIF_WRITE_BEATS_CH1',
'A7XX_PERF_UCHE_WRITE_REQUESTS_LRZ',
'A7XX_PERF_UCHE_WRITE_REQUESTS_SP',
'A7XX_PERF_UCHE_WRITE_REQUESTS_VPC',
'A7XX_PERF_UCHE_WRITE_REQUESTS_VSC', 'A7XX_PERF_UFC_BUSY_CYCLES',
'A7XX_PERF_UFC_EVICTION_STALLED_CYCLES',
'A7XX_PERF_UFC_L0_SP_FILTER_HIT',
'A7XX_PERF_UFC_L0_SP_FILTER_MISS', 'A7XX_PERF_UFC_L0_SP_REQUESTS',
'A7XX_PERF_UFC_L0_SP_REQ_STALLED_CYCLES',
'A7XX_PERF_UFC_L0_TP_HINT_IS_ALPHA0',
'A7XX_PERF_UFC_L0_TP_HINT_IS_ALPHA1',
'A7XX_PERF_UFC_L0_TP_HINT_IS_FCLEAR',
'A7XX_PERF_UFC_L0_TP_HINT_IS_UNCOMP',
'A7XX_PERF_UFC_L0_TP_HINT_REQUESTS',
'A7XX_PERF_UFC_L0_TP_HINT_TAG_HIT_NRDY',
'A7XX_PERF_UFC_L0_TP_HINT_TAG_HIT_RDY',
'A7XX_PERF_UFC_L0_TP_HINT_TAG_MISS',
'A7XX_PERF_UFC_L0_TP_REQ_STALLED_CYCLES',
'A7XX_PERF_UFC_L0_TP_RTN_STALLED_CYCLES',
'A7XX_PERF_UFC_L1_CRE_FILTER_HIT',
'A7XX_PERF_UFC_L1_CRE_FILTER_MISS',
'A7XX_PERF_UFC_L1_CRE_REQUESTS',
'A7XX_PERF_UFC_L1_CRE_STALLED_CYCLES',
'A7XX_PERF_UFC_L1_SP_FILTER_HIT',
'A7XX_PERF_UFC_L1_SP_FILTER_MISS', 'A7XX_PERF_UFC_L1_SP_REQUESTS',
'A7XX_PERF_UFC_L1_SP_STALLED_CYCLES',
'A7XX_PERF_UFC_L1_TP_HINT_REQUESTS',
'A7XX_PERF_UFC_L1_TP_HINT_TAG_HIT_NRDY',
'A7XX_PERF_UFC_L1_TP_HINT_TAG_HIT_RDY',
'A7XX_PERF_UFC_L1_TP_HINT_TAG_MISS',
'A7XX_PERF_UFC_L1_TP_STALLED_CYCLES',
'A7XX_PERF_UFC_LOCK_STALLED_CYCLES',
'A7XX_PERF_UFC_MAIN_HIT_CRE_PREFETCH',
'A7XX_PERF_UFC_MAIN_HIT_SP_PREFETCH',
'A7XX_PERF_UFC_MAIN_HIT_TP_PREFETCH',
'A7XX_PERF_UFC_MAIN_HIT_UBWC_READ',
'A7XX_PERF_UFC_MAIN_HIT_UBWC_WRITE',
'A7XX_PERF_UFC_MAIN_MISS_CRE_PREFETCH',
'A7XX_PERF_UFC_MAIN_MISS_SP_PREFETCH',
'A7XX_PERF_UFC_MAIN_MISS_TP_PREFETCH',
'A7XX_PERF_UFC_MAIN_MISS_UBWC_READ',
'A7XX_PERF_UFC_MAIN_MISS_UBWC_WRITE',
'A7XX_PERF_UFC_MAIN_TP_RD_NRDY', 'A7XX_PERF_UFC_MAIN_TP_RD_RDY',
'A7XX_PERF_UFC_MAIN_UBWC_RD_NRDY',
'A7XX_PERF_UFC_MAIN_UBWC_RD_RDY',
'A7XX_PERF_UFC_MISS_LATENCY_CYCLES',
'A7XX_PERF_UFC_MISS_LATENCY_SAMPLES', 'A7XX_PERF_UFC_NEVER_COUNT',
'A7XX_PERF_UFC_PREFETCH_STALLED_CYCLES',
'A7XX_PERF_UFC_READ_DATA_VBIF', 'A7XX_PERF_UFC_READ_REQUEST_VBIF',
'A7XX_PERF_UFC_STALL_CYCLES_GBIF_CMD',
'A7XX_PERF_UFC_STALL_CYCLES_GBIF_RDATA',
'A7XX_PERF_UFC_STALL_CYCLES_GBIF_WDATA',
'A7XX_PERF_UFC_STALL_CYCLES_UBWC_EVENT',
'A7XX_PERF_UFC_STALL_CYCLES_UBWC_FLAG_RTN',
'A7XX_PERF_UFC_STALL_CYCLES_UBWC_WR_FLAG',
'A7XX_PERF_UFC_UBWC_RD_STALLED_CYCLES',
'A7XX_PERF_UFC_UBWC_REQ_STALLED_CYCLES',
'A7XX_PERF_UFC_UBWC_WR_STALLED_CYCLES',
'A7XX_PERF_UFC_WRITE_DATA_VBIF',
'A7XX_PERF_UFC_WRITE_REQUEST_VBIF',
'A7XX_PERF_VFDP_STALL_CYCLES_VFD',
'A7XX_PERF_VFDP_STALL_CYCLES_VFD_INDEX',
'A7XX_PERF_VFDP_STALL_CYCLES_VFD_PROG',
'A7XX_PERF_VFDP_STARVE_CYCLES_PC',
'A7XX_PERF_VFDP_VS_STAGE_WAVES',
'A7XX_PERF_VFD_ATTR_INFO_FIFO_FULL', 'A7XX_PERF_VFD_BUSY_CYCLES',
'A7XX_PERF_VFD_DECODED_ATTRIBUTE_BYTES',
'A7XX_PERF_VFD_LOWER_SHADER_FIBERS',
'A7XX_PERF_VFD_MODE_0_FIBERS', 'A7XX_PERF_VFD_MODE_1_FIBERS',
'A7XX_PERF_VFD_MODE_2_FIBERS', 'A7XX_PERF_VFD_MODE_3_FIBERS',
'A7XX_PERF_VFD_MODE_4_FIBERS', 'A7XX_PERF_VFD_NEVER_COUNT',
'A7XX_PERF_VFD_NUM_ATTRIBUTES', 'A7XX_PERF_VFD_RBUFFER_FULL',
'A7XX_PERF_VFD_STALL_CYCLES_CBSYNC',
'A7XX_PERF_VFD_STALL_CYCLES_PRG_END_FE',
'A7XX_PERF_VFD_STALL_CYCLES_SP_ATTR',
'A7XX_PERF_VFD_STALL_CYCLES_SP_INFO',
'A7XX_PERF_VFD_STALL_CYCLES_UCHE',
'A7XX_PERF_VFD_STALL_CYCLES_VPC_ALLOC',
'A7XX_PERF_VFD_STARVE_CYCLES_UCHE',
'A7XX_PERF_VFD_TOTAL_VERTICES',
'A7XX_PERF_VFD_UPPER_SHADER_FIBERS', 'A7XX_PERF_VHUB_PTABLE_FULL',
'A7XX_PERF_VPC_BE_BOTTLENECK', 'A7XX_PERF_VPC_BE_BUSY_CYCLES',
'A7XX_PERF_VPC_BE_CCHE_NUM_POS_REQ',
'A7XX_PERF_VPC_BE_CCHE_REQBUF_FULL',
'A7XX_PERF_VPC_BE_LM_FULL_WAIT_FOR_INTP_END',
'A7XX_PERF_VPC_BE_LM_TRANSACTION',
'A7XX_PERF_VPC_BE_LRZ_ASSIGN_PRIMITIVES',
'A7XX_PERF_VPC_BE_NUM_ATTR_REQ_LM',
'A7XX_PERF_VPC_BE_NUM_LM_REQ_HIT', 'A7XX_PERF_VPC_BE_NUM_PA_REQ',
'A7XX_PERF_VPC_BE_POS_OVERFETCH_ATTR',
'A7XX_PERF_VPC_BE_PS_BUSY_CYCLES',
'A7XX_PERF_VPC_BE_PS_WORKING_CYCLES',
'A7XX_PERF_VPC_BE_RB_VISIBLE_PRIMITIVES',
'A7XX_PERF_VPC_BE_STALL_CYCLES_CCHE',
'A7XX_PERF_VPC_BE_STALL_CYCLES_HLSQ_PRIM_ALLOC',
'A7XX_PERF_VPC_BE_STALL_CYCLES_LM_ACK',
'A7XX_PERF_VPC_BE_STALL_CYCLES_PRG_END_VPCPS',
'A7XX_PERF_VPC_BE_STALL_CYCLES_SP_LM',
'A7XX_PERF_VPC_BE_STALL_CYCLES_TSE_BE',
'A7XX_PERF_VPC_BE_STARVE_CYCLES_CCHE',
'A7XX_PERF_VPC_BE_STARVE_CYCLES_LRZ',
'A7XX_PERF_VPC_BE_STARVE_CYCLES_RB',
'A7XX_PERF_VPC_BE_TSE_BE_PRIMITIVES',
'A7XX_PERF_VPC_BE_TSE_BE_TRANSACTIONS',
'A7XX_PERF_VPC_BE_WORKING_CYCLES', 'A7XX_PERF_VPC_FE_BOTTLENECK',
'A7XX_PERF_VPC_FE_BUSY_CYCLES',
'A7XX_PERF_VPC_FE_GMEM_NOP_FULL_CYCLES',
'A7XX_PERF_VPC_FE_GMEM_POS_FULL_CYCLES',
'A7XX_PERF_VPC_FE_GS_PRIMITIVES',
'A7XX_PERF_VPC_FE_NUM_VPCRAM_READ_POS',
'A7XX_PERF_VPC_FE_NUM_VPCRAM_WRITE',
'A7XX_PERF_VPC_FE_NUM_WM_HIT', 'A7XX_PERF_VPC_FE_PC_PRIMITIVES',
'A7XX_PERF_VPC_FE_POSRAM_FULL_CYCLES',
'A7XX_PERF_VPC_FE_SP_COMPONENTS',
'A7XX_PERF_VPC_FE_STALL_CYCLES_CCU',
'A7XX_PERF_VPC_FE_STALL_CYCLES_PRG_END_FE',
'A7XX_PERF_VPC_FE_STALL_CYCLES_PRG_END_VPCVS',
'A7XX_PERF_VPC_FE_STALL_CYCLES_TSE_FE',
'A7XX_PERF_VPC_FE_STALL_CYCLES_VFD_WACK',
'A7XX_PERF_VPC_FE_STALL_CYCLES_VPCRAM_POS',
'A7XX_PERF_VPC_FE_STALL_CYCLES_VPC_US',
'A7XX_PERF_VPC_FE_STALL_DQ_WACK',
'A7XX_PERF_VPC_FE_STARVE_CYCLES_SP',
'A7XX_PERF_VPC_FE_TSE_FE_PRIMITIVES',
'A7XX_PERF_VPC_FE_TSE_FE_TRANSACTIONS',
'A7XX_PERF_VPC_FE_VPCRAM_FULL_CYCLES',
'A7XX_PERF_VPC_FE_VS_BUSY_CYCLES',
'A7XX_PERF_VPC_FE_VS_WORKING_CYCLES',
'A7XX_PERF_VPC_FE_WIT_FULL_CYCLES',
'A7XX_PERF_VPC_FE_WORKING_CYCLES', 'A7XX_PERF_VPC_NEVER_COUNT',
'A7XX_PERF_VPC_RESERVED_42', 'A7XX_PERF_VPC_RESERVED_43',
'A7XX_PERF_VPC_RESERVED_44', 'A7XX_PERF_VPC_US_BOTTLENECK',
'A7XX_PERF_VPC_US_BUSY_CYCLES',
'A7XX_PERF_VPC_US_COMP_INVIS_PRIM_COUNT',
'A7XX_PERF_VPC_US_NUM_GMEM_READ_SO', 'A7XX_PERF_VPC_US_PTUS_FULL',
'A7XX_PERF_VPC_US_STALL_CYCLES_PRG_END_VPCUS',
'A7XX_PERF_VPC_US_STALL_CYCLES_UCHE',
'A7XX_PERF_VPC_US_STALL_CYCLES_VPC_BE',
'A7XX_PERF_VPC_US_STALL_CYCLES_VSC',
'A7XX_PERF_VPC_US_STARVE_CYCLES_REORDER',
'A7XX_PERF_VPC_US_STARVE_CYCLES_TSE_FE',
'A7XX_PERF_VPC_US_STARVE_CYCLES_UCHE_RD',
'A7XX_PERF_VPC_US_STREAMOUT_TRANSACTION',
'A7XX_PERF_VPC_US_WORKING_CYCLES', 'A7XX_PERF_VSC_BUSY_CYCLES',
'A7XX_PERF_VSC_EOT_NUM', 'A7XX_PERF_VSC_INPUT_TILES',
'A7XX_PERF_VSC_NEVER_COUNT', 'A7XX_PERF_VSC_STALL_CYCLES_UCHE',
'A7XX_PERF_VSC_TILE_BYPASS_TRAN', 'A7XX_PERF_VSC_TILE_COMP_TRAN',
'A7XX_PERF_VSC_WORKING_CYCLES', 'A7XX_PIPE_BR', 'A7XX_PIPE_BV',
'A7XX_PIPE_LPAC', 'A7XX_PIPE_NONE',
'A7XX_RBBM_CGC_P2S_STATUS_TXDONE',
'A7XX_RB_BIN_CONTROL_BINH__MASK',
'A7XX_RB_BIN_CONTROL_BINH__SHIFT',
'A7XX_RB_BIN_CONTROL_BINW__MASK',
'A7XX_RB_BIN_CONTROL_BINW__SHIFT',
'A7XX_RB_BIN_CONTROL_FORCE_LRZ_WRITE_DIS',
'A7XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK',
'A7XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT',
'A7XX_RB_BIN_CONTROL_RENDER_MODE__MASK',
'A7XX_RB_BIN_CONTROL_RENDER_MODE__SHIFT',
'A7XX_RB_CCU_CNTL2_COLOR_CACHE_SIZE__MASK',
'A7XX_RB_CCU_CNTL2_COLOR_CACHE_SIZE__SHIFT',
'A7XX_RB_CCU_CNTL2_COLOR_OFFSET_HI__MASK',
'A7XX_RB_CCU_CNTL2_COLOR_OFFSET_HI__SHIFT',
'A7XX_RB_CCU_CNTL2_COLOR_OFFSET__MASK',
'A7XX_RB_CCU_CNTL2_COLOR_OFFSET__SHIFT',
'A7XX_RB_CCU_CNTL2_DEPTH_CACHE_SIZE__MASK',
'A7XX_RB_CCU_CNTL2_DEPTH_CACHE_SIZE__SHIFT',
'A7XX_RB_CCU_CNTL2_DEPTH_OFFSET_HI__MASK',
'A7XX_RB_CCU_CNTL2_DEPTH_OFFSET_HI__SHIFT',
'A7XX_RB_CCU_CNTL2_DEPTH_OFFSET__MASK',
'A7XX_RB_CCU_CNTL2_DEPTH_OFFSET__SHIFT',
'A7XX_RB_CCU_CNTL_CONCURRENT_RESOLVE',
'A7XX_RB_CCU_CNTL_GMEM_FAST_CLEAR_DISABLE',
'A7XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK',
'A7XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT',
'A7XX_RB_DEPTH_BUFFER_INFO_LOSSLESSCOMPEN',
'A7XX_RB_DEPTH_BUFFER_INFO_TILEMODE__MASK',
'A7XX_RB_DEPTH_BUFFER_INFO_TILEMODE__SHIFT',
'A7XX_RB_DEPTH_BUFFER_INFO_UNK3__MASK',
'A7XX_RB_DEPTH_BUFFER_INFO_UNK3__SHIFT',
'A7XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK',
'A7XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT',
'A7XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK',
'A7XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT',
'A7XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK',
'A7XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT',
'A7XX_RB_MRT_BUF_INFO_LOSSLESSCOMPEN',
'A7XX_RB_MRT_BUF_INFO_UNK10', 'A7XX_RB_RENDER_CNTL_BINNING',
'A7XX_RB_RENDER_CNTL_CONSERVATIVERASEN',
'A7XX_RB_RENDER_CNTL_EARLYVIZOUTEN',
'A7XX_RB_RENDER_CNTL_INNERCONSERVATIVERASEN',
'A7XX_RB_RENDER_CNTL_RASTER_DIRECTION__MASK',
'A7XX_RB_RENDER_CNTL_RASTER_DIRECTION__SHIFT',
'A7XX_RB_RENDER_CNTL_RASTER_MODE__MASK',
'A7XX_RB_RENDER_CNTL_RASTER_MODE__SHIFT',
'A7XX_RB_STENCIL_INFO_SEPARATE_STENCIL',
'A7XX_RB_STENCIL_INFO_TILEMODE__MASK',
'A7XX_RB_STENCIL_INFO_TILEMODE__SHIFT',
'A7XX_RB_STENCIL_INFO_UNK1', 'A7XX_RB_UNKNOWN_88E4_UNK0',
'A7XX_SP_2D_DST_FORMAT_COLOR_FORMAT__MASK',
'A7XX_SP_2D_DST_FORMAT_COLOR_FORMAT__SHIFT',
'A7XX_SP_2D_DST_FORMAT_MASK__MASK',
'A7XX_SP_2D_DST_FORMAT_MASK__SHIFT', 'A7XX_SP_2D_DST_FORMAT_NORM',
'A7XX_SP_2D_DST_FORMAT_SINT', 'A7XX_SP_2D_DST_FORMAT_SRGB',
'A7XX_SP_2D_DST_FORMAT_UINT',
'A7XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK',
'A7XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT',
'A7XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK',
'A7XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT',
'A7XX_SP_CB_RAM',
'A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK',
'A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT',
'A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK',
'A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT',
'A7XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__MASK',
'A7XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT',
'A7XX_SP_CS_CNTL_1_THREADSIZE_SCALAR',
'A7XX_SP_CS_CNTL_1_THREADSIZE__MASK',
'A7XX_SP_CS_CNTL_1_THREADSIZE__SHIFT', 'A7XX_SP_CS_CNTL_1_UNK15',
'A7XX_SP_CTX0_3D_CPS_REG', 'A7XX_SP_CTX0_3D_CVS_REG',
'A7XX_SP_CTX1_3D_CPS_REG', 'A7XX_SP_CTX1_3D_CVS_REG',
'A7XX_SP_CTX2_3D_CPS_REG', 'A7XX_SP_CTX3_3D_CPS_REG',
'A7XX_SP_FS_PREFETCH_CMD_BINDLESS',
'A7XX_SP_FS_PREFETCH_CMD_CMD__MASK',
'A7XX_SP_FS_PREFETCH_CMD_CMD__SHIFT',
'A7XX_SP_FS_PREFETCH_CMD_DST__MASK',
'A7XX_SP_FS_PREFETCH_CMD_DST__SHIFT',
'A7XX_SP_FS_PREFETCH_CMD_HALF',
'A7XX_SP_FS_PREFETCH_CMD_SAMP_ID__MASK',
'A7XX_SP_FS_PREFETCH_CMD_SAMP_ID__SHIFT',
'A7XX_SP_FS_PREFETCH_CMD_SRC__MASK',
'A7XX_SP_FS_PREFETCH_CMD_SRC__SHIFT',
'A7XX_SP_FS_PREFETCH_CMD_TEX_ID__MASK',
'A7XX_SP_FS_PREFETCH_CMD_TEX_ID__SHIFT',
'A7XX_SP_FS_PREFETCH_CMD_WRMASK__MASK',
'A7XX_SP_FS_PREFETCH_CMD_WRMASK__SHIFT', 'A7XX_SP_HWAVE_RAM',
'A7XX_SP_INST_DATA', 'A7XX_SP_INST_DATA_1', 'A7XX_SP_INST_DATA_2',
'A7XX_SP_INST_TAG', 'A7XX_SP_L0_INST_BUF', 'A7XX_SP_LB_0_DATA',
'A7XX_SP_LB_10_DATA', 'A7XX_SP_LB_11_DATA', 'A7XX_SP_LB_12_DATA',
'A7XX_SP_LB_13_DATA', 'A7XX_SP_LB_14_DATA', 'A7XX_SP_LB_1_DATA',
'A7XX_SP_LB_2_DATA', 'A7XX_SP_LB_3_DATA', 'A7XX_SP_LB_4_DATA',
'A7XX_SP_LB_5_DATA', 'A7XX_SP_LB_6_DATA', 'A7XX_SP_LB_7_DATA',
'A7XX_SP_LB_8_DATA', 'A7XX_SP_LB_9_DATA', 'A7XX_SP_NCTX_REG',
'A7XX_SP_PS_2D_SRC_FLAGS_PITCH__MASK',
'A7XX_SP_PS_2D_SRC_FLAGS_PITCH__SHIFT',
'A7XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK',
'A7XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT',
'A7XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK',
'A7XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT',
'A7XX_SP_PS_2D_SRC_INFO_FILTER', 'A7XX_SP_PS_2D_SRC_INFO_FLAGS',
'A7XX_SP_PS_2D_SRC_INFO_SAMPLES_AVERAGE',
'A7XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK',
'A7XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT',
'A7XX_SP_PS_2D_SRC_INFO_SRGB',
'A7XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK',
'A7XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT',
'A7XX_SP_PS_2D_SRC_INFO_UNK17', 'A7XX_SP_PS_2D_SRC_INFO_UNK19',
'A7XX_SP_PS_2D_SRC_INFO_UNK20', 'A7XX_SP_PS_2D_SRC_INFO_UNK21',
'A7XX_SP_PS_2D_SRC_INFO_UNK22',
'A7XX_SP_PS_2D_SRC_INFO_UNK23__MASK',
'A7XX_SP_PS_2D_SRC_INFO_UNK23__SHIFT',
'A7XX_SP_PS_2D_SRC_INFO_UNK28',
'A7XX_SP_PS_2D_SRC_PITCH_PITCH__MASK',
'A7XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT',
'A7XX_SP_PS_2D_SRC_PITCH_UNK0__MASK',
'A7XX_SP_PS_2D_SRC_PITCH_UNK0__SHIFT',
'A7XX_SP_PS_2D_SRC_PLANE_PITCH__MASK',
'A7XX_SP_PS_2D_SRC_PLANE_PITCH__SHIFT',
'A7XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK',
'A7XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT',
'A7XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK',
'A7XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT',
'A7XX_SP_PS_2D_WINDOW_OFFSET_X__MASK',
'A7XX_SP_PS_2D_WINDOW_OFFSET_X__SHIFT',
'A7XX_SP_PS_2D_WINDOW_OFFSET_Y__MASK',
'A7XX_SP_PS_2D_WINDOW_OFFSET_Y__SHIFT',
'A7XX_SP_PS_ALIASED_COMPONENTS_CONTROL_ENABLED',
'A7XX_SP_PS_ALIASED_COMPONENTS_RT0__MASK',
'A7XX_SP_PS_ALIASED_COMPONENTS_RT0__SHIFT',
'A7XX_SP_PS_ALIASED_COMPONENTS_RT1__MASK',
'A7XX_SP_PS_ALIASED_COMPONENTS_RT1__SHIFT',
'A7XX_SP_PS_ALIASED_COMPONENTS_RT2__MASK',
'A7XX_SP_PS_ALIASED_COMPONENTS_RT2__SHIFT',
'A7XX_SP_PS_ALIASED_COMPONENTS_RT3__MASK',
'A7XX_SP_PS_ALIASED_COMPONENTS_RT3__SHIFT',
'A7XX_SP_PS_ALIASED_COMPONENTS_RT4__MASK',
'A7XX_SP_PS_ALIASED_COMPONENTS_RT4__SHIFT',
'A7XX_SP_PS_ALIASED_COMPONENTS_RT5__MASK',
'A7XX_SP_PS_ALIASED_COMPONENTS_RT5__SHIFT',
'A7XX_SP_PS_ALIASED_COMPONENTS_RT6__MASK',
'A7XX_SP_PS_ALIASED_COMPONENTS_RT6__SHIFT',
'A7XX_SP_PS_ALIASED_COMPONENTS_RT7__MASK',
'A7XX_SP_PS_ALIASED_COMPONENTS_RT7__SHIFT',
'A7XX_SP_READ_SEL_LOCATION__MASK',
'A7XX_SP_READ_SEL_LOCATION__SHIFT', 'A7XX_SP_READ_SEL_PIPE__MASK',
'A7XX_SP_READ_SEL_PIPE__SHIFT', 'A7XX_SP_READ_SEL_SPTP__MASK',
'A7XX_SP_READ_SEL_SPTP__SHIFT',
'A7XX_SP_READ_SEL_STATETYPE__MASK',
'A7XX_SP_READ_SEL_STATETYPE__SHIFT',
'A7XX_SP_READ_SEL_USPTP__MASK', 'A7XX_SP_READ_SEL_USPTP__SHIFT',
'A7XX_SP_SMO_TAG', 'A7XX_SP_STATE_DATA', 'A7XX_SP_TMO_TAG',
'A7XX_SP_TOP', 'A7XX_SP_WINDOW_OFFSET_X__MASK',
'A7XX_SP_WINDOW_OFFSET_X__SHIFT', 'A7XX_SP_WINDOW_OFFSET_Y__MASK',
'A7XX_SP_WINDOW_OFFSET_Y__SHIFT', 'A7XX_TP0_CTX0_3D_CPS_REG',
'A7XX_TP0_CTX0_3D_CVS_REG', 'A7XX_TP0_CTX1_3D_CPS_REG',
'A7XX_TP0_CTX1_3D_CVS_REG', 'A7XX_TP0_CTX2_3D_CPS_REG',
'A7XX_TP0_CTX3_3D_CPS_REG', 'A7XX_TP0_MIPMAP_BASE_DATA',
'A7XX_TP0_NCTX_REG', 'A7XX_TP0_SMO_DATA', 'A7XX_TP0_TMO_DATA',
'A7XX_USPTP', 'A7XX_VPC_ATTR_BUF_BASE_GMEM_BASE_GMEM__MASK',
'A7XX_VPC_ATTR_BUF_BASE_GMEM_BASE_GMEM__SHIFT',
'A7XX_VPC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__MASK',
'A7XX_VPC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__SHIFT',
'A7XX_VPC_MULTIVIEW_CNTL_DISABLEMULTIPOS',
'A7XX_VPC_MULTIVIEW_CNTL_ENABLE',
'A7XX_VPC_MULTIVIEW_CNTL_VIEWS__MASK',
'A7XX_VPC_MULTIVIEW_CNTL_VIEWS__SHIFT',
'A7XX_VPC_POLYGON_MODE2_MODE__MASK',
'A7XX_VPC_POLYGON_MODE2_MODE__SHIFT',
'A7XX_VPC_PRIMITIVE_CNTL_0_D3D_VERTEX_ORDERING',
'A7XX_VPC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART',
'A7XX_VPC_PRIMITIVE_CNTL_0_PROVOKING_VTX_LAST',
'A7XX_VPC_PRIMITIVE_CNTL_0_UNK3',
'A7XX_VPC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__MASK',
'A7XX_VPC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__SHIFT',
'A7XX_VPC_PRIMITIVE_CNTL_5_GS_OUTPUT__MASK',
'A7XX_VPC_PRIMITIVE_CNTL_5_GS_OUTPUT__SHIFT',
'A7XX_VPC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__MASK',
'A7XX_VPC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__SHIFT',
'A7XX_VPC_PRIMITIVE_CNTL_5_LINELENGTHEN',
'A7XX_VPC_PRIMITIVE_CNTL_5_UNK18',
'A7XX_VSC_UNKNOWN_0CD8_BINNING', 'ADDR_32B', 'ADDR_64B',
'AXXX_CP_CSQ_AVAIL_IB1__MASK', 'AXXX_CP_CSQ_AVAIL_IB1__SHIFT',
'AXXX_CP_CSQ_AVAIL_IB2__MASK', 'AXXX_CP_CSQ_AVAIL_IB2__SHIFT',
'AXXX_CP_CSQ_AVAIL_RING__MASK', 'AXXX_CP_CSQ_AVAIL_RING__SHIFT',
'AXXX_CP_CSQ_IB1_STAT_RPTR__MASK',
'AXXX_CP_CSQ_IB1_STAT_RPTR__SHIFT',
'AXXX_CP_CSQ_IB1_STAT_WPTR__MASK',
'AXXX_CP_CSQ_IB1_STAT_WPTR__SHIFT',
'AXXX_CP_CSQ_IB2_STAT_RPTR__MASK',
'AXXX_CP_CSQ_IB2_STAT_RPTR__SHIFT',
'AXXX_CP_CSQ_IB2_STAT_WPTR__MASK',
'AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT',
'AXXX_CP_CSQ_RB_STAT_RPTR__MASK',
'AXXX_CP_CSQ_RB_STAT_RPTR__SHIFT',
'AXXX_CP_CSQ_RB_STAT_WPTR__MASK',
'AXXX_CP_CSQ_RB_STAT_WPTR__SHIFT',
'AXXX_CP_DEBUG_DYNAMIC_CLK_DISABLE',
'AXXX_CP_DEBUG_MIU_128BIT_WRITE_ENABLE',
'AXXX_CP_DEBUG_MIU_WRITE_PACK_DISABLE',
'AXXX_CP_DEBUG_PREDICATE_DISABLE',
'AXXX_CP_DEBUG_PREFETCH_MATCH_DISABLE',
'AXXX_CP_DEBUG_PREFETCH_PASS_NOPS',
'AXXX_CP_DEBUG_PROG_END_PTR_ENABLE',
'AXXX_CP_DEBUG_SIMPLE_ME_FLOW_CONTROL',
'AXXX_CP_INT_CNTL_IB1_INT_MASK', 'AXXX_CP_INT_CNTL_IB2_INT_MASK',
'AXXX_CP_INT_CNTL_IB_ERROR_MASK',
'AXXX_CP_INT_CNTL_OPCODE_ERROR_MASK',
'AXXX_CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK',
'AXXX_CP_INT_CNTL_RB_INT_MASK',
'AXXX_CP_INT_CNTL_RESERVED_BIT_ERROR_MASK',
'AXXX_CP_INT_CNTL_SW_INT_MASK',
'AXXX_CP_INT_CNTL_T0_PACKET_IN_IB_MASK',
'AXXX_CP_MEQ_AVAIL_MEQ__MASK', 'AXXX_CP_MEQ_AVAIL_MEQ__SHIFT',
'AXXX_CP_MEQ_THRESHOLDS_MEQ_END__MASK',
'AXXX_CP_MEQ_THRESHOLDS_MEQ_END__SHIFT',
'AXXX_CP_MEQ_THRESHOLDS_ROQ_END__MASK',
'AXXX_CP_MEQ_THRESHOLDS_ROQ_END__SHIFT', 'AXXX_CP_ME_CNTL_BUSY',
'AXXX_CP_ME_CNTL_HALT',
'AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__MASK',
'AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__SHIFT',
'AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__MASK',
'AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__SHIFT',
'AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__MASK',
'AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__SHIFT',
'AXXX_CP_RB_CNTL_BLKSZ__MASK', 'AXXX_CP_RB_CNTL_BLKSZ__SHIFT',
'AXXX_CP_RB_CNTL_BUFSZ__MASK', 'AXXX_CP_RB_CNTL_BUFSZ__SHIFT',
'AXXX_CP_RB_CNTL_BUF_SWAP__MASK',
'AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT', 'AXXX_CP_RB_CNTL_NO_UPDATE',
'AXXX_CP_RB_CNTL_POLL_EN', 'AXXX_CP_RB_CNTL_RPTR_WR_EN',
'AXXX_CP_RB_RPTR_ADDR_ADDR__MASK',
'AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT',
'AXXX_CP_RB_RPTR_ADDR_SWAP__MASK',
'AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT',
'AXXX_CP_STAT_CF_EVENT_FIFO_BUSY', 'AXXX_CP_STAT_CP_3D_BUSY',
'AXXX_CP_STAT_CP_BUSY', 'AXXX_CP_STAT_CP_NRT_BUSY',
'AXXX_CP_STAT_CSF_BUSY', 'AXXX_CP_STAT_CSF_INDIRECT2_BUSY',
'AXXX_CP_STAT_CSF_INDIRECTS_BUSY', 'AXXX_CP_STAT_CSF_RING_BUSY',
'AXXX_CP_STAT_CSF_ST_BUSY', 'AXXX_CP_STAT_EVENT_BUSY',
'AXXX_CP_STAT_INDIRECT2_QUEUE_BUSY',
'AXXX_CP_STAT_INDIRECTS_QUEUE_BUSY', 'AXXX_CP_STAT_MEQ_RING_BUSY',
'AXXX_CP_STAT_ME_BUSY', 'AXXX_CP_STAT_MIU_RD_REQ_BUSY',
'AXXX_CP_STAT_MIU_RD_RETURN_BUSY', 'AXXX_CP_STAT_MIU_WR_BUSY',
'AXXX_CP_STAT_MIU_WR_C_BUSY', 'AXXX_CP_STAT_PFP_BUSY',
'AXXX_CP_STAT_PS_EVENT_FIFO_BUSY', 'AXXX_CP_STAT_RBIU_BUSY',
'AXXX_CP_STAT_RBIU_SCRATCH_BUSY',
'AXXX_CP_STAT_RB_EVENT_FIFO_BUSY', 'AXXX_CP_STAT_RCIU_BUSY',
'AXXX_CP_STAT_RCIU_ME_BUSY', 'AXXX_CP_STAT_RCIU_PFP_BUSY',
'AXXX_CP_STAT_RING_QUEUE_BUSY', 'AXXX_CP_STAT_ST_QUEUE_BUSY',
'AXXX_CP_STAT_VS_EVENT_FIFO_BUSY', 'AXXX_CP_STQ_AVAIL_ST__MASK',
'AXXX_CP_STQ_AVAIL_ST__SHIFT', 'AXXX_SCRATCH_UMSK_SWAP__MASK',
'AXXX_SCRATCH_UMSK_SWAP__SHIFT', 'AXXX_SCRATCH_UMSK_UMSK__MASK',
'AXXX_SCRATCH_UMSK_UMSK__SHIFT', 'BINDLESS_BASE_0_ADDR',
'BINDLESS_BASE_1_ADDR', 'BINDLESS_BASE_2_ADDR',
'BINDLESS_BASE_3_ADDR', 'BINDLESS_BASE_4_ADDR',
'BINDLESS_BASE_5_ADDR', 'BINDLESS_BASE_6_ADDR',
'BINDLESS_DESCRIPTOR_16B', 'BINDLESS_DESCRIPTOR_64B', 'BINNING',
'BINNING_PASS', 'BLEND_DST_MINUS_SRC', 'BLEND_DST_PLUS_SRC',
'BLEND_MAX_DST_SRC', 'BLEND_MIN_DST_SRC', 'BLEND_SRC_MINUS_DST',
'BLIT', 'BLIT2D', 'BLIT2DSCALE', 'BLIT_OP_COPY',
'BLIT_OP_COPY_2D', 'BLIT_OP_FILL', 'BLIT_OP_FILL_2D',
'BLIT_OP_SCALE', 'BLIT_OP_SCALE_2D', 'BRESENHAM', 'BUFFER',
'BUFFERS_IN_GMEM', 'BUFFERS_IN_SYSMEM', 'BYPASS', 'CACHE',
'CACHE_CLEAN', 'CACHE_FLUSH', 'CACHE_FLUSH7',
'CACHE_FLUSH_AND_INV_EVENT', 'CACHE_FLUSH_AND_INV_TS_EVENT',
'CACHE_FLUSH_TS', 'CACHE_INVALIDATE', 'CACHE_INVALIDATE7',
'CACHE_RESET', 'CCU_CACHE_SIZE_EIGHTH', 'CCU_CACHE_SIZE_FULL',
'CCU_CACHE_SIZE_HALF', 'CCU_CACHE_SIZE_QUARTER',
'CCU_CLEAN_COLOR', 'CCU_CLEAN_DEPTH', 'CCU_END_RESOLVE_GROUP',
'CCU_FLUSH_COLOR', 'CCU_FLUSH_DEPTH', 'CCU_INVALIDATE_COLOR',
'CCU_INVALIDATE_DEPTH', 'CCU_RESOLVE', 'CCU_RESOLVE_CLEAN',
'CONTEXT_DONE', 'CONTEXT_DONE_2D', 'COUNTER', 'CP_BLIT',
'CP_BLIT_0_OP__MASK', 'CP_BLIT_0_OP__SHIFT',
'CP_BLIT_1_SRC_X1__MASK', 'CP_BLIT_1_SRC_X1__SHIFT',
'CP_BLIT_1_SRC_Y1__MASK', 'CP_BLIT_1_SRC_Y1__SHIFT',
'CP_BLIT_2_SRC_X2__MASK', 'CP_BLIT_2_SRC_X2__SHIFT',
'CP_BLIT_2_SRC_Y2__MASK', 'CP_BLIT_2_SRC_Y2__SHIFT',
'CP_BLIT_3_DST_X1__MASK', 'CP_BLIT_3_DST_X1__SHIFT',
'CP_BLIT_3_DST_Y1__MASK', 'CP_BLIT_3_DST_Y1__SHIFT',
'CP_BLIT_4_DST_X2__MASK', 'CP_BLIT_4_DST_X2__SHIFT',
'CP_BLIT_4_DST_Y2__MASK', 'CP_BLIT_4_DST_Y2__SHIFT',
'CP_BOOTSTRAP_UCODE', 'CP_BV_BR_COUNT_OPS',
'CP_BV_BR_COUNT_OPS_0_OP__MASK', 'CP_BV_BR_COUNT_OPS_0_OP__SHIFT',
'CP_BV_BR_COUNT_OPS_1_BR_OFFSET__MASK',
'CP_BV_BR_COUNT_OPS_1_BR_OFFSET__SHIFT', 'CP_CCHE_INVALIDATE',
'CP_COMPUTE_CHECKPOINT',
'CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__MASK',
'CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__SHIFT',
'CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__MASK',
'CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__SHIFT',
'CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__MASK',
'CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__SHIFT',
'CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__MASK',
'CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__SHIFT',
'CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__MASK',
'CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__SHIFT', 'CP_COND_EXEC',
'CP_COND_EXEC_0_ADDR0_LO__MASK', 'CP_COND_EXEC_0_ADDR0_LO__SHIFT',
'CP_COND_EXEC_1_ADDR0_HI__MASK', 'CP_COND_EXEC_1_ADDR0_HI__SHIFT',
'CP_COND_EXEC_2_ADDR1_LO__MASK', 'CP_COND_EXEC_2_ADDR1_LO__SHIFT',
'CP_COND_EXEC_3_ADDR1_HI__MASK', 'CP_COND_EXEC_3_ADDR1_HI__SHIFT',
'CP_COND_EXEC_4_REF__MASK', 'CP_COND_EXEC_4_REF__SHIFT',
'CP_COND_EXEC_5_DWORDS__MASK', 'CP_COND_EXEC_5_DWORDS__SHIFT',
'CP_COND_INDIRECT_BUFFER_PFD', 'CP_COND_INDIRECT_BUFFER_PFE',
'CP_COND_REG_EXEC', 'CP_COND_REG_EXEC_0_BINNING',
'CP_COND_REG_EXEC_0_BR', 'CP_COND_REG_EXEC_0_BV',
'CP_COND_REG_EXEC_0_GMEM', 'CP_COND_REG_EXEC_0_LPAC',
'CP_COND_REG_EXEC_0_MODE__MASK', 'CP_COND_REG_EXEC_0_MODE__SHIFT',
'CP_COND_REG_EXEC_0_ONCHIP_MEM',
'CP_COND_REG_EXEC_0_PRED_BIT__MASK',
'CP_COND_REG_EXEC_0_PRED_BIT__SHIFT',
'CP_COND_REG_EXEC_0_REG0__MASK', 'CP_COND_REG_EXEC_0_REG0__SHIFT',
'CP_COND_REG_EXEC_0_SKIP_WAIT_FOR_ME',
'CP_COND_REG_EXEC_0_SYSMEM', 'CP_COND_REG_EXEC_2_DWORDS__MASK',
'CP_COND_REG_EXEC_2_DWORDS__SHIFT', 'CP_COND_WRITE',
'CP_COND_WRITE5', 'CP_COND_WRITE5_0_FUNCTION__MASK',
'CP_COND_WRITE5_0_FUNCTION__SHIFT', 'CP_COND_WRITE5_0_POLL__MASK',
'CP_COND_WRITE5_0_POLL__SHIFT', 'CP_COND_WRITE5_0_SIGNED_COMPARE',
'CP_COND_WRITE5_0_WRITE_MEMORY',
'CP_COND_WRITE5_1_POLL_ADDR_LO__MASK',
'CP_COND_WRITE5_1_POLL_ADDR_LO__SHIFT',
'CP_COND_WRITE5_2_POLL_ADDR_HI__MASK',
'CP_COND_WRITE5_2_POLL_ADDR_HI__SHIFT',
'CP_COND_WRITE5_3_REF__MASK', 'CP_COND_WRITE5_3_REF__SHIFT',
'CP_COND_WRITE5_4_MASK__MASK', 'CP_COND_WRITE5_4_MASK__SHIFT',
'CP_COND_WRITE5_5_WRITE_ADDR_LO__MASK',
'CP_COND_WRITE5_5_WRITE_ADDR_LO__SHIFT',
'CP_COND_WRITE5_6_WRITE_ADDR_HI__MASK',
'CP_COND_WRITE5_6_WRITE_ADDR_HI__SHIFT',
'CP_COND_WRITE5_7_WRITE_DATA__MASK',
'CP_COND_WRITE5_7_WRITE_DATA__SHIFT',
'CP_COND_WRITE_0_FUNCTION__MASK',
'CP_COND_WRITE_0_FUNCTION__SHIFT', 'CP_COND_WRITE_0_POLL_MEMORY',
'CP_COND_WRITE_0_WRITE_MEMORY', 'CP_COND_WRITE_1_POLL_ADDR__MASK',
'CP_COND_WRITE_1_POLL_ADDR__SHIFT', 'CP_COND_WRITE_2_REF__MASK',
'CP_COND_WRITE_2_REF__SHIFT', 'CP_COND_WRITE_3_MASK__MASK',
'CP_COND_WRITE_3_MASK__SHIFT', 'CP_COND_WRITE_4_WRITE_ADDR__MASK',
'CP_COND_WRITE_4_WRITE_ADDR__SHIFT',
'CP_COND_WRITE_5_WRITE_DATA__MASK',
'CP_COND_WRITE_5_WRITE_DATA__SHIFT', 'CP_CONTEXT_REG_BUNCH',
'CP_CONTEXT_REG_BUNCH2', 'CP_CONTEXT_SWITCH',
'CP_CONTEXT_SWITCH_YIELD', 'CP_CONTEXT_UPDATE',
'CP_DISPATCH_COMPUTE_1_X__MASK', 'CP_DISPATCH_COMPUTE_1_X__SHIFT',
'CP_DISPATCH_COMPUTE_2_Y__MASK', 'CP_DISPATCH_COMPUTE_2_Y__SHIFT',
'CP_DISPATCH_COMPUTE_3_Z__MASK', 'CP_DISPATCH_COMPUTE_3_Z__SHIFT',
'CP_DRAW_AUTO', 'CP_DRAW_AUTO_0_GS_ENABLE',
'CP_DRAW_AUTO_0_INDEX_SIZE__MASK',
'CP_DRAW_AUTO_0_INDEX_SIZE__SHIFT',
'CP_DRAW_AUTO_0_PATCH_TYPE__MASK',
'CP_DRAW_AUTO_0_PATCH_TYPE__SHIFT',
'CP_DRAW_AUTO_0_PRIM_TYPE__MASK',
'CP_DRAW_AUTO_0_PRIM_TYPE__SHIFT',
'CP_DRAW_AUTO_0_SOURCE_SELECT__MASK',
'CP_DRAW_AUTO_0_SOURCE_SELECT__SHIFT',
'CP_DRAW_AUTO_0_TESS_ENABLE', 'CP_DRAW_AUTO_0_VIS_CULL__MASK',
'CP_DRAW_AUTO_0_VIS_CULL__SHIFT',
'CP_DRAW_AUTO_1_NUM_INSTANCES__MASK',
'CP_DRAW_AUTO_1_NUM_INSTANCES__SHIFT',
'CP_DRAW_AUTO_4_NUM_VERTICES_OFFSET__MASK',
'CP_DRAW_AUTO_4_NUM_VERTICES_OFFSET__SHIFT',
'CP_DRAW_AUTO_5_STRIDE__MASK', 'CP_DRAW_AUTO_5_STRIDE__SHIFT',
'CP_DRAW_INDIRECT', 'CP_DRAW_INDIRECT_MULTI', 'CP_DRAW_INDX',
'CP_DRAW_INDX_0_VIZ_QUERY__MASK',
'CP_DRAW_INDX_0_VIZ_QUERY__SHIFT',
'CP_DRAW_INDX_1_INDEX_SIZE__MASK',
'CP_DRAW_INDX_1_INDEX_SIZE__SHIFT', 'CP_DRAW_INDX_1_NOT_EOP',
'CP_DRAW_INDX_1_NUM_INSTANCES__MASK',
'CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT',
'CP_DRAW_INDX_1_PRE_DRAW_INITIATOR_ENABLE',
'CP_DRAW_INDX_1_PRIM_TYPE__MASK',
'CP_DRAW_INDX_1_PRIM_TYPE__SHIFT', 'CP_DRAW_INDX_1_SMALL_INDEX',
'CP_DRAW_INDX_1_SOURCE_SELECT__MASK',
'CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT',
'CP_DRAW_INDX_1_VIS_CULL__MASK', 'CP_DRAW_INDX_1_VIS_CULL__SHIFT',
'CP_DRAW_INDX_2', 'CP_DRAW_INDX_2_0_VIZ_QUERY__MASK',
'CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT',
'CP_DRAW_INDX_2_1_INDEX_SIZE__MASK',
'CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT', 'CP_DRAW_INDX_2_1_NOT_EOP',
'CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK',
'CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT',
'CP_DRAW_INDX_2_1_PRE_DRAW_INITIATOR_ENABLE',
'CP_DRAW_INDX_2_1_PRIM_TYPE__MASK',
'CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT',
'CP_DRAW_INDX_2_1_SMALL_INDEX',
'CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK',
'CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT',
'CP_DRAW_INDX_2_1_VIS_CULL__MASK',
'CP_DRAW_INDX_2_1_VIS_CULL__SHIFT',
'CP_DRAW_INDX_2_2_NUM_INDICES__MASK',
'CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT', 'CP_DRAW_INDX_2_BIN',
'CP_DRAW_INDX_2_NUM_INDICES__MASK',
'CP_DRAW_INDX_2_NUM_INDICES__SHIFT',
'CP_DRAW_INDX_3_INDX_BASE__MASK',
'CP_DRAW_INDX_3_INDX_BASE__SHIFT',
'CP_DRAW_INDX_4_INDX_SIZE__MASK',
'CP_DRAW_INDX_4_INDX_SIZE__SHIFT', 'CP_DRAW_INDX_BIN',
'CP_DRAW_INDX_INDIRECT', 'CP_DRAW_INDX_OFFSET',
'CP_DRAW_INDX_OFFSET_0_GS_ENABLE',
'CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK',
'CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT',
'CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__MASK',
'CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__SHIFT',
'CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK',
'CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT',
'CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK',
'CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT',
'CP_DRAW_INDX_OFFSET_0_TESS_ENABLE',
'CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK',
'CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT',
'CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK',
'CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT',
'CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK',
'CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT',
'CP_DRAW_INDX_OFFSET_3_FIRST_INDX__MASK',
'CP_DRAW_INDX_OFFSET_3_FIRST_INDX__SHIFT',
'CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK',
'CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT',
'CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK',
'CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT',
'CP_DRAW_PRED_ENABLE_GLOBAL',
'CP_DRAW_PRED_ENABLE_GLOBAL_0_ENABLE',
'CP_DRAW_PRED_ENABLE_LOCAL', 'CP_DRAW_PRED_ENABLE_LOCAL_0_ENABLE',
'CP_DRAW_PRED_SET', 'CP_DRAW_PRED_SET_0_SRC__MASK',
'CP_DRAW_PRED_SET_0_SRC__SHIFT', 'CP_DRAW_PRED_SET_0_TEST__MASK',
'CP_DRAW_PRED_SET_0_TEST__SHIFT', 'CP_END_BIN', 'CP_EVENT_WRITE',
'CP_EVENT_WRITE7', 'CP_EVENT_WRITE7_0_CLEAR_LRZ_RESOURCE',
'CP_EVENT_WRITE7_0_CLEAR_RENDER_RESOURCE',
'CP_EVENT_WRITE7_0_EVENT__MASK', 'CP_EVENT_WRITE7_0_EVENT__SHIFT',
'CP_EVENT_WRITE7_0_INC_BR_COUNT',
'CP_EVENT_WRITE7_0_INC_BV_COUNT',
'CP_EVENT_WRITE7_0_SAMPLE_COUNT_END_OFFSET',
'CP_EVENT_WRITE7_0_WRITE_ACCUM_SAMPLE_COUNT_DIFF',
'CP_EVENT_WRITE7_0_WRITE_DST__MASK',
'CP_EVENT_WRITE7_0_WRITE_DST__SHIFT',
'CP_EVENT_WRITE7_0_WRITE_ENABLED',
'CP_EVENT_WRITE7_0_WRITE_SAMPLE_COUNT',
'CP_EVENT_WRITE7_0_WRITE_SRC__MASK',
'CP_EVENT_WRITE7_0_WRITE_SRC__SHIFT',
'CP_EVENT_WRITE_0_EVENT__MASK', 'CP_EVENT_WRITE_0_EVENT__SHIFT',
'CP_EVENT_WRITE_0_IRQ', 'CP_EVENT_WRITE_0_TIMESTAMP',
'CP_EVENT_WRITE_1_ADDR_0_LO__MASK',
'CP_EVENT_WRITE_1_ADDR_0_LO__SHIFT',
'CP_EVENT_WRITE_2_ADDR_0_HI__MASK',
'CP_EVENT_WRITE_2_ADDR_0_HI__SHIFT', 'CP_EVENT_WRITE_CFL',
'CP_EVENT_WRITE_SHD', 'CP_EVENT_WRITE_ZPD', 'CP_EXEC_CS',
'CP_EXEC_CS_1_NGROUPS_X__MASK', 'CP_EXEC_CS_1_NGROUPS_X__SHIFT',
'CP_EXEC_CS_2_NGROUPS_Y__MASK', 'CP_EXEC_CS_2_NGROUPS_Y__SHIFT',
'CP_EXEC_CS_3_NGROUPS_Z__MASK', 'CP_EXEC_CS_3_NGROUPS_Z__SHIFT',
'CP_EXEC_CS_INDIRECT', 'CP_FIXED_STRIDE_DRAW_TABLE',
'CP_FIXED_STRIDE_DRAW_TABLE_2_IB_SIZE__MASK',
'CP_FIXED_STRIDE_DRAW_TABLE_2_IB_SIZE__SHIFT',
'CP_FIXED_STRIDE_DRAW_TABLE_2_STRIDE__MASK',
'CP_FIXED_STRIDE_DRAW_TABLE_2_STRIDE__SHIFT',
'CP_FIXED_STRIDE_DRAW_TABLE_3_COUNT__MASK',
'CP_FIXED_STRIDE_DRAW_TABLE_3_COUNT__SHIFT',
'CP_GLOBAL_TIMESTAMP', 'CP_IM_LOAD', 'CP_IM_LOAD_IMMEDIATE',
'CP_IM_STORE', 'CP_INDIRECT_BUFFER', 'CP_INDIRECT_BUFFER_CHAIN',
'CP_INDIRECT_BUFFER_PFD', 'CP_INDIRECT_BUFFER_PFE',
'CP_INTERRUPT', 'CP_INVALIDATE_STATE', 'CP_LOAD_CONSTANT_CONTEXT',
'CP_LOAD_STATE', 'CP_LOAD_STATE4',
'CP_LOAD_STATE4_0_DST_OFF__MASK',
'CP_LOAD_STATE4_0_DST_OFF__SHIFT',
'CP_LOAD_STATE4_0_NUM_UNIT__MASK',
'CP_LOAD_STATE4_0_NUM_UNIT__SHIFT',
'CP_LOAD_STATE4_0_STATE_BLOCK__MASK',
'CP_LOAD_STATE4_0_STATE_BLOCK__SHIFT',
'CP_LOAD_STATE4_0_STATE_SRC__MASK',
'CP_LOAD_STATE4_0_STATE_SRC__SHIFT',
'CP_LOAD_STATE4_1_EXT_SRC_ADDR__MASK',
'CP_LOAD_STATE4_1_EXT_SRC_ADDR__SHIFT',
'CP_LOAD_STATE4_1_STATE_TYPE__MASK',
'CP_LOAD_STATE4_1_STATE_TYPE__SHIFT',
'CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__MASK',
'CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__SHIFT', 'CP_LOAD_STATE6',
'CP_LOAD_STATE6_0_DST_OFF__MASK',
'CP_LOAD_STATE6_0_DST_OFF__SHIFT',
'CP_LOAD_STATE6_0_NUM_UNIT__MASK',
'CP_LOAD_STATE6_0_NUM_UNIT__SHIFT',
'CP_LOAD_STATE6_0_STATE_BLOCK__MASK',
'CP_LOAD_STATE6_0_STATE_BLOCK__SHIFT',
'CP_LOAD_STATE6_0_STATE_SRC__MASK',
'CP_LOAD_STATE6_0_STATE_SRC__SHIFT',
'CP_LOAD_STATE6_0_STATE_TYPE__MASK',
'CP_LOAD_STATE6_0_STATE_TYPE__SHIFT',
'CP_LOAD_STATE6_1_EXT_SRC_ADDR__MASK',
'CP_LOAD_STATE6_1_EXT_SRC_ADDR__SHIFT',
'CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__MASK',
'CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__SHIFT', 'CP_LOAD_STATE6_FRAG',
'CP_LOAD_STATE6_GEOM', 'CP_LOAD_STATE_0_DST_OFF__MASK',
'CP_LOAD_STATE_0_DST_OFF__SHIFT',
'CP_LOAD_STATE_0_NUM_UNIT__MASK',
'CP_LOAD_STATE_0_NUM_UNIT__SHIFT',
'CP_LOAD_STATE_0_STATE_BLOCK__MASK',
'CP_LOAD_STATE_0_STATE_BLOCK__SHIFT',
'CP_LOAD_STATE_0_STATE_SRC__MASK',
'CP_LOAD_STATE_0_STATE_SRC__SHIFT',
'CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK',
'CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT',
'CP_LOAD_STATE_1_STATE_TYPE__MASK',
'CP_LOAD_STATE_1_STATE_TYPE__SHIFT', 'CP_LOCAL_TIMESTAMP',
'CP_MEMCPY', 'CP_MEMCPY_0_DWORDS__MASK',
'CP_MEMCPY_0_DWORDS__SHIFT', 'CP_MEMCPY_1_SRC_LO__MASK',
'CP_MEMCPY_1_SRC_LO__SHIFT', 'CP_MEMCPY_2_SRC_HI__MASK',
'CP_MEMCPY_2_SRC_HI__SHIFT', 'CP_MEMCPY_3_DST_LO__MASK',
'CP_MEMCPY_3_DST_LO__SHIFT', 'CP_MEMCPY_4_DST_HI__MASK',
'CP_MEMCPY_4_DST_HI__SHIFT', 'CP_MEM_TO_MEM',
'CP_MEM_TO_MEM_0_DOUBLE', 'CP_MEM_TO_MEM_0_NEG_A',
'CP_MEM_TO_MEM_0_NEG_B', 'CP_MEM_TO_MEM_0_NEG_C',
'CP_MEM_TO_MEM_0_UNK31', 'CP_MEM_TO_MEM_0_WAIT_FOR_MEM_WRITES',
'CP_MEM_TO_REG', 'CP_MEM_TO_REG_0_CNT__MASK',
'CP_MEM_TO_REG_0_CNT__SHIFT', 'CP_MEM_TO_REG_0_REG__MASK',
'CP_MEM_TO_REG_0_REG__SHIFT', 'CP_MEM_TO_REG_0_SHIFT_BY_2',
'CP_MEM_TO_REG_0_UNK31', 'CP_MEM_TO_REG_1_SRC__MASK',
'CP_MEM_TO_REG_1_SRC__SHIFT', 'CP_MEM_TO_REG_2_SRC_HI__MASK',
'CP_MEM_TO_REG_2_SRC_HI__SHIFT', 'CP_MEM_TO_SCRATCH_MEM',
'CP_MEM_TO_SCRATCH_MEM_0_CNT__MASK',
'CP_MEM_TO_SCRATCH_MEM_0_CNT__SHIFT',
'CP_MEM_TO_SCRATCH_MEM_1_OFFSET__MASK',
'CP_MEM_TO_SCRATCH_MEM_1_OFFSET__SHIFT',
'CP_MEM_TO_SCRATCH_MEM_2_SRC__MASK',
'CP_MEM_TO_SCRATCH_MEM_2_SRC__SHIFT',
'CP_MEM_TO_SCRATCH_MEM_3_SRC_HI__MASK',
'CP_MEM_TO_SCRATCH_MEM_3_SRC_HI__SHIFT', 'CP_MEM_WRITE',
'CP_MEM_WRITE_0_ADDR_LO__MASK', 'CP_MEM_WRITE_0_ADDR_LO__SHIFT',
'CP_MEM_WRITE_1_ADDR_HI__MASK', 'CP_MEM_WRITE_1_ADDR_HI__SHIFT',
'CP_MEM_WRITE_CNTR', 'CP_ME_INIT', 'CP_MODIFY_TIMESTAMP',
'CP_MODIFY_TIMESTAMP_0_ADD__MASK',
'CP_MODIFY_TIMESTAMP_0_ADD__SHIFT',
'CP_MODIFY_TIMESTAMP_0_OP__MASK',
'CP_MODIFY_TIMESTAMP_0_OP__SHIFT', 'CP_NOP',
'CP_PERFCOUNTER_ACTION',
'CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__MASK',
'CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__SHIFT',
'CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__MASK',
'CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__SHIFT', 'CP_PREEMPT_DISABLE',
'CP_PREEMPT_ENABLE', 'CP_PREEMPT_ENABLE_GLOBAL',
'CP_PREEMPT_ENABLE_LOCAL', 'CP_PREEMPT_TOKEN',
'CP_RECORD_PFP_TIMESTAMP', 'CP_REG_RMW',
'CP_REG_RMW_0_DST_REG__MASK', 'CP_REG_RMW_0_DST_REG__SHIFT',
'CP_REG_RMW_0_ROTATE__MASK', 'CP_REG_RMW_0_ROTATE__SHIFT',
'CP_REG_RMW_0_SRC0_IS_REG', 'CP_REG_RMW_0_SRC1_ADD',
'CP_REG_RMW_0_SRC1_IS_REG', 'CP_REG_RMW_1_SRC0__MASK',
'CP_REG_RMW_1_SRC0__SHIFT', 'CP_REG_RMW_2_SRC1__MASK',
'CP_REG_RMW_2_SRC1__SHIFT', 'CP_REG_TEST', 'CP_REG_TO_MEM',
'CP_REG_TO_MEM_0_64B', 'CP_REG_TO_MEM_0_ACCUMULATE',
'CP_REG_TO_MEM_0_CNT__MASK', 'CP_REG_TO_MEM_0_CNT__SHIFT',
'CP_REG_TO_MEM_0_REG__MASK', 'CP_REG_TO_MEM_0_REG__SHIFT',
'CP_REG_TO_MEM_1_DEST__MASK', 'CP_REG_TO_MEM_1_DEST__SHIFT',
'CP_REG_TO_MEM_2_DEST_HI__MASK', 'CP_REG_TO_MEM_2_DEST_HI__SHIFT',
'CP_REG_TO_MEM_OFFSET_MEM', 'CP_REG_TO_MEM_OFFSET_MEM_0_64B',
'CP_REG_TO_MEM_OFFSET_MEM_0_ACCUMULATE',
'CP_REG_TO_MEM_OFFSET_MEM_0_CNT__MASK',
'CP_REG_TO_MEM_OFFSET_MEM_0_CNT__SHIFT',
'CP_REG_TO_MEM_OFFSET_MEM_0_REG__MASK',
'CP_REG_TO_MEM_OFFSET_MEM_0_REG__SHIFT',
'CP_REG_TO_MEM_OFFSET_MEM_1_DEST__MASK',
'CP_REG_TO_MEM_OFFSET_MEM_1_DEST__SHIFT',
'CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__MASK',
'CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__SHIFT',
'CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO__MASK',
'CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO__SHIFT',
'CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI__MASK',
'CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI__SHIFT',
'CP_REG_TO_MEM_OFFSET_REG', 'CP_REG_TO_MEM_OFFSET_REG_0_64B',
'CP_REG_TO_MEM_OFFSET_REG_0_ACCUMULATE',
'CP_REG_TO_MEM_OFFSET_REG_0_CNT__MASK',
'CP_REG_TO_MEM_OFFSET_REG_0_CNT__SHIFT',
'CP_REG_TO_MEM_OFFSET_REG_0_REG__MASK',
'CP_REG_TO_MEM_OFFSET_REG_0_REG__SHIFT',
'CP_REG_TO_MEM_OFFSET_REG_1_DEST__MASK',
'CP_REG_TO_MEM_OFFSET_REG_1_DEST__SHIFT',
'CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__MASK',
'CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__SHIFT',
'CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0_SCRATCH',
'CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__MASK',
'CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__SHIFT', 'CP_REG_TO_SCRATCH',
'CP_REG_TO_SCRATCH_0_CNT__MASK', 'CP_REG_TO_SCRATCH_0_CNT__SHIFT',
'CP_REG_TO_SCRATCH_0_REG__MASK', 'CP_REG_TO_SCRATCH_0_REG__SHIFT',
'CP_REG_TO_SCRATCH_0_SCRATCH__MASK',
'CP_REG_TO_SCRATCH_0_SCRATCH__SHIFT', 'CP_REG_WRITE',
'CP_REG_WRITE_0_TRACKER__MASK', 'CP_REG_WRITE_0_TRACKER__SHIFT',
'CP_REG_WR_NO_CTXT', 'CP_RESET_CONTEXT_STATE',
'CP_RESET_CONTEXT_STATE_0_CLEAR_GLOBAL_LOCAL_TS',
'CP_RESET_CONTEXT_STATE_0_CLEAR_ON_CHIP_TS',
'CP_RESET_CONTEXT_STATE_0_CLEAR_RESOURCE_TABLE',
'CP_RESOURCE_LIST', 'CP_RUN_OPENCL', 'CP_SCRATCH_TO_REG',
'CP_SCRATCH_TO_REG_0_CNT__MASK', 'CP_SCRATCH_TO_REG_0_CNT__SHIFT',
'CP_SCRATCH_TO_REG_0_REG__MASK', 'CP_SCRATCH_TO_REG_0_REG__SHIFT',
'CP_SCRATCH_TO_REG_0_SCRATCH__MASK',
'CP_SCRATCH_TO_REG_0_SCRATCH__SHIFT', 'CP_SCRATCH_TO_REG_0_UNK18',
'CP_SCRATCH_WRITE', 'CP_SCRATCH_WRITE_0_SCRATCH__MASK',
'CP_SCRATCH_WRITE_0_SCRATCH__SHIFT', 'CP_SET_BIN',
'CP_SET_BIN_1_X1__MASK', 'CP_SET_BIN_1_X1__SHIFT',
'CP_SET_BIN_1_Y1__MASK', 'CP_SET_BIN_1_Y1__SHIFT',
'CP_SET_BIN_2_X2__MASK', 'CP_SET_BIN_2_X2__SHIFT',
'CP_SET_BIN_2_Y2__MASK', 'CP_SET_BIN_2_Y2__SHIFT',
'CP_SET_BIN_DATA', 'CP_SET_BIN_DATA5',
'CP_SET_BIN_DATA5_0_VSC_N__MASK',
'CP_SET_BIN_DATA5_0_VSC_N__SHIFT',
'CP_SET_BIN_DATA5_0_VSC_SIZE__MASK',
'CP_SET_BIN_DATA5_0_VSC_SIZE__SHIFT',
'CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__MASK',
'CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__SHIFT',
'CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__MASK',
'CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__SHIFT',
'CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__MASK',
'CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__SHIFT',
'CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__MASK',
'CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__SHIFT',
'CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO__MASK',
'CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO__SHIFT',
'CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI__MASK',
'CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI__SHIFT',
'CP_SET_BIN_DATA5_OFFSET',
'CP_SET_BIN_DATA5_OFFSET_0_VSC_N__MASK',
'CP_SET_BIN_DATA5_OFFSET_0_VSC_N__SHIFT',
'CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__MASK',
'CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__SHIFT',
'CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET__MASK',
'CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET__SHIFT',
'CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET__MASK',
'CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET__SHIFT',
'CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET__MASK',
'CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET__SHIFT',
'CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK',
'CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT',
'CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK',
'CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT', 'CP_SET_BIN_MASK',
'CP_SET_BIN_SELECT', 'CP_SET_CONSTANT', 'CP_SET_CTXSWITCH_IB',
'CP_SET_CTXSWITCH_IB_0_ADDR_LO__MASK',
'CP_SET_CTXSWITCH_IB_0_ADDR_LO__SHIFT',
'CP_SET_CTXSWITCH_IB_1_ADDR_HI__MASK',
'CP_SET_CTXSWITCH_IB_1_ADDR_HI__SHIFT',
'CP_SET_CTXSWITCH_IB_2_DWORDS__MASK',
'CP_SET_CTXSWITCH_IB_2_DWORDS__SHIFT',
'CP_SET_CTXSWITCH_IB_2_TYPE__MASK',
'CP_SET_CTXSWITCH_IB_2_TYPE__SHIFT', 'CP_SET_DRAW_INIT_FLAGS',
'CP_SET_DRAW_STATE', 'CP_SET_DRAW_STATE__0_BINNING',
'CP_SET_DRAW_STATE__0_COUNT__MASK',
'CP_SET_DRAW_STATE__0_COUNT__SHIFT', 'CP_SET_DRAW_STATE__0_DIRTY',
'CP_SET_DRAW_STATE__0_DISABLE',
'CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS',
'CP_SET_DRAW_STATE__0_GMEM',
'CP_SET_DRAW_STATE__0_GROUP_ID__MASK',
'CP_SET_DRAW_STATE__0_GROUP_ID__SHIFT',
'CP_SET_DRAW_STATE__0_LOAD_IMMED', 'CP_SET_DRAW_STATE__0_SYSMEM',
'CP_SET_DRAW_STATE__1_ADDR_LO__MASK',
'CP_SET_DRAW_STATE__1_ADDR_LO__SHIFT',
'CP_SET_DRAW_STATE__2_ADDR_HI__MASK',
'CP_SET_DRAW_STATE__2_ADDR_HI__SHIFT', 'CP_SET_MARKER',
'CP_SET_MODE', 'CP_SET_PROTECTED_MODE', 'CP_SET_PSEUDO_REG',
'CP_SET_RENDER_MODE', 'CP_SET_RENDER_MODE_0_MODE__MASK',
'CP_SET_RENDER_MODE_0_MODE__SHIFT',
'CP_SET_RENDER_MODE_1_ADDR_0_LO__MASK',
'CP_SET_RENDER_MODE_1_ADDR_0_LO__SHIFT',
'CP_SET_RENDER_MODE_2_ADDR_0_HI__MASK',
'CP_SET_RENDER_MODE_2_ADDR_0_HI__SHIFT',
'CP_SET_RENDER_MODE_3_GMEM_ENABLE',
'CP_SET_RENDER_MODE_3_VSC_ENABLE',
'CP_SET_RENDER_MODE_5_ADDR_1_LEN__MASK',
'CP_SET_RENDER_MODE_5_ADDR_1_LEN__SHIFT',
'CP_SET_RENDER_MODE_6_ADDR_1_LO__MASK',
'CP_SET_RENDER_MODE_6_ADDR_1_LO__SHIFT',
'CP_SET_RENDER_MODE_7_ADDR_1_HI__MASK',
'CP_SET_RENDER_MODE_7_ADDR_1_HI__SHIFT', 'CP_SET_SECURE_MODE',
'CP_SET_SHADER_BASES', 'CP_SET_STATE', 'CP_SET_SUBDRAW_SIZE',
'CP_SET_THREAD_BOTH', 'CP_SET_THREAD_BR', 'CP_SET_THREAD_BV',
'CP_SET_UNK_BIN_DATA', 'CP_SET_VISIBILITY_OVERRIDE',
'CP_SKIP_IB2_ENABLE_GLOBAL', 'CP_SKIP_IB2_ENABLE_LOCAL',
'CP_SMMU_TABLE_UPDATE', 'CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__MASK',
'CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__SHIFT',
'CP_SMMU_TABLE_UPDATE_1_ASID__MASK',
'CP_SMMU_TABLE_UPDATE_1_ASID__SHIFT',
'CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__MASK',
'CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__SHIFT',
'CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__MASK',
'CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__SHIFT',
'CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__MASK',
'CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__SHIFT', 'CP_START_BIN',
'CP_TEST_TWO_MEMS', 'CP_THREAD_CONTROL',
'CP_THREAD_CONTROL_0_CONCURRENT_BIN_DISABLE',
'CP_THREAD_CONTROL_0_SYNC_THREADS',
'CP_THREAD_CONTROL_0_THREAD__MASK',
'CP_THREAD_CONTROL_0_THREAD__SHIFT', 'CP_TYPE0_PKT',
'CP_TYPE1_PKT', 'CP_TYPE2_PKT', 'CP_TYPE3_PKT', 'CP_TYPE4_PKT',
'CP_TYPE7_PKT', 'CP_VIZ_QUERY', 'CP_WAIT_FOR_IDLE',
'CP_WAIT_FOR_ME', 'CP_WAIT_IB_PFD_COMPLETE', 'CP_WAIT_MEM_GTE',
'CP_WAIT_MEM_GTE_0_RESERVED__MASK',
'CP_WAIT_MEM_GTE_0_RESERVED__SHIFT',
'CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__MASK',
'CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__SHIFT',
'CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__MASK',
'CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__SHIFT',
'CP_WAIT_MEM_GTE_3_REF__MASK', 'CP_WAIT_MEM_GTE_3_REF__SHIFT',
'CP_WAIT_MEM_WRITES', 'CP_WAIT_REG_EQ', 'CP_WAIT_REG_GTE',
'CP_WAIT_REG_MEM', 'CP_WAIT_REG_MEM_0_FUNCTION__MASK',
'CP_WAIT_REG_MEM_0_FUNCTION__SHIFT',
'CP_WAIT_REG_MEM_0_POLL__MASK', 'CP_WAIT_REG_MEM_0_POLL__SHIFT',
'CP_WAIT_REG_MEM_0_SIGNED_COMPARE',
'CP_WAIT_REG_MEM_0_WRITE_MEMORY',
'CP_WAIT_REG_MEM_1_POLL_ADDR_LO__MASK',
'CP_WAIT_REG_MEM_1_POLL_ADDR_LO__SHIFT',
'CP_WAIT_REG_MEM_2_POLL_ADDR_HI__MASK',
'CP_WAIT_REG_MEM_2_POLL_ADDR_HI__SHIFT',
'CP_WAIT_REG_MEM_3_REF__MASK', 'CP_WAIT_REG_MEM_3_REF__SHIFT',
'CP_WAIT_REG_MEM_4_MASK__MASK', 'CP_WAIT_REG_MEM_4_MASK__SHIFT',
'CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES__MASK',
'CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES__SHIFT', 'CP_WAIT_TIMESTAMP',
'CP_WAIT_TIMESTAMP_0_WAIT_DST__MASK',
'CP_WAIT_TIMESTAMP_0_WAIT_DST__SHIFT',
'CP_WAIT_TIMESTAMP_0_WAIT_VALUE_SRC__MASK',
'CP_WAIT_TIMESTAMP_0_WAIT_VALUE_SRC__SHIFT', 'CP_WAIT_TWO_REGS',
'CP_WAIT_TWO_REGS_0_REG0__MASK', 'CP_WAIT_TWO_REGS_0_REG0__SHIFT',
'CP_WAIT_TWO_REGS_1_REG1__MASK', 'CP_WAIT_TWO_REGS_1_REG1__SHIFT',
'CP_WAIT_TWO_REGS_2_REF__MASK', 'CP_WAIT_TWO_REGS_2_REF__SHIFT',
'CP_WAIT_UNTIL_READ', 'CP_WHERE_AM_I', 'CP_WIDE_REG_WRITE',
'CP_YIELD_ENABLE', 'CS_YALIGN_1', 'CS_YALIGN_2', 'CS_YALIGN_4',
'CS_YALIGN_8', 'DEPTH6_16', 'DEPTH6_24_8', 'DEPTH6_32',
'DEPTH6_NONE', 'DEPTHX_16', 'DEPTHX_24_8', 'DEPTHX_32',
'DIST_ALL_TO_RB0', 'DIST_SCREEN_COORD', 'DITHER_ALWAYS',
'DITHER_DISABLE', 'DITHER_IF_ALPHA_OFF', 'DI_FACE_BACKFACE_CULL',
'DI_FACE_CULL_FETCH', 'DI_FACE_CULL_NONE',
'DI_FACE_FRONTFACE_CULL', 'DI_PT_LINELIST', 'DI_PT_LINELOOP',
'DI_PT_LINESTRIP', 'DI_PT_LINESTRIP_ADJ', 'DI_PT_LINE_ADJ',
'DI_PT_NONE', 'DI_PT_PATCHES0', 'DI_PT_PATCHES1',
'DI_PT_PATCHES10', 'DI_PT_PATCHES11', 'DI_PT_PATCHES12',
'DI_PT_PATCHES13', 'DI_PT_PATCHES14', 'DI_PT_PATCHES15',
'DI_PT_PATCHES16', 'DI_PT_PATCHES17', 'DI_PT_PATCHES18',
'DI_PT_PATCHES19', 'DI_PT_PATCHES2', 'DI_PT_PATCHES20',
'DI_PT_PATCHES21', 'DI_PT_PATCHES22', 'DI_PT_PATCHES23',
'DI_PT_PATCHES24', 'DI_PT_PATCHES25', 'DI_PT_PATCHES26',
'DI_PT_PATCHES27', 'DI_PT_PATCHES28', 'DI_PT_PATCHES29',
'DI_PT_PATCHES3', 'DI_PT_PATCHES30', 'DI_PT_PATCHES31',
'DI_PT_PATCHES4', 'DI_PT_PATCHES5', 'DI_PT_PATCHES6',
'DI_PT_PATCHES7', 'DI_PT_PATCHES8', 'DI_PT_PATCHES9',
'DI_PT_POINTLIST', 'DI_PT_POINTLIST_PSIZE', 'DI_PT_RECTLIST',
'DI_PT_TRIFAN', 'DI_PT_TRILIST', 'DI_PT_TRISTRIP',
'DI_PT_TRISTRIP_ADJ', 'DI_PT_TRI_ADJ', 'DI_SRC_SEL_AUTO_INDEX',
'DI_SRC_SEL_AUTO_XFB', 'DI_SRC_SEL_DMA', 'DI_SRC_SEL_IMMEDIATE',
'DRAW_STRM_ADDRESS', 'DRAW_STRM_SIZE_ADDRESS', 'DUMMY_EVENT',
'END2D', 'ENDIAN_16IN32', 'ENDIAN_8IN128', 'ENDIAN_8IN16',
'ENDIAN_8IN32', 'ENDIAN_8IN64', 'ENDIAN_NONE', 'EQUAL_SPACING',
'EQ_0_PASS', 'EVEN_SPACING', 'EV_DST_ONCHIP',
'EV_DST_ONCHIP_CP_EVENT_WRITE7_1_ONCHIP_ADDR_0__MASK',
'EV_DST_ONCHIP_CP_EVENT_WRITE7_1_ONCHIP_ADDR_0__SHIFT',
'EV_DST_ONCHIP_CP_EVENT_WRITE7_3_PAYLOAD_0__MASK',
'EV_DST_ONCHIP_CP_EVENT_WRITE7_3_PAYLOAD_0__SHIFT',
'EV_DST_ONCHIP_CP_EVENT_WRITE7_4_PAYLOAD_1__MASK',
'EV_DST_ONCHIP_CP_EVENT_WRITE7_4_PAYLOAD_1__SHIFT', 'EV_DST_RAM',
'EV_DST_RAM_CP_EVENT_WRITE7_1_ADDR_0_LO__MASK',
'EV_DST_RAM_CP_EVENT_WRITE7_1_ADDR_0_LO__SHIFT',
'EV_DST_RAM_CP_EVENT_WRITE7_2_ADDR_0_HI__MASK',
'EV_DST_RAM_CP_EVENT_WRITE7_2_ADDR_0_HI__SHIFT',
'EV_DST_RAM_CP_EVENT_WRITE7_3_PAYLOAD_0__MASK',
'EV_DST_RAM_CP_EVENT_WRITE7_3_PAYLOAD_0__SHIFT',
'EV_DST_RAM_CP_EVENT_WRITE7_4_PAYLOAD_1__MASK',
'EV_DST_RAM_CP_EVENT_WRITE7_4_PAYLOAD_1__SHIFT',
'EV_WRITE_ALWAYSON', 'EV_WRITE_REGS_CONTENT',
'EV_WRITE_TIMESTAMP_SUM', 'EV_WRITE_USER_32B',
'EV_WRITE_USER_64B', 'FACENESS_FLUSH', 'FACTOR_CONSTANT_ALPHA',
'FACTOR_CONSTANT_COLOR', 'FACTOR_DST_ALPHA', 'FACTOR_DST_COLOR',
'FACTOR_ONE', 'FACTOR_ONE_MINUS_CONSTANT_ALPHA',
'FACTOR_ONE_MINUS_CONSTANT_COLOR', 'FACTOR_ONE_MINUS_DST_ALPHA',
'FACTOR_ONE_MINUS_DST_COLOR', 'FACTOR_ONE_MINUS_SRC1_ALPHA',
'FACTOR_ONE_MINUS_SRC1_COLOR', 'FACTOR_ONE_MINUS_SRC_ALPHA',
'FACTOR_ONE_MINUS_SRC_COLOR', 'FACTOR_SRC1_ALPHA',
'FACTOR_SRC1_COLOR', 'FACTOR_SRC_ALPHA',
'FACTOR_SRC_ALPHA_SATURATE', 'FACTOR_SRC_COLOR', 'FACTOR_ZERO',
'FLUSH_PER_OVERLAP', 'FLUSH_PER_OVERLAP_AND_OVERWRITE',
'FLUSH_SO_0', 'FLUSH_SO_1', 'FLUSH_SO_2', 'FLUSH_SO_3',
'FMT6_10_10_10_2_SINT', 'FMT6_10_10_10_2_SNORM',
'FMT6_10_10_10_2_UINT', 'FMT6_10_10_10_2_UNORM',
'FMT6_10_10_10_2_UNORM_DEST', 'FMT6_11_11_10_FLOAT',
'FMT6_16_16_16_16_FLOAT', 'FMT6_16_16_16_16_SINT',
'FMT6_16_16_16_16_SNORM', 'FMT6_16_16_16_16_UINT',
'FMT6_16_16_16_16_UNORM', 'FMT6_16_16_16_FLOAT',
'FMT6_16_16_16_SINT', 'FMT6_16_16_16_SNORM', 'FMT6_16_16_16_UINT',
'FMT6_16_16_16_UNORM', 'FMT6_16_16_FLOAT', 'FMT6_16_16_SINT',
'FMT6_16_16_SNORM', 'FMT6_16_16_UINT', 'FMT6_16_16_UNORM',
'FMT6_16_FLOAT', 'FMT6_16_SINT', 'FMT6_16_SNORM', 'FMT6_16_UINT',
'FMT6_16_UNORM', 'FMT6_1_5_5_5_UNORM', 'FMT6_32_32_32_32_FIXED',
'FMT6_32_32_32_32_FLOAT', 'FMT6_32_32_32_32_SINT',
'FMT6_32_32_32_32_SNORM', 'FMT6_32_32_32_32_UINT',
'FMT6_32_32_32_32_UNORM', 'FMT6_32_32_32_FIXED',
'FMT6_32_32_32_FLOAT', 'FMT6_32_32_32_SINT',
'FMT6_32_32_32_SNORM', 'FMT6_32_32_32_UINT',
'FMT6_32_32_32_UNORM', 'FMT6_32_32_FIXED', 'FMT6_32_32_FLOAT',
'FMT6_32_32_SINT', 'FMT6_32_32_SNORM', 'FMT6_32_32_UINT',
'FMT6_32_32_UNORM', 'FMT6_32_FIXED', 'FMT6_32_FLOAT',
'FMT6_32_SINT', 'FMT6_32_SNORM', 'FMT6_32_UINT', 'FMT6_32_UNORM',
'FMT6_4_4_4_4_UNORM', 'FMT6_5_5_5_1_UNORM', 'FMT6_5_6_5_UNORM',
'FMT6_8_8_8_8_SINT', 'FMT6_8_8_8_8_SNORM', 'FMT6_8_8_8_8_UINT',
'FMT6_8_8_8_8_UNORM', 'FMT6_8_8_8_SINT', 'FMT6_8_8_8_SNORM',
'FMT6_8_8_8_UINT', 'FMT6_8_8_8_UNORM', 'FMT6_8_8_8_X8_UNORM',
'FMT6_8_8_SINT', 'FMT6_8_8_SNORM', 'FMT6_8_8_UINT',
'FMT6_8_8_UNORM', 'FMT6_8_SINT', 'FMT6_8_SNORM', 'FMT6_8_UINT',
'FMT6_8_UNORM', 'FMT6_9_9_9_E5_FLOAT', 'FMT6_A8_UNORM',
'FMT6_ASTC_10x10', 'FMT6_ASTC_10x5', 'FMT6_ASTC_10x6',
'FMT6_ASTC_10x8', 'FMT6_ASTC_12x10', 'FMT6_ASTC_12x12',
'FMT6_ASTC_4x4', 'FMT6_ASTC_5x4', 'FMT6_ASTC_5x5',
'FMT6_ASTC_6x5', 'FMT6_ASTC_6x6', 'FMT6_ASTC_8x5',
'FMT6_ASTC_8x6', 'FMT6_ASTC_8x8', 'FMT6_BPTC', 'FMT6_BPTC_FLOAT',
'FMT6_BPTC_UFLOAT', 'FMT6_DXT1', 'FMT6_DXT3', 'FMT6_DXT5',
'FMT6_ETC1', 'FMT6_ETC2_R11_SNORM', 'FMT6_ETC2_R11_UNORM',
'FMT6_ETC2_RG11_SNORM', 'FMT6_ETC2_RG11_UNORM', 'FMT6_ETC2_RGB8',
'FMT6_ETC2_RGB8A1', 'FMT6_ETC2_RGBA8', 'FMT6_G8R8B8R8_422_UNORM',
'FMT6_L8_A8_UNORM', 'FMT6_NONE', 'FMT6_NV12_4R',
'FMT6_NV12_4R_UV', 'FMT6_NV12_4R_Y', 'FMT6_NV12_UV',
'FMT6_NV12_VU', 'FMT6_NV12_Y', 'FMT6_NV21', 'FMT6_P010',
'FMT6_P010_UV', 'FMT6_P010_Y', 'FMT6_R8G8R8B8_422_UNORM',
'FMT6_R8_G8B8_2PLANE_420_UNORM', 'FMT6_R8_G8_B8_3PLANE_420_UNORM',
'FMT6_RGTC1_SNORM', 'FMT6_RGTC1_UNORM', 'FMT6_RGTC2_SNORM',
'FMT6_RGTC2_UNORM', 'FMT6_TP10', 'FMT6_TP10_UV', 'FMT6_TP10_Y',
'FMT6_Z24_UINT_S8_UINT', 'FMT6_Z24_UNORM_S8_UINT',
'FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8', 'FOUR_QUADS',
'FRAGCOORD_CENTER', 'FRAGCOORD_SAMPLE', 'FUNC_ALWAYS',
'FUNC_EQUAL', 'FUNC_GEQUAL', 'FUNC_GREATER', 'FUNC_LEQUAL',
'FUNC_LESS', 'FUNC_NEVER', 'FUNC_NOTEQUAL', 'GMEM', 'HLSQ_FLUSH',
'IGNORE_VISIBILITY', 'INDEX4_SIZE_16_BIT', 'INDEX4_SIZE_32_BIT',
'INDEX4_SIZE_8_BIT', 'INDEX_SIZE_16_BIT', 'INDEX_SIZE_32_BIT',
'INDEX_SIZE_8_BIT', 'INDEX_SIZE_IGN', 'INDEX_SIZE_INVALID',
'INDIRECT_OP_INDEXED', 'INDIRECT_OP_INDIRECT_COUNT',
'INDIRECT_OP_INDIRECT_COUNT_INDEXED', 'INDIRECT_OP_NORMAL',
'INTERP_FLAT', 'INTERP_ONE', 'INTERP_SMOOTH', 'INTERP_ZERO',
'IN_CONST_PREFETCH', 'IN_GMU_INTERRUPT', 'IN_IB_END',
'IN_IB_PREFETCH_END', 'IN_INCR_UPDT_CONST', 'IN_INCR_UPDT_INSTR',
'IN_INCR_UPDT_STATE', 'IN_INSTR_MATCH', 'IN_INSTR_PREFETCH',
'IN_PREEMPT', 'IN_SUBBLK_PREFETCH', 'ISAMMODE_CL', 'ISAMMODE_GL',
'LABEL', 'LRZ_CLEAR', 'LRZ_DIR_GE', 'LRZ_DIR_INVALID',
'LRZ_DIR_LE', 'LRZ_FLIP_BUFFER', 'LRZ_FLUSH', 'LR_BT', 'LR_TB',
'MODIFY_TIMESTAMP_ADD_GLOBAL', 'MODIFY_TIMESTAMP_ADD_LOCAL',
'MODIFY_TIMESTAMP_CLEAR', 'MSAA_EIGHT', 'MSAA_FOUR', 'MSAA_ONE',
'MSAA_TWO', 'MULTI', 'NE_0_PASS', 'NON_PRIV_SAVE_ADDR',
'NON_SECURE_SAVE_ADDR', 'NO_FLUSH', 'ODD_SPACING',
'PC_CCU_FLUSH_COLOR_TS', 'PC_CCU_FLUSH_DEPTH_TS',
'PC_CCU_INVALIDATE_COLOR', 'PC_CCU_INVALIDATE_DEPTH',
'PC_CCU_RESOLVE_TS', 'PC_DRAW_LINES', 'PC_DRAW_POINTS',
'PC_DRAW_TRIANGLES', 'PERFCOUNTER_START', 'PERFCOUNTER_STOP',
'PERF_CCU_2D_RD_REQ', 'PERF_CCU_2D_WR_REQ',
'PERF_CCU_BUSY_CYCLES', 'PERF_CCU_COLOR_BLOCKS',
'PERF_CCU_COLOR_BLOCK_HIT', 'PERF_CCU_COLOR_READ_FLAG0_COUNT',
'PERF_CCU_COLOR_READ_FLAG1_COUNT',
'PERF_CCU_COLOR_READ_FLAG2_COUNT',
'PERF_CCU_COLOR_READ_FLAG3_COUNT',
'PERF_CCU_COLOR_READ_FLAG4_COUNT',
'PERF_CCU_COLOR_READ_FLAG5_COUNT',
'PERF_CCU_COLOR_READ_FLAG6_COUNT',
'PERF_CCU_COLOR_READ_FLAG8_COUNT', 'PERF_CCU_DEPTH_BLOCKS',
'PERF_CCU_DEPTH_BLOCK_HIT', 'PERF_CCU_DEPTH_READ_FLAG0_COUNT',
'PERF_CCU_DEPTH_READ_FLAG1_COUNT',
'PERF_CCU_DEPTH_READ_FLAG2_COUNT',
'PERF_CCU_DEPTH_READ_FLAG3_COUNT',
'PERF_CCU_DEPTH_READ_FLAG4_COUNT',
'PERF_CCU_DEPTH_READ_FLAG5_COUNT',
'PERF_CCU_DEPTH_READ_FLAG6_COUNT',
'PERF_CCU_DEPTH_READ_FLAG8_COUNT', 'PERF_CCU_GMEM_READ',
'PERF_CCU_GMEM_WRITE', 'PERF_CCU_PARTIAL_BLOCK_READ',
'PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN',
'PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN',
'PERF_CCU_STARVE_CYCLES_FLAG_RETURN',
'PERF_CMPDECMP_2D_BUSY_CYCLES', 'PERF_CMPDECMP_2D_OUTPUT_TRANS',
'PERF_CMPDECMP_2D_PIXELS', 'PERF_CMPDECMP_2D_RD_DATA',
'PERF_CMPDECMP_2D_REORDER_STARVE_CYCLES',
'PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ',
'PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN',
'PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR',
'PERF_CMPDECMP_2D_WR_DATA',
'PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT',
'PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT',
'PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT',
'PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT',
'PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT',
'PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT',
'PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT',
'PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT',
'PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT',
'PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT',
'PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT',
'PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT',
'PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT',
'PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT',
'PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT',
'PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT',
'PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT',
'PERF_CMPDECMP_FLAG_FETCH_CYCLES',
'PERF_CMPDECMP_FLAG_FETCH_SAMPLES',
'PERF_CMPDECMP_STALL_CYCLES_ARB',
'PERF_CMPDECMP_VBIF_LATENCY_CYCLES',
'PERF_CMPDECMP_VBIF_LATENCY_SAMPLES',
'PERF_CMPDECMP_VBIF_READ_DATA',
'PERF_CMPDECMP_VBIF_READ_DATA_CCU',
'PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0',
'PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1',
'PERF_CMPDECMP_VBIF_READ_REQUEST',
'PERF_CMPDECMP_VBIF_WRITE_DATA',
'PERF_CMPDECMP_VBIF_WRITE_DATA_CCU',
'PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE',
'PERF_CMPDECMP_VBIF_WRITE_REQUEST', 'PERF_CP_AHB_STALL_SQE_GMU',
'PERF_CP_AHB_STALL_SQE_RD_OTHER',
'PERF_CP_AHB_STALL_SQE_WR_OTHER',
'PERF_CP_AHB_WR_STALL_PRE_DRAWS', 'PERF_CP_ALWAYS_COUNT',
'PERF_CP_BUSY_CYCLES', 'PERF_CP_BUSY_GFX_CORE_IDLE',
'PERF_CP_CACHE_FLUSH', 'PERF_CP_CLUSTER0_EMPTY',
'PERF_CP_CLUSTER1_EMPTY', 'PERF_CP_CLUSTER2_EMPTY',
'PERF_CP_CLUSTER3_EMPTY', 'PERF_CP_CLUSTER4_EMPTY',
'PERF_CP_CLUSTER5_EMPTY', 'PERF_CP_CONTEXT_DONE',
'PERF_CP_DEAD_DRAWS_IN_BIN_RENDER', 'PERF_CP_LONG_PREEMPTIONS',
'PERF_CP_MEMORY_POOL_ABOVE_THRESH', 'PERF_CP_MEMORY_POOL_EMPTY',
'PERF_CP_MEMORY_POOL_SYNC_STALL', 'PERF_CP_MODE_SWITCH',
'PERF_CP_NUM_PREEMPTIONS', 'PERF_CP_PM4_DATA',
'PERF_CP_PM4_HEADERS', 'PERF_CP_PREDICATED_DRAWS_KILLED',
'PERF_CP_PREEMPTION_REACTION_DELAY',
'PERF_CP_PREEMPTION_SWITCH_IN_TIME',
'PERF_CP_PREEMPTION_SWITCH_OUT_TIME',
'PERF_CP_SQE_CTXT_REG_BUNCH_EXEC', 'PERF_CP_SQE_DRAW_EXEC',
'PERF_CP_SQE_EXEC_PROFILED', 'PERF_CP_SQE_IDLE',
'PERF_CP_SQE_INSTR_COUNTER', 'PERF_CP_SQE_I_CACHE_STARVE',
'PERF_CP_SQE_LOAD_STATE_EXEC', 'PERF_CP_SQE_MRB_STARVE',
'PERF_CP_SQE_PIPE_OUT_STALL', 'PERF_CP_SQE_PM4_STARVE_RB_IB',
'PERF_CP_SQE_PM4_STARVE_SDS', 'PERF_CP_SQE_PM4_WFI_STALL',
'PERF_CP_SQE_RRB_STARVE', 'PERF_CP_SQE_SAVE_SDS_STATE',
'PERF_CP_SQE_SYNC_STALL', 'PERF_CP_SQE_SYS_WFI_STALL',
'PERF_CP_SQE_T4_EXEC', 'PERF_CP_SQE_VSD_STARVE',
'PERF_CP_VBIF_READ_BEATS', 'PERF_CP_VBIF_WRITE_BEATS',
'PERF_CP_VSD_DECODE_STARVE', 'PERF_CP_ZPASS_DONE',
'PERF_HLSQ_BUSY_CYCLES', 'PERF_HLSQ_COMPUTE_DRAWCALLS',
'PERF_HLSQ_CS_INVOCATIONS',
'PERF_HLSQ_DRAW_MODE_SWITCH_VSFS_SYNC',
'PERF_HLSQ_DUAL_FS_PROG_ACTIVE', 'PERF_HLSQ_DUAL_VS_PROG_ACTIVE',
'PERF_HLSQ_FS_BATCH_COUNT_ZERO',
'PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING',
'PERF_HLSQ_FS_STAGE_1X_WAVES', 'PERF_HLSQ_FS_STAGE_2X_WAVES',
'PERF_HLSQ_PIXELS', 'PERF_HLSQ_QUADS',
'PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE',
'PERF_HLSQ_STALL_CYCLES_SP_STATE', 'PERF_HLSQ_STALL_CYCLES_UCHE',
'PERF_HLSQ_STALL_CYCLES_VPC', 'PERF_HLSQ_UCHE_LATENCY_COUNT',
'PERF_HLSQ_UCHE_LATENCY_CYCLES', 'PERF_HLSQ_VS_BATCH_COUNT_ZERO',
'PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE',
'PERF_HLSQ_WAVE_PENDING_NO_QUAD', 'PERF_LRZ_BUSY_CYCLES',
'PERF_LRZ_FEEDBACK_ACCEPT', 'PERF_LRZ_FEEDBACK_DISCARD',
'PERF_LRZ_FEEDBACK_STALL', 'PERF_LRZ_FULLY_COVERED_TILES',
'PERF_LRZ_FULL_8X8_TILES', 'PERF_LRZ_LRZ_READ',
'PERF_LRZ_LRZ_WRITE', 'PERF_LRZ_MERGE_CACHE_UPDATING',
'PERF_LRZ_PARTIAL_8X8_TILES', 'PERF_LRZ_PARTIAL_COVERED_TILES',
'PERF_LRZ_PRIM_KILLED_BY_LRZ', 'PERF_LRZ_PRIM_KILLED_BY_MASKGEN',
'PERF_LRZ_RAS_MASK_TRANS', 'PERF_LRZ_READ_LATENCY',
'PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH', 'PERF_LRZ_STALL_CYCLES_RB',
'PERF_LRZ_STALL_CYCLES_RB_BPLANE',
'PERF_LRZ_STALL_CYCLES_RB_ZPLANE', 'PERF_LRZ_STALL_CYCLES_UCHE',
'PERF_LRZ_STALL_CYCLES_VC', 'PERF_LRZ_STALL_CYCLES_VPC',
'PERF_LRZ_STALL_CYCLES_VSC', 'PERF_LRZ_STARVE_CYCLES_RAS',
'PERF_LRZ_TILE_KILLED', 'PERF_LRZ_TOTAL_PIXEL',
'PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ',
'PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ', 'PERF_PC_2D_DRAWCALLS',
'PERF_PC_3D_DRAWCALLS', 'PERF_PC_BUSY_CYCLES',
'PERF_PC_DEAD_PRIM', 'PERF_PC_DS_INVOCATIONS',
'PERF_PC_DS_PRIMITIVES', 'PERF_PC_GS_INVOCATIONS',
'PERF_PC_GS_PRIMITIVES', 'PERF_PC_HS_INVOCATIONS',
'PERF_PC_IA_PRIMITIVES', 'PERF_PC_IA_VERTICES',
'PERF_PC_INSTANCES', 'PERF_PC_LIVE_PRIM',
'PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS',
'PERF_PC_PASS1_TF_STALL_CYCLES', 'PERF_PC_STALL_CYCLES_TESS',
'PERF_PC_STALL_CYCLES_TSE', 'PERF_PC_STALL_CYCLES_TSE_ONLY',
'PERF_PC_STALL_CYCLES_UCHE', 'PERF_PC_STALL_CYCLES_VFD',
'PERF_PC_STALL_CYCLES_VPC', 'PERF_PC_STALL_CYCLES_VPC_ONLY',
'PERF_PC_STARVE_CYCLES_DI', 'PERF_PC_STARVE_CYCLES_FOR_INDEX',
'PERF_PC_STARVE_CYCLES_FOR_POSITION',
'PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR',
'PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM',
'PERF_PC_TESS_FACTOR_TRANS', 'PERF_PC_TESS_PC_UV_PATCHES',
'PERF_PC_TESS_PC_UV_TRANS', 'PERF_PC_TSE_TRANSACTION',
'PERF_PC_TSE_VERTEX', 'PERF_PC_VERTEX_HITS',
'PERF_PC_VIS_STREAMS_LOADED', 'PERF_PC_VPC_POS_DATA_TRANSACTION',
'PERF_PC_VPC_PRIMITIVES', 'PERF_PC_VS_INVOCATIONS',
'PERF_PC_WORKING_CYCLES', 'PERF_RAS_8X4_TILES', 'PERF_RAS_BLOCKS',
'PERF_RAS_BUSY_CYCLES', 'PERF_RAS_FULLY_COVERED_8X4_TILES',
'PERF_RAS_FULLY_COVERED_SUPER_TILES',
'PERF_RAS_LRZ_INTF_WORKING_CYCLES', 'PERF_RAS_MASKGEN_ACTIVE',
'PERF_RAS_PRIM_KILLED_INVISILBE', 'PERF_RAS_STALL_CYCLES_LRZ',
'PERF_RAS_STARVE_CYCLES_TSE', 'PERF_RAS_SUPERTILE_ACTIVE_CYCLES',
'PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES', 'PERF_RAS_SUPER_TILES',
'PERF_RBBM_ALWAYS_COUNT', 'PERF_RBBM_ALWAYS_ON',
'PERF_RBBM_COM_BUSY', 'PERF_RBBM_DCOM_BUSY',
'PERF_RBBM_HLSQ_BUSY', 'PERF_RBBM_PC_DCALL_BUSY',
'PERF_RBBM_PC_VSD_BUSY', 'PERF_RBBM_RAS_BUSY',
'PERF_RBBM_STATUS_MASKED', 'PERF_RBBM_TESS_BUSY',
'PERF_RBBM_TSE_BUSY', 'PERF_RBBM_UCHE_BUSY',
'PERF_RBBM_VBIF_BUSY', 'PERF_RBBM_VSC_BUSY',
'PERF_RB_2D_ALIVE_CYCLES', 'PERF_RB_2D_INPUT_TRANS',
'PERF_RB_2D_OUTPUT_RB_DST_TRANS',
'PERF_RB_2D_OUTPUT_RB_SRC_TRANS', 'PERF_RB_2D_STALL_CYCLES_A2D',
'PERF_RB_2D_STARVE_CYCLES_DST', 'PERF_RB_2D_STARVE_CYCLES_SP',
'PERF_RB_2D_STARVE_CYCLES_SRC', 'PERF_RB_2D_VALID_PIXELS',
'PERF_RB_3D_PIXELS', 'PERF_RB_BLENDED_FP16_COMPONENTS',
'PERF_RB_BLENDED_FP32_COMPONENTS',
'PERF_RB_BLENDED_FXP_COMPONENTS',
'PERF_RB_BLENDER_WORKING_CYCLES', 'PERF_RB_BUSY_CYCLES',
'PERF_RB_COLOR_PIX_TILES', 'PERF_RB_CPROC_WORKING_CYCLES',
'PERF_RB_C_READ', 'PERF_RB_C_WRITE', 'PERF_RB_EARLY_Z_ARB3_GRANT',
'PERF_RB_EARLY_Z_SKIP_GRANT', 'PERF_RB_HLSQ_ACTIVE',
'PERF_RB_LATE_Z_ARB3_GRANT', 'PERF_RB_PS_INVOCATIONS',
'PERF_RB_SAMPLER_WORKING_CYCLES', 'PERF_RB_STALL_CYCLES_CCU',
'PERF_RB_STALL_CYCLES_CCU_COLOR_READ',
'PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE',
'PERF_RB_STALL_CYCLES_CCU_DEPTH_READ',
'PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE',
'PERF_RB_STALL_CYCLES_FIFO0_FULL',
'PERF_RB_STALL_CYCLES_FIFO1_FULL',
'PERF_RB_STALL_CYCLES_FIFO2_FULL', 'PERF_RB_STALL_CYCLES_HLSQ',
'PERF_RB_STALL_CYCLES_VPC', 'PERF_RB_STARVE_CYCLES_BARY_PLANE',
'PERF_RB_STARVE_CYCLES_CCU', 'PERF_RB_STARVE_CYCLES_LRZ_TILE',
'PERF_RB_STARVE_CYCLES_SP', 'PERF_RB_STARVE_CYCLES_Z_PLANE',
'PERF_RB_S_FAIL', 'PERF_RB_TOTAL_PASS',
'PERF_RB_ZPROC_WORKING_CYCLES', 'PERF_RB_Z_FAIL',
'PERF_RB_Z_PASS', 'PERF_RB_Z_READ', 'PERF_RB_Z_WORKLOAD',
'PERF_RB_Z_WRITE', 'PERF_SP_ADDR_LOCK_COUNT',
'PERF_SP_ALU_WORKING_CYCLES', 'PERF_SP_ANY_EU_WORKING',
'PERF_SP_ANY_EU_WORKING_CS_STAGE',
'PERF_SP_ANY_EU_WORKING_FS_STAGE',
'PERF_SP_ANY_EU_WORKING_VS_STAGE', 'PERF_SP_BUSY_CYCLES',
'PERF_SP_CS_INSTRUCTIONS', 'PERF_SP_DISPATCHER_WORKING_CYCLES',
'PERF_SP_DS_INSTRUCTIONS', 'PERF_SP_EFU_WORKING_CYCLES',
'PERF_SP_EXECUTABLE_WAVES', 'PERF_SP_EXPORT_RB_TRANS',
'PERF_SP_EXPORT_VPC_TRANS', 'PERF_SP_FLOW_CONTROL_WORKING_CYCLES',
'PERF_SP_FS_INSTRUCTIONS', 'PERF_SP_FS_STAGE_BARY_INSTRUCTIONS',
'PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS',
'PERF_SP_FS_STAGE_DURATION_CYCLES',
'PERF_SP_FS_STAGE_EFU_INSTRUCTIONS',
'PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS',
'PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS',
'PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS',
'PERF_SP_FS_STAGE_TEX_INSTRUCTIONS',
'PERF_SP_FS_STAGE_WAVE_CYCLES', 'PERF_SP_FS_STAGE_WAVE_SAMPLES',
'PERF_SP_GM_ATOMICS', 'PERF_SP_GM_LOAD_INSTRUCTIONS',
'PERF_SP_GM_LOAD_LATENCY_CYCLES',
'PERF_SP_GM_LOAD_LATENCY_SAMPLES',
'PERF_SP_GM_STORE_INSTRUCTIONS', 'PERF_SP_GPR_READ',
'PERF_SP_GPR_READ_CONFLICT', 'PERF_SP_GPR_READ_PREFETCH',
'PERF_SP_GPR_WRITE', 'PERF_SP_GPR_WRITE_CONFLICT',
'PERF_SP_GS_INSTRUCTIONS', 'PERF_SP_HS_INSTRUCTIONS',
'PERF_SP_ICL1_MISSES', 'PERF_SP_ICL1_REQUESTS',
'PERF_SP_LM_ATOMICS', 'PERF_SP_LM_BANK_CONFLICTS',
'PERF_SP_LM_LOAD_INSTRUCTIONS', 'PERF_SP_LM_STORE_INSTRUCTIONS',
'PERF_SP_LM_WORKING_CYCLES',
'PERF_SP_LOAD_CONTROL_WORKING_CYCLES',
'PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP',
'PERF_SP_NON_EXECUTION_CYCLES', 'PERF_SP_NON_EXECUTION_LS_CYCLES',
'PERF_SP_PIXELS_KILLED', 'PERF_SP_SEQUENCER_WORKING_CYCLES',
'PERF_SP_STALL_CYCLES_RB', 'PERF_SP_STALL_CYCLES_TP',
'PERF_SP_STALL_CYCLES_UCHE', 'PERF_SP_STALL_CYCLES_VPC',
'PERF_SP_STARVE_CYCLES_HLSQ',
'PERF_SP_TEX_CONTROL_WORKING_CYCLES', 'PERF_SP_UCHE_READ_TRANS',
'PERF_SP_UCHE_WRITE_TRANS', 'PERF_SP_VS_INSTRUCTIONS',
'PERF_SP_VS_STAGE_DURATION_CYCLES',
'PERF_SP_VS_STAGE_EFU_INSTRUCTIONS',
'PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS',
'PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS',
'PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS',
'PERF_SP_VS_STAGE_TEX_INSTRUCTIONS',
'PERF_SP_VS_STAGE_WAVE_CYCLES', 'PERF_SP_VS_STAGE_WAVE_SAMPLES',
'PERF_SP_WAVE_CONTEXTS', 'PERF_SP_WAVE_CONTEXT_CYCLES',
'PERF_SP_WAVE_CTRL_CYCLES', 'PERF_SP_WAVE_EMIT_CYCLES',
'PERF_SP_WAVE_END_CYCLES', 'PERF_SP_WAVE_FETCH_CYCLES',
'PERF_SP_WAVE_IDLE_CYCLES', 'PERF_SP_WAVE_JOIN_CYCLES',
'PERF_SP_WAVE_LOAD_CYCLES', 'PERF_SP_WAVE_LONG_SYNC_CYCLES',
'PERF_SP_WAVE_NOP_CYCLES', 'PERF_SP_WAVE_SHORT_SYNC_CYCLES',
'PERF_SP_WAVE_WAIT_CYCLES', 'PERF_SP_WORKING_EU',
'PERF_SP_WORKING_EU_CS_STAGE', 'PERF_SP_WORKING_EU_FS_STAGE',
'PERF_SP_WORKING_EU_VS_STAGE', 'PERF_TESS_BUSY_CYCLES',
'PERF_TESS_STALL_CYCLES_PC', 'PERF_TESS_STARVE_CYCLES_PC',
'PERF_TESS_WORKING_CYCLES', 'PERF_TP_2D_FILTER_WORKLOAD_16BIT',
'PERF_TP_2D_FILTER_WORKLOAD_32BIT', 'PERF_TP_2D_OUTPUT_PIXELS',
'PERF_TP_2D_OUTPUT_PIXELS_BILINEAR',
'PERF_TP_2D_OUTPUT_PIXELS_POINT',
'PERF_TP_BACKEND_WORKING_CYCLES', 'PERF_TP_BUSY_CYCLES',
'PERF_TP_DIVERGENT_QUADS_RECEIVED',
'PERF_TP_FILTER_WORKLOAD_16BIT', 'PERF_TP_FILTER_WORKLOAD_32BIT',
'PERF_TP_FLAG_CACHE_MISSES', 'PERF_TP_FLAG_CACHE_REQUESTS',
'PERF_TP_FLAG_CACHE_REQUEST_LATENCY',
'PERF_TP_FLAG_CACHE_REQUEST_SAMPLES',
'PERF_TP_FLAG_CACHE_WORKING_CYCLES',
'PERF_TP_FRONTEND_WORKING_CYCLES',
'PERF_TP_L1_5_CACHE_WORKING_CYCLES',
'PERF_TP_L1_5_L2_COMPRESS_MISS', 'PERF_TP_L1_5_L2_COMPRESS_REQS',
'PERF_TP_L1_5_L2_REQUESTS', 'PERF_TP_L1_5_MISS_LATENCY_CYCLES',
'PERF_TP_L1_5_MISS_LATENCY_TRANS', 'PERF_TP_L1_BANK_CONFLICT',
'PERF_TP_L1_CACHELINE_MISSES', 'PERF_TP_L1_CACHELINE_REQUESTS',
'PERF_TP_L1_DATA_WRITE_WORKING_CYCLES',
'PERF_TP_L1_MISSES_ASTC_1TILE', 'PERF_TP_L1_MISSES_ASTC_2TILE',
'PERF_TP_L1_MISSES_ASTC_4TILE', 'PERF_TP_L1_TAG_WORKING_CYCLES',
'PERF_TP_LATENCY_CYCLES', 'PERF_TP_LATENCY_TRANS',
'PERF_TP_OUTPUT_PIXELS', 'PERF_TP_OUTPUT_PIXELS_ANISO',
'PERF_TP_OUTPUT_PIXELS_BILINEAR', 'PERF_TP_OUTPUT_PIXELS_MIP',
'PERF_TP_OUTPUT_PIXELS_POINT', 'PERF_TP_OUTPUT_PIXELS_ZERO_LOD',
'PERF_TP_PRE_L1_DECOM_WORKING_CYCLES',
'PERF_TP_PRT_NON_RESIDENT_EVENTS', 'PERF_TP_QUADS_1D',
'PERF_TP_QUADS_2D', 'PERF_TP_QUADS_3D', 'PERF_TP_QUADS_ARRAY',
'PERF_TP_QUADS_BUFFER', 'PERF_TP_QUADS_CONSTANT_MULTIPLIED',
'PERF_TP_QUADS_CUBE', 'PERF_TP_QUADS_GRADIENT',
'PERF_TP_QUADS_OFFSET', 'PERF_TP_QUADS_RECEIVED',
'PERF_TP_QUADS_SHADOW', 'PERF_TP_SP_TP_TRANS',
'PERF_TP_STALL_CYCLES_UCHE', 'PERF_TP_STARVE_CYCLES_SP',
'PERF_TP_STARVE_CYCLES_UCHE', 'PERF_TP_TPA2TPC_TRANS',
'PERF_TP_TP_SP_TRANS', 'PERF_TSE_2D_ALIVE_CYCLES',
'PERF_TSE_2D_INPUT_PRIM', 'PERF_TSE_BUSY_CYCLES',
'PERF_TSE_CINVOCATION', 'PERF_TSE_CLIPPED_PRIM',
'PERF_TSE_CLIPPING_CYCLES', 'PERF_TSE_CLIP_PLANES',
'PERF_TSE_CPRIMITIVES', 'PERF_TSE_FACENESS_CULLED_PRIM',
'PERF_TSE_INPUT_NULL_PRIM', 'PERF_TSE_INPUT_PRIM',
'PERF_TSE_OUTPUT_NULL_PRIM', 'PERF_TSE_OUTPUT_VISIBLE_PRIM',
'PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE',
'PERF_TSE_STALL_CYCLES_LRZ_ZPLANE', 'PERF_TSE_STALL_CYCLES_RAS',
'PERF_TSE_STARVE_CYCLES_PC', 'PERF_TSE_TRIVAL_REJ_PRIM',
'PERF_TSE_ZERO_AREA_PRIM', 'PERF_TSE_ZERO_PIXEL_PRIM',
'PERF_UCHE_BANK_REQ0', 'PERF_UCHE_BANK_REQ1',
'PERF_UCHE_BANK_REQ2', 'PERF_UCHE_BANK_REQ3',
'PERF_UCHE_BANK_REQ4', 'PERF_UCHE_BANK_REQ5',
'PERF_UCHE_BANK_REQ6', 'PERF_UCHE_BANK_REQ7',
'PERF_UCHE_BUSY_CYCLES', 'PERF_UCHE_DCMP_LATENCY_CYCLES',
'PERF_UCHE_DCMP_LATENCY_SAMPLES', 'PERF_UCHE_EVICTS',
'PERF_UCHE_GMEM_READ_BEATS', 'PERF_UCHE_RAM_READ_REQ',
'PERF_UCHE_RAM_WRITE_REQ', 'PERF_UCHE_READ_REQUESTS_HLSQ',
'PERF_UCHE_READ_REQUESTS_LRZ', 'PERF_UCHE_READ_REQUESTS_PC',
'PERF_UCHE_READ_REQUESTS_SP', 'PERF_UCHE_READ_REQUESTS_TP',
'PERF_UCHE_READ_REQUESTS_VFD', 'PERF_UCHE_STALL_CYCLES_ARBITER',
'PERF_UCHE_TPH_EXT_FULL', 'PERF_UCHE_TPH_REF_FULL',
'PERF_UCHE_TPH_VICTIM_FULL', 'PERF_UCHE_VBIF_LATENCY_CYCLES',
'PERF_UCHE_VBIF_LATENCY_SAMPLES', 'PERF_UCHE_VBIF_READ_BEATS_CH0',
'PERF_UCHE_VBIF_READ_BEATS_CH1', 'PERF_UCHE_VBIF_READ_BEATS_HLSQ',
'PERF_UCHE_VBIF_READ_BEATS_LRZ', 'PERF_UCHE_VBIF_READ_BEATS_PC',
'PERF_UCHE_VBIF_READ_BEATS_SP', 'PERF_UCHE_VBIF_READ_BEATS_TP',
'PERF_UCHE_VBIF_READ_BEATS_VFD',
'PERF_UCHE_VBIF_STALL_WRITE_DATA', 'PERF_UCHE_WRITE_REQUESTS_LRZ',
'PERF_UCHE_WRITE_REQUESTS_SP', 'PERF_UCHE_WRITE_REQUESTS_VPC',
'PERF_UCHE_WRITE_REQUESTS_VSC', 'PERF_VFDP_STALL_CYCLES_VFD',
'PERF_VFDP_STALL_CYCLES_VFD_INDEX',
'PERF_VFDP_STALL_CYCLES_VFD_PROG', 'PERF_VFDP_STARVE_CYCLES_PC',
'PERF_VFDP_VS_STAGE_WAVES', 'PERF_VFD_ATTR_INFO_FIFO_FULL',
'PERF_VFD_BUSY_CYCLES', 'PERF_VFD_DECODED_ATTRIBUTE_BYTES',
'PERF_VFD_LOWER_SHADER_FIBERS', 'PERF_VFD_MODE_0_FIBERS',
'PERF_VFD_MODE_1_FIBERS', 'PERF_VFD_MODE_2_FIBERS',
'PERF_VFD_MODE_3_FIBERS', 'PERF_VFD_MODE_4_FIBERS',
'PERF_VFD_NUM_ATTRIBUTES', 'PERF_VFD_RBUFFER_FULL',
'PERF_VFD_STALL_CYCLES_SP_ATTR', 'PERF_VFD_STALL_CYCLES_SP_INFO',
'PERF_VFD_STALL_CYCLES_UCHE', 'PERF_VFD_STALL_CYCLES_VPC_ALLOC',
'PERF_VFD_STARVE_CYCLES_UCHE', 'PERF_VFD_TOTAL_VERTICES',
'PERF_VFD_UPPER_SHADER_FIBERS', 'PERF_VPC_BUSY_CYCLES',
'PERF_VPC_LM_FULL_WAIT_FOR_INTP_END', 'PERF_VPC_LM_TRANSACTION',
'PERF_VPC_LRZ_ASSIGN_PRIMITIVES', 'PERF_VPC_NUM_ATTR_REQ_LM',
'PERF_VPC_NUM_VPCRAM_READ_POS', 'PERF_VPC_NUM_VPCRAM_READ_SO',
'PERF_VPC_NUM_VPCRAM_WRITE', 'PERF_VPC_PC_PRIMITIVES',
'PERF_VPC_PS_BUSY_CYCLES', 'PERF_VPC_PS_WORKING_CYCLES',
'PERF_VPC_RB_VISIBLE_PRIMITIVES', 'PERF_VPC_SP_COMPONENTS',
'PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC',
'PERF_VPC_STALL_CYCLES_PC', 'PERF_VPC_STALL_CYCLES_SP_LM',
'PERF_VPC_STALL_CYCLES_UCHE', 'PERF_VPC_STALL_CYCLES_VFD_WACK',
'PERF_VPC_STALL_CYCLES_VPCRAM_POS', 'PERF_VPC_STARVE_CYCLES_LRZ',
'PERF_VPC_STARVE_CYCLES_RB', 'PERF_VPC_STARVE_CYCLES_SP',
'PERF_VPC_STREAMOUT_TRANSACTION', 'PERF_VPC_VPCRAM_FULL_CYCLES',
'PERF_VPC_VS_BUSY_CYCLES', 'PERF_VPC_VS_WORKING_CYCLES',
'PERF_VPC_WIT_FULL_CYCLES', 'PERF_VPC_WORKING_CYCLES',
'PERF_VSC_BUSY_CYCLES', 'PERF_VSC_EOT_NUM',
'PERF_VSC_INPUT_TILES', 'PERF_VSC_STALL_CYCLES_UCHE',
'PERF_VSC_WORKING_CYCLES', 'PIPE_BR_WAIT_FOR_BV',
'PIPE_BV_WAIT_FOR_BR', 'PIPE_CLEAR_BV_BR', 'PIPE_SET_BR_OFFSET',
'PKT4', 'POLL_MEMORY', 'POLL_ON_CHIP', 'POLL_REGISTER',
'POLL_SCRATCH', 'POLYMODE6_LINES', 'POLYMODE6_POINTS',
'POLYMODE6_TRIANGLES', 'PRED_SRC_MEM', 'PRED_TEST',
'PRED_TEST_CP_COND_REG_EXEC_1_DWORDS__MASK',
'PRED_TEST_CP_COND_REG_EXEC_1_DWORDS__SHIFT', 'PRIM_STRM_ADDRESS',
'PS_DEALLOC', 'PS_DONE_TS', 'PS_REPL_NONE', 'PS_REPL_ONE_MINUS_T',
'PS_REPL_S', 'PS_REPL_T', 'R2D_FLOAT16', 'R2D_FLOAT32',
'R2D_INT16', 'R2D_INT32', 'R2D_INT8', 'R2D_RAW', 'R2D_UNORM8',
'R2D_UNORM8_SRGB', 'RB_BT', 'RB_COMPUTE_PASS', 'RB_COPY_CLEAR',
'RB_COPY_DEPTH_STENCIL', 'RB_COPY_RESOLVE', 'RB_DONE_TS',
'RB_RENDERING_PASS', 'RB_RESOLVE_PASS', 'RB_SAVE_IB',
'RB_TILING_PASS', 'RECTANGULAR', 'REG_A4XX_CP_DRAW_INDIRECT_0',
'REG_A4XX_CP_DRAW_INDIRECT_1', 'REG_A4XX_CP_DRAW_INDX_INDIRECT_0',
'REG_A4XX_CP_DRAW_INDX_INDIRECT_1',
'REG_A4XX_CP_DRAW_INDX_INDIRECT_2',
'REG_A4XX_CP_DRAW_INDX_INDIRECT_3',
'REG_A4XX_CP_EXEC_CS_INDIRECT_0',
'REG_A4XX_CP_EXEC_CS_INDIRECT_1',
'REG_A4XX_CP_EXEC_CS_INDIRECT_2', 'REG_A5XX_CP_DRAW_INDIRECT_1',
'REG_A5XX_CP_DRAW_INDIRECT_2',
'REG_A5XX_CP_DRAW_INDIRECT_INDIRECT',
'REG_A5XX_CP_DRAW_INDX_INDIRECT_1',
'REG_A5XX_CP_DRAW_INDX_INDIRECT_2',
'REG_A5XX_CP_DRAW_INDX_INDIRECT_3',
'REG_A5XX_CP_DRAW_INDX_INDIRECT_4',
'REG_A5XX_CP_DRAW_INDX_INDIRECT_5',
'REG_A5XX_CP_DRAW_INDX_INDIRECT_INDIRECT',
'REG_A5XX_CP_DRAW_INDX_INDIRECT_INDX_BASE',
'REG_A5XX_CP_DRAW_INDX_OFFSET_4',
'REG_A5XX_CP_DRAW_INDX_OFFSET_5',
'REG_A5XX_CP_DRAW_INDX_OFFSET_6',
'REG_A5XX_CP_DRAW_INDX_OFFSET_INDX_BASE',
'REG_A5XX_CP_EXEC_CS_INDIRECT_1',
'REG_A5XX_CP_EXEC_CS_INDIRECT_2',
'REG_A5XX_CP_EXEC_CS_INDIRECT_3', 'REG_A6XX_CP_2D_EVENT_END',
'REG_A6XX_CP_2D_EVENT_START', 'REG_A6XX_CP_ADDR_MODE_CNTL',
'REG_A6XX_CP_AHB_CNTL', 'REG_A6XX_CP_ALWAYS_ON_COUNTER',
'REG_A6XX_CP_APERTURE_CNTL_CD', 'REG_A6XX_CP_APERTURE_CNTL_HOST',
'REG_A6XX_CP_APRIV_CNTL', 'REG_A6XX_CP_CHICKEN_DBG',
'REG_A6XX_CP_CONTEXT_SWITCH_CNTL',
'REG_A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR',
'REG_A6XX_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR',
'REG_A6XX_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR',
'REG_A6XX_CP_CONTEXT_SWITCH_SMMU_INFO',
'REG_A6XX_CP_CP2GMU_STATUS', 'REG_A6XX_CP_CRASH_DUMP_CNTL',
'REG_A6XX_CP_CRASH_DUMP_STATUS', 'REG_A6XX_CP_CRASH_SCRIPT_BASE',
'REG_A6XX_CP_DBG_ECO_CNTL', 'REG_A6XX_CP_DRAW_INDIRECT_MULTI_0',
'REG_A6XX_CP_DRAW_INDIRECT_MULTI_1',
'REG_A6XX_CP_DRAW_INDIRECT_MULTI_DRAW_COUNT',
'REG_A6XX_CP_DRAW_STATE_ADDR', 'REG_A6XX_CP_DRAW_STATE_DATA',
'REG_A6XX_CP_EVENT_END', 'REG_A6XX_CP_EVENT_START',
'REG_A6XX_CP_HW_FAULT', 'REG_A6XX_CP_IB1_BASE',
'REG_A6XX_CP_IB1_DWORDS', 'REG_A6XX_CP_IB1_REM_SIZE',
'REG_A6XX_CP_IB2_BASE', 'REG_A6XX_CP_IB2_DWORDS',
'REG_A6XX_CP_IB2_REM_SIZE', 'REG_A6XX_CP_INTERRUPT_STATUS',
'REG_A6XX_CP_LPAC_PROG_FIFO_SIZE', 'REG_A6XX_CP_LPAC_SQE_CNTL',
'REG_A6XX_CP_LPAC_SQE_INSTR_BASE',
'REG_A6XX_CP_MEM_POOL_DBG_ADDR', 'REG_A6XX_CP_MEM_POOL_DBG_DATA',
'REG_A6XX_CP_MEM_POOL_SIZE', 'REG_A6XX_CP_MISC_CNTL',
'REG_A6XX_CP_MRB_BASE', 'REG_A6XX_CP_MRB_DWORDS',
'REG_A6XX_CP_MRB_REM_SIZE', 'REG_A6XX_CP_PREEMPT_THRESHOLD',
'REG_A6XX_CP_PROTECT_CNTL', 'REG_A6XX_CP_PROTECT_STATUS',
'REG_A6XX_CP_RB_BASE', 'REG_A6XX_CP_RB_CNTL',
'REG_A6XX_CP_RB_RPTR', 'REG_A6XX_CP_RB_RPTR_ADDR',
'REG_A6XX_CP_RB_WPTR', 'REG_A6XX_CP_REG_TEST_0',
'REG_A6XX_CP_REG_TEST_PRED_MASK', 'REG_A6XX_CP_REG_TEST_PRED_VAL',
'REG_A6XX_CP_ROQ_AVAIL_IB1', 'REG_A6XX_CP_ROQ_AVAIL_IB2',
'REG_A6XX_CP_ROQ_AVAIL_MRB', 'REG_A6XX_CP_ROQ_AVAIL_RB',
'REG_A6XX_CP_ROQ_AVAIL_SDS', 'REG_A6XX_CP_ROQ_AVAIL_VSD',
'REG_A6XX_CP_ROQ_DBG_ADDR', 'REG_A6XX_CP_ROQ_DBG_DATA',
'REG_A6XX_CP_ROQ_IB1_STAT', 'REG_A6XX_CP_ROQ_IB2_STAT',
'REG_A6XX_CP_ROQ_MRB_STAT', 'REG_A6XX_CP_ROQ_RB_STAT',
'REG_A6XX_CP_ROQ_SDS_STAT', 'REG_A6XX_CP_ROQ_THRESHOLDS_1',
'REG_A6XX_CP_ROQ_THRESHOLDS_2', 'REG_A6XX_CP_ROQ_VSD_STAT',
'REG_A6XX_CP_SDS_BASE', 'REG_A6XX_CP_SDS_DWORDS',
'REG_A6XX_CP_SDS_REM_SIZE', 'REG_A6XX_CP_SET_MARKER_0',
'REG_A6XX_CP_SQE_CNTL', 'REG_A6XX_CP_SQE_INSTR_BASE',
'REG_A6XX_CP_SQE_STAT_ADDR', 'REG_A6XX_CP_SQE_STAT_DATA',
'REG_A6XX_CP_SQE_UCODE_DBG_ADDR',
'REG_A6XX_CP_SQE_UCODE_DBG_DATA', 'REG_A6XX_CP_STATUS_1',
'REG_A6XX_CP_VSD_BASE', 'REG_A6XX_CP_VSD_DWORDS',
'REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0',
'REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1',
'REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLM',
'REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLT',
'REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_0',
'REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_1',
'REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_2',
'REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_3',
'REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_0',
'REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_1',
'REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_2',
'REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_3',
'REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_A',
'REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_B',
'REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_C',
'REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_D',
'REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF1',
'REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF2',
'REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_0',
'REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_1',
'REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_0',
'REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_1',
'REG_A6XX_DBGC_CFG_DBGBUS_CNTLM',
'REG_A6XX_DBGC_CFG_DBGBUS_CNTLT',
'REG_A6XX_DBGC_CFG_DBGBUS_IVTL_0',
'REG_A6XX_DBGC_CFG_DBGBUS_IVTL_1',
'REG_A6XX_DBGC_CFG_DBGBUS_IVTL_2',
'REG_A6XX_DBGC_CFG_DBGBUS_IVTL_3',
'REG_A6XX_DBGC_CFG_DBGBUS_MASKL_0',
'REG_A6XX_DBGC_CFG_DBGBUS_MASKL_1',
'REG_A6XX_DBGC_CFG_DBGBUS_MASKL_2',
'REG_A6XX_DBGC_CFG_DBGBUS_MASKL_3',
'REG_A6XX_DBGC_CFG_DBGBUS_SEL_A',
'REG_A6XX_DBGC_CFG_DBGBUS_SEL_B',
'REG_A6XX_DBGC_CFG_DBGBUS_SEL_C',
'REG_A6XX_DBGC_CFG_DBGBUS_SEL_D',
'REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF1',
'REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF2', 'REG_A6XX_GBIF_HALT',
'REG_A6XX_GBIF_HALT_ACK', 'REG_A6XX_GBIF_PERF_CNT_HIGH0',
'REG_A6XX_GBIF_PERF_CNT_HIGH1', 'REG_A6XX_GBIF_PERF_CNT_HIGH2',
'REG_A6XX_GBIF_PERF_CNT_HIGH3', 'REG_A6XX_GBIF_PERF_CNT_LOW0',
'REG_A6XX_GBIF_PERF_CNT_LOW1', 'REG_A6XX_GBIF_PERF_CNT_LOW2',
'REG_A6XX_GBIF_PERF_CNT_LOW3', 'REG_A6XX_GBIF_PERF_CNT_SEL',
'REG_A6XX_GBIF_PERF_PWR_CNT_CLR', 'REG_A6XX_GBIF_PERF_PWR_CNT_EN',
'REG_A6XX_GBIF_PERF_PWR_CNT_SEL', 'REG_A6XX_GBIF_PWR_CNT_HIGH0',
'REG_A6XX_GBIF_PWR_CNT_HIGH1', 'REG_A6XX_GBIF_PWR_CNT_HIGH2',
'REG_A6XX_GBIF_PWR_CNT_LOW0', 'REG_A6XX_GBIF_PWR_CNT_LOW1',
'REG_A6XX_GBIF_PWR_CNT_LOW2', 'REG_A6XX_GBIF_QSB_SIDE0',
'REG_A6XX_GBIF_QSB_SIDE1', 'REG_A6XX_GBIF_QSB_SIDE2',
'REG_A6XX_GBIF_QSB_SIDE3', 'REG_A6XX_GBIF_SCACHE_CNTL0',
'REG_A6XX_GBIF_SCACHE_CNTL1', 'REG_A6XX_GRAS_2D_BLIT_CNTL',
'REG_A6XX_GRAS_2D_DST_BR', 'REG_A6XX_GRAS_2D_DST_TL',
'REG_A6XX_GRAS_2D_RESOLVE_CNTL_1',
'REG_A6XX_GRAS_2D_RESOLVE_CNTL_2', 'REG_A6XX_GRAS_2D_SRC_BR_X',
'REG_A6XX_GRAS_2D_SRC_BR_Y', 'REG_A6XX_GRAS_2D_SRC_TL_X',
'REG_A6XX_GRAS_2D_SRC_TL_Y', 'REG_A6XX_GRAS_2D_UNKNOWN_8407',
'REG_A6XX_GRAS_2D_UNKNOWN_8408', 'REG_A6XX_GRAS_2D_UNKNOWN_8409',
'REG_A6XX_GRAS_ADDR_MODE_CNTL', 'REG_A6XX_GRAS_BIN_CONTROL',
'REG_A6XX_GRAS_CL_CNTL', 'REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ',
'REG_A6XX_GRAS_CNTL', 'REG_A6XX_GRAS_DBG_ECO_CNTL',
'REG_A6XX_GRAS_DEST_MSAA_CNTL', 'REG_A6XX_GRAS_DS_CL_CNTL',
'REG_A6XX_GRAS_DS_LAYER_CNTL', 'REG_A6XX_GRAS_GS_CL_CNTL',
'REG_A6XX_GRAS_GS_LAYER_CNTL', 'REG_A6XX_GRAS_LRZ_BUFFER_BASE',
'REG_A6XX_GRAS_LRZ_BUFFER_PITCH', 'REG_A6XX_GRAS_LRZ_CNTL',
'REG_A6XX_GRAS_LRZ_DEPTH_VIEW',
'REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE',
'REG_A6XX_GRAS_LRZ_MRT_BUF_INFO_0',
'REG_A6XX_GRAS_LRZ_PS_INPUT_CNTL',
'REG_A6XX_GRAS_MAX_LAYER_INDEX', 'REG_A6XX_GRAS_RAS_MSAA_CNTL',
'REG_A6XX_GRAS_SAMPLE_CNTL', 'REG_A6XX_GRAS_SAMPLE_CONFIG',
'REG_A6XX_GRAS_SAMPLE_LOCATION_0',
'REG_A6XX_GRAS_SAMPLE_LOCATION_1', 'REG_A6XX_GRAS_SC_CNTL',
'REG_A6XX_GRAS_SC_WINDOW_SCISSOR_BR',
'REG_A6XX_GRAS_SC_WINDOW_SCISSOR_TL', 'REG_A6XX_GRAS_SU_CNTL',
'REG_A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL',
'REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO',
'REG_A6XX_GRAS_SU_DEPTH_CNTL',
'REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL',
'REG_A6XX_GRAS_SU_PATH_RENDERING_CNTL',
'REG_A6XX_GRAS_SU_POINT_MINMAX', 'REG_A6XX_GRAS_SU_POINT_SIZE',
'REG_A6XX_GRAS_SU_POLY_OFFSET_OFFSET',
'REG_A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP',
'REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE',
'REG_A6XX_GRAS_SU_STENCIL_CNTL', 'REG_A6XX_GRAS_UNKNOWN_80AF',
'REG_A6XX_GRAS_UNKNOWN_8110', 'REG_A6XX_GRAS_VS_CL_CNTL',
'REG_A6XX_GRAS_VS_LAYER_CNTL', 'REG_A6XX_HLSQ_2D_EVENT_CMD',
'REG_A6XX_HLSQ_ADDR_MODE_CNTL',
'REG_A6XX_HLSQ_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE',
'REG_A6XX_HLSQ_CONTROL_1_REG', 'REG_A6XX_HLSQ_CONTROL_2_REG',
'REG_A6XX_HLSQ_CONTROL_3_REG', 'REG_A6XX_HLSQ_CONTROL_4_REG',
'REG_A6XX_HLSQ_CONTROL_5_REG', 'REG_A6XX_HLSQ_CS_CNTL',
'REG_A6XX_HLSQ_CS_CNTL_0', 'REG_A6XX_HLSQ_CS_CNTL_1',
'REG_A6XX_HLSQ_CS_KERNEL_GROUP_X',
'REG_A6XX_HLSQ_CS_KERNEL_GROUP_Y',
'REG_A6XX_HLSQ_CS_KERNEL_GROUP_Z', 'REG_A6XX_HLSQ_CS_NDRANGE_0',
'REG_A6XX_HLSQ_CS_NDRANGE_1', 'REG_A6XX_HLSQ_CS_NDRANGE_2',
'REG_A6XX_HLSQ_CS_NDRANGE_3', 'REG_A6XX_HLSQ_CS_NDRANGE_4',
'REG_A6XX_HLSQ_CS_NDRANGE_5', 'REG_A6XX_HLSQ_CS_NDRANGE_6',
'REG_A6XX_HLSQ_CS_UNKNOWN_B9D0',
'REG_A6XX_HLSQ_DBG_AHB_READ_APERTURE',
'REG_A6XX_HLSQ_DBG_ECO_CNTL', 'REG_A6XX_HLSQ_DBG_READ_SEL',
'REG_A6XX_HLSQ_DISPATCH_CMD', 'REG_A6XX_HLSQ_DRAW_CMD',
'REG_A6XX_HLSQ_DS_CNTL', 'REG_A6XX_HLSQ_EVENT_CMD',
'REG_A6XX_HLSQ_FS_CNTL', 'REG_A6XX_HLSQ_FS_CNTL_0',
'REG_A6XX_HLSQ_GS_CNTL', 'REG_A6XX_HLSQ_HS_CNTL',
'REG_A6XX_HLSQ_INVALIDATE_CMD',
'REG_A6XX_HLSQ_LOAD_STATE_FRAG_CMD',
'REG_A6XX_HLSQ_LOAD_STATE_FRAG_DATA',
'REG_A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR',
'REG_A6XX_HLSQ_LOAD_STATE_GEOM_CMD',
'REG_A6XX_HLSQ_LOAD_STATE_GEOM_DATA',
'REG_A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR',
'REG_A6XX_HLSQ_SHARED_CONSTS', 'REG_A6XX_HLSQ_UNKNOWN_B981',
'REG_A6XX_HLSQ_UNKNOWN_BE00', 'REG_A6XX_HLSQ_UNKNOWN_BE01',
'REG_A6XX_HLSQ_UNKNOWN_BE08', 'REG_A6XX_HLSQ_VS_CNTL',
'REG_A6XX_PC_2D_EVENT_CMD', 'REG_A6XX_PC_ADDR_MODE_CNTL',
'REG_A6XX_PC_BIN_DRAW_STRM', 'REG_A6XX_PC_BIN_PRIM_STRM',
'REG_A6XX_PC_DBG_ECO_CNTL',
'REG_A6XX_PC_DGEN_SU_CONSERVATIVE_RAS_CNTL',
'REG_A6XX_PC_DISPATCH_CMD', 'REG_A6XX_PC_DRAW_CMD',
'REG_A6XX_PC_DRAW_FIRST_INDX', 'REG_A6XX_PC_DRAW_INDX_BASE',
'REG_A6XX_PC_DRAW_INITIATOR', 'REG_A6XX_PC_DRAW_MAX_INDICES',
'REG_A6XX_PC_DRAW_NUM_INDICES', 'REG_A6XX_PC_DRAW_NUM_INSTANCES',
'REG_A6XX_PC_DS_OUT_CNTL', 'REG_A6XX_PC_EVENT_CMD',
'REG_A6XX_PC_GS_OUT_CNTL', 'REG_A6XX_PC_HS_INPUT_SIZE',
'REG_A6XX_PC_HS_OUT_CNTL', 'REG_A6XX_PC_MARKER',
'REG_A6XX_PC_MODE_CNTL', 'REG_A6XX_PC_MULTIVIEW_CNTL',
'REG_A6XX_PC_MULTIVIEW_MASK', 'REG_A6XX_PC_POLYGON_MODE',
'REG_A6XX_PC_POWER_CNTL', 'REG_A6XX_PC_PRIMITIVE_CNTL_0',
'REG_A6XX_PC_PRIMITIVE_CNTL_5', 'REG_A6XX_PC_PRIMITIVE_CNTL_6',
'REG_A6XX_PC_PS_CNTL', 'REG_A6XX_PC_RASTER_CNTL',
'REG_A6XX_PC_RESTART_INDEX', 'REG_A6XX_PC_SO_STREAM_CNTL',
'REG_A6XX_PC_TESSFACTOR_ADDR', 'REG_A6XX_PC_TESS_CNTL',
'REG_A6XX_PC_TESS_NUM_VERTEX', 'REG_A6XX_PC_UNKNOWN_9E72',
'REG_A6XX_PC_VISIBILITY_OVERRIDE', 'REG_A6XX_PC_VSTREAM_CONTROL',
'REG_A6XX_PC_VS_OUT_CNTL', 'REG_A6XX_PDC_GPU_ENABLE_PDC',
'REG_A6XX_PDC_GPU_SEQ_MEM_0', 'REG_A6XX_PDC_GPU_SEQ_START_ADDR',
'REG_A6XX_PDC_GPU_TCS0_CMD0_ADDR',
'REG_A6XX_PDC_GPU_TCS0_CMD0_DATA',
'REG_A6XX_PDC_GPU_TCS0_CMD0_MSGID',
'REG_A6XX_PDC_GPU_TCS0_CMD_ENABLE_BANK',
'REG_A6XX_PDC_GPU_TCS0_CMD_WAIT_FOR_CMPL_BANK',
'REG_A6XX_PDC_GPU_TCS0_CONTROL',
'REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR',
'REG_A6XX_PDC_GPU_TCS1_CMD0_DATA',
'REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID',
'REG_A6XX_PDC_GPU_TCS1_CMD_ENABLE_BANK',
'REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK',
'REG_A6XX_PDC_GPU_TCS1_CONTROL',
'REG_A6XX_PDC_GPU_TCS2_CMD0_ADDR',
'REG_A6XX_PDC_GPU_TCS2_CMD0_DATA',
'REG_A6XX_PDC_GPU_TCS2_CMD0_MSGID',
'REG_A6XX_PDC_GPU_TCS2_CMD_ENABLE_BANK',
'REG_A6XX_PDC_GPU_TCS2_CMD_WAIT_FOR_CMPL_BANK',
'REG_A6XX_PDC_GPU_TCS2_CONTROL',
'REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR',
'REG_A6XX_PDC_GPU_TCS3_CMD0_DATA',
'REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID',
'REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK',
'REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK',
'REG_A6XX_PDC_GPU_TCS3_CONTROL',
'REG_A6XX_RBBM_BLOCK_SW_RESET_CMD',
'REG_A6XX_RBBM_BLOCK_SW_RESET_CMD2', 'REG_A6XX_RBBM_CLOCK_CNTL',
'REG_A6XX_RBBM_CLOCK_CNTL2_RAC', 'REG_A6XX_RBBM_CLOCK_CNTL2_RB0',
'REG_A6XX_RBBM_CLOCK_CNTL2_RB1', 'REG_A6XX_RBBM_CLOCK_CNTL2_RB2',
'REG_A6XX_RBBM_CLOCK_CNTL2_RB3', 'REG_A6XX_RBBM_CLOCK_CNTL2_SP0',
'REG_A6XX_RBBM_CLOCK_CNTL2_SP1', 'REG_A6XX_RBBM_CLOCK_CNTL2_SP2',
'REG_A6XX_RBBM_CLOCK_CNTL2_SP3', 'REG_A6XX_RBBM_CLOCK_CNTL2_TP0',
'REG_A6XX_RBBM_CLOCK_CNTL2_TP1', 'REG_A6XX_RBBM_CLOCK_CNTL2_TP2',
'REG_A6XX_RBBM_CLOCK_CNTL2_TP3', 'REG_A6XX_RBBM_CLOCK_CNTL2_UCHE',
'REG_A6XX_RBBM_CLOCK_CNTL3_TP0', 'REG_A6XX_RBBM_CLOCK_CNTL3_TP1',
'REG_A6XX_RBBM_CLOCK_CNTL3_TP2', 'REG_A6XX_RBBM_CLOCK_CNTL3_TP3',
'REG_A6XX_RBBM_CLOCK_CNTL3_UCHE', 'REG_A6XX_RBBM_CLOCK_CNTL4_TP0',
'REG_A6XX_RBBM_CLOCK_CNTL4_TP1', 'REG_A6XX_RBBM_CLOCK_CNTL4_TP2',
'REG_A6XX_RBBM_CLOCK_CNTL4_TP3', 'REG_A6XX_RBBM_CLOCK_CNTL4_UCHE',
'REG_A6XX_RBBM_CLOCK_CNTL_CCU0', 'REG_A6XX_RBBM_CLOCK_CNTL_CCU1',
'REG_A6XX_RBBM_CLOCK_CNTL_CCU2', 'REG_A6XX_RBBM_CLOCK_CNTL_CCU3',
'REG_A6XX_RBBM_CLOCK_CNTL_FCHE', 'REG_A6XX_RBBM_CLOCK_CNTL_GLC',
'REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX',
'REG_A6XX_RBBM_CLOCK_CNTL_MHUB', 'REG_A6XX_RBBM_CLOCK_CNTL_RAC',
'REG_A6XX_RBBM_CLOCK_CNTL_RB0', 'REG_A6XX_RBBM_CLOCK_CNTL_RB1',
'REG_A6XX_RBBM_CLOCK_CNTL_RB2', 'REG_A6XX_RBBM_CLOCK_CNTL_RB3',
'REG_A6XX_RBBM_CLOCK_CNTL_SP0', 'REG_A6XX_RBBM_CLOCK_CNTL_SP1',
'REG_A6XX_RBBM_CLOCK_CNTL_SP2', 'REG_A6XX_RBBM_CLOCK_CNTL_SP3',
'REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE',
'REG_A6XX_RBBM_CLOCK_CNTL_TP0', 'REG_A6XX_RBBM_CLOCK_CNTL_TP1',
'REG_A6XX_RBBM_CLOCK_CNTL_TP2', 'REG_A6XX_RBBM_CLOCK_CNTL_TP3',
'REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM',
'REG_A6XX_RBBM_CLOCK_CNTL_UCHE', 'REG_A6XX_RBBM_CLOCK_DELAY2_TP0',
'REG_A6XX_RBBM_CLOCK_DELAY2_TP1',
'REG_A6XX_RBBM_CLOCK_DELAY2_TP2',
'REG_A6XX_RBBM_CLOCK_DELAY2_TP3',
'REG_A6XX_RBBM_CLOCK_DELAY3_TP0',
'REG_A6XX_RBBM_CLOCK_DELAY3_TP1',
'REG_A6XX_RBBM_CLOCK_DELAY3_TP2',
'REG_A6XX_RBBM_CLOCK_DELAY3_TP3',
'REG_A6XX_RBBM_CLOCK_DELAY4_TP0',
'REG_A6XX_RBBM_CLOCK_DELAY4_TP1',
'REG_A6XX_RBBM_CLOCK_DELAY4_TP2',
'REG_A6XX_RBBM_CLOCK_DELAY4_TP3',
'REG_A6XX_RBBM_CLOCK_DELAY_FCHE', 'REG_A6XX_RBBM_CLOCK_DELAY_GLC',
'REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX',
'REG_A6XX_RBBM_CLOCK_DELAY_GPC', 'REG_A6XX_RBBM_CLOCK_DELAY_HLSQ',
'REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2',
'REG_A6XX_RBBM_CLOCK_DELAY_MHUB', 'REG_A6XX_RBBM_CLOCK_DELAY_RAC',
'REG_A6XX_RBBM_CLOCK_DELAY_SP0', 'REG_A6XX_RBBM_CLOCK_DELAY_SP1',
'REG_A6XX_RBBM_CLOCK_DELAY_SP2', 'REG_A6XX_RBBM_CLOCK_DELAY_SP3',
'REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE',
'REG_A6XX_RBBM_CLOCK_DELAY_TP0', 'REG_A6XX_RBBM_CLOCK_DELAY_TP1',
'REG_A6XX_RBBM_CLOCK_DELAY_TP2', 'REG_A6XX_RBBM_CLOCK_DELAY_TP3',
'REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM',
'REG_A6XX_RBBM_CLOCK_DELAY_UCHE', 'REG_A6XX_RBBM_CLOCK_DELAY_VFD',
'REG_A6XX_RBBM_CLOCK_HYST2_TP0', 'REG_A6XX_RBBM_CLOCK_HYST2_TP1',
'REG_A6XX_RBBM_CLOCK_HYST2_TP2', 'REG_A6XX_RBBM_CLOCK_HYST2_TP3',
'REG_A6XX_RBBM_CLOCK_HYST3_TP0', 'REG_A6XX_RBBM_CLOCK_HYST3_TP1',
'REG_A6XX_RBBM_CLOCK_HYST3_TP2', 'REG_A6XX_RBBM_CLOCK_HYST3_TP3',
'REG_A6XX_RBBM_CLOCK_HYST4_TP0', 'REG_A6XX_RBBM_CLOCK_HYST4_TP1',
'REG_A6XX_RBBM_CLOCK_HYST4_TP2', 'REG_A6XX_RBBM_CLOCK_HYST4_TP3',
'REG_A6XX_RBBM_CLOCK_HYST_FCHE', 'REG_A6XX_RBBM_CLOCK_HYST_GLC',
'REG_A6XX_RBBM_CLOCK_HYST_GMU_GX', 'REG_A6XX_RBBM_CLOCK_HYST_GPC',
'REG_A6XX_RBBM_CLOCK_HYST_HLSQ', 'REG_A6XX_RBBM_CLOCK_HYST_MHUB',
'REG_A6XX_RBBM_CLOCK_HYST_RAC',
'REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0',
'REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1',
'REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2',
'REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3',
'REG_A6XX_RBBM_CLOCK_HYST_SP0', 'REG_A6XX_RBBM_CLOCK_HYST_SP1',
'REG_A6XX_RBBM_CLOCK_HYST_SP2', 'REG_A6XX_RBBM_CLOCK_HYST_SP3',
'REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE',
'REG_A6XX_RBBM_CLOCK_HYST_TP0', 'REG_A6XX_RBBM_CLOCK_HYST_TP1',
'REG_A6XX_RBBM_CLOCK_HYST_TP2', 'REG_A6XX_RBBM_CLOCK_HYST_TP3',
'REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM',
'REG_A6XX_RBBM_CLOCK_HYST_UCHE', 'REG_A6XX_RBBM_CLOCK_HYST_VFD',
'REG_A6XX_RBBM_CLOCK_MODE_GPC', 'REG_A6XX_RBBM_CLOCK_MODE_HLSQ',
'REG_A6XX_RBBM_CLOCK_MODE_VFD',
'REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL', 'REG_A6XX_RBBM_GBIF_HALT',
'REG_A6XX_RBBM_GBIF_HALT_ACK', 'REG_A6XX_RBBM_GPR0_CNTL',
'REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL',
'REG_A6XX_RBBM_INT_0_MASK', 'REG_A6XX_RBBM_INT_0_STATUS',
'REG_A6XX_RBBM_INT_CLEAR_CMD', 'REG_A6XX_RBBM_ISDB_CNT',
'REG_A6XX_RBBM_LPAC_GBIF_CLIENT_QOS_CNTL',
'REG_A6XX_RBBM_PERFCTR_CNTL',
'REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED',
'REG_A6XX_RBBM_PERFCTR_LOAD_CMD0',
'REG_A6XX_RBBM_PERFCTR_LOAD_CMD1',
'REG_A6XX_RBBM_PERFCTR_LOAD_CMD2',
'REG_A6XX_RBBM_PERFCTR_LOAD_CMD3',
'REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_HI',
'REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_LO',
'REG_A6XX_RBBM_PERFCTR_SRAM_INIT_CMD',
'REG_A6XX_RBBM_PERFCTR_SRAM_INIT_STATUS',
'REG_A6XX_RBBM_PRIMCTR_0_HI', 'REG_A6XX_RBBM_PRIMCTR_0_LO',
'REG_A6XX_RBBM_PRIMCTR_10_HI', 'REG_A6XX_RBBM_PRIMCTR_10_LO',
'REG_A6XX_RBBM_PRIMCTR_1_HI', 'REG_A6XX_RBBM_PRIMCTR_1_LO',
'REG_A6XX_RBBM_PRIMCTR_2_HI', 'REG_A6XX_RBBM_PRIMCTR_2_LO',
'REG_A6XX_RBBM_PRIMCTR_3_HI', 'REG_A6XX_RBBM_PRIMCTR_3_LO',
'REG_A6XX_RBBM_PRIMCTR_4_HI', 'REG_A6XX_RBBM_PRIMCTR_4_LO',
'REG_A6XX_RBBM_PRIMCTR_5_HI', 'REG_A6XX_RBBM_PRIMCTR_5_LO',
'REG_A6XX_RBBM_PRIMCTR_6_HI', 'REG_A6XX_RBBM_PRIMCTR_6_LO',
'REG_A6XX_RBBM_PRIMCTR_7_HI', 'REG_A6XX_RBBM_PRIMCTR_7_LO',
'REG_A6XX_RBBM_PRIMCTR_8_HI', 'REG_A6XX_RBBM_PRIMCTR_8_LO',
'REG_A6XX_RBBM_PRIMCTR_9_HI', 'REG_A6XX_RBBM_PRIMCTR_9_LO',
'REG_A6XX_RBBM_RAC_THRESHOLD_CNT',
'REG_A6XX_RBBM_SECVID_TRUST_CNTL',
'REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL',
'REG_A6XX_RBBM_SECVID_TSB_CNTL',
'REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE',
'REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE',
'REG_A6XX_RBBM_SP_HYST_CNT', 'REG_A6XX_RBBM_STATUS',
'REG_A6XX_RBBM_STATUS1', 'REG_A6XX_RBBM_STATUS2',
'REG_A6XX_RBBM_STATUS3', 'REG_A6XX_RBBM_SW_RESET_CMD',
'REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL',
'REG_A6XX_RBBM_VBIF_GX_RESET_STATUS',
'REG_A6XX_RBBM_WAIT_FOR_GPU_IDLE_CMD', 'REG_A6XX_RB_2D_BLIT_CNTL',
'REG_A6XX_RB_2D_DST', 'REG_A6XX_RB_2D_DST_FLAGS',
'REG_A6XX_RB_2D_DST_FLAGS_PITCH',
'REG_A6XX_RB_2D_DST_FLAGS_PLANE',
'REG_A6XX_RB_2D_DST_FLAGS_PLANE_PITCH', 'REG_A6XX_RB_2D_DST_INFO',
'REG_A6XX_RB_2D_DST_PITCH', 'REG_A6XX_RB_2D_DST_PLANE1',
'REG_A6XX_RB_2D_DST_PLANE2', 'REG_A6XX_RB_2D_DST_PLANE_PITCH',
'REG_A6XX_RB_2D_SRC_SOLID_C0', 'REG_A6XX_RB_2D_SRC_SOLID_C1',
'REG_A6XX_RB_2D_SRC_SOLID_C2', 'REG_A6XX_RB_2D_SRC_SOLID_C3',
'REG_A6XX_RB_2D_UNKNOWN_8C01', 'REG_A6XX_RB_ADDR_MODE_CNTL',
'REG_A6XX_RB_ALPHA_CONTROL', 'REG_A6XX_RB_BIN_CONTROL',
'REG_A6XX_RB_BIN_CONTROL2', 'REG_A6XX_RB_BLEND_ALPHA_F32',
'REG_A6XX_RB_BLEND_BLUE_F32', 'REG_A6XX_RB_BLEND_CNTL',
'REG_A6XX_RB_BLEND_GREEN_F32', 'REG_A6XX_RB_BLEND_RED_F32',
'REG_A6XX_RB_BLIT_BASE_GMEM', 'REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0',
'REG_A6XX_RB_BLIT_CLEAR_COLOR_DW1',
'REG_A6XX_RB_BLIT_CLEAR_COLOR_DW2',
'REG_A6XX_RB_BLIT_CLEAR_COLOR_DW3', 'REG_A6XX_RB_BLIT_DST',
'REG_A6XX_RB_BLIT_DST_ARRAY_PITCH', 'REG_A6XX_RB_BLIT_DST_INFO',
'REG_A6XX_RB_BLIT_DST_PITCH', 'REG_A6XX_RB_BLIT_FLAG_DST',
'REG_A6XX_RB_BLIT_FLAG_DST_PITCH',
'REG_A6XX_RB_BLIT_GMEM_MSAA_CNTL', 'REG_A6XX_RB_BLIT_INFO',
'REG_A6XX_RB_BLIT_SCISSOR_BR', 'REG_A6XX_RB_BLIT_SCISSOR_TL',
'REG_A6XX_RB_CCU_CNTL', 'REG_A6XX_RB_CMP_DBG_ECO_CNTL',
'REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE',
'REG_A6XX_RB_DBG_ECO_CNTL',
'REG_A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH',
'REG_A6XX_RB_DEPTH_BUFFER_BASE',
'REG_A6XX_RB_DEPTH_BUFFER_BASE_GMEM',
'REG_A6XX_RB_DEPTH_BUFFER_INFO', 'REG_A6XX_RB_DEPTH_BUFFER_PITCH',
'REG_A6XX_RB_DEPTH_CNTL', 'REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE',
'REG_A6XX_RB_DEPTH_FLAG_BUFFER_PITCH',
'REG_A6XX_RB_DEPTH_PLANE_CNTL', 'REG_A6XX_RB_DEST_MSAA_CNTL',
'REG_A6XX_RB_DITHER_CNTL', 'REG_A6XX_RB_FS_OUTPUT_CNTL0',
'REG_A6XX_RB_FS_OUTPUT_CNTL1', 'REG_A6XX_RB_LRZ_CNTL',
'REG_A6XX_RB_NC_MODE_CNTL', 'REG_A6XX_RB_RAS_MSAA_CNTL',
'REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD',
'REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST',
'REG_A6XX_RB_RENDER_CNTL', 'REG_A6XX_RB_RENDER_COMPONENTS',
'REG_A6XX_RB_RENDER_CONTROL0', 'REG_A6XX_RB_RENDER_CONTROL1',
'REG_A6XX_RB_SAMPLE_CNTL', 'REG_A6XX_RB_SAMPLE_CONFIG',
'REG_A6XX_RB_SAMPLE_COUNT_ADDR',
'REG_A6XX_RB_SAMPLE_COUNT_CONTROL',
'REG_A6XX_RB_SAMPLE_LOCATION_0', 'REG_A6XX_RB_SAMPLE_LOCATION_1',
'REG_A6XX_RB_SRGB_CNTL', 'REG_A6XX_RB_STENCILMASK',
'REG_A6XX_RB_STENCILREF', 'REG_A6XX_RB_STENCILWRMASK',
'REG_A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH',
'REG_A6XX_RB_STENCIL_BUFFER_BASE',
'REG_A6XX_RB_STENCIL_BUFFER_BASE_GMEM',
'REG_A6XX_RB_STENCIL_BUFFER_PITCH', 'REG_A6XX_RB_STENCIL_CONTROL',
'REG_A6XX_RB_STENCIL_INFO', 'REG_A6XX_RB_UNKNOWN_8811',
'REG_A6XX_RB_UNKNOWN_8818', 'REG_A6XX_RB_UNKNOWN_8819',
'REG_A6XX_RB_UNKNOWN_881A', 'REG_A6XX_RB_UNKNOWN_881B',
'REG_A6XX_RB_UNKNOWN_881C', 'REG_A6XX_RB_UNKNOWN_881D',
'REG_A6XX_RB_UNKNOWN_881E', 'REG_A6XX_RB_UNKNOWN_88D0',
'REG_A6XX_RB_UNKNOWN_88F0', 'REG_A6XX_RB_UNKNOWN_88F4',
'REG_A6XX_RB_UNKNOWN_8A00', 'REG_A6XX_RB_UNKNOWN_8A10',
'REG_A6XX_RB_UNKNOWN_8A20', 'REG_A6XX_RB_UNKNOWN_8A30',
'REG_A6XX_RB_UNKNOWN_8E01', 'REG_A6XX_RB_UNKNOWN_8E51',
'REG_A6XX_RB_UNK_FLAG_BUFFER_BASE',
'REG_A6XX_RB_UNK_FLAG_BUFFER_PITCH', 'REG_A6XX_RB_WINDOW_OFFSET',
'REG_A6XX_RB_WINDOW_OFFSET2', 'REG_A6XX_RB_Z_BOUNDS_MAX',
'REG_A6XX_RB_Z_BOUNDS_MIN', 'REG_A6XX_RB_Z_CLAMP_MAX',
'REG_A6XX_RB_Z_CLAMP_MIN', 'REG_A6XX_SP_2D_DST_FORMAT',
'REG_A6XX_SP_ADDR_MODE_CNTL', 'REG_A6XX_SP_BLEND_CNTL',
'REG_A6XX_SP_CHICKEN_BITS',
'REG_A6XX_SP_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE',
'REG_A6XX_SP_CS_BRANCH_COND', 'REG_A6XX_SP_CS_CNTL_0',
'REG_A6XX_SP_CS_CNTL_1', 'REG_A6XX_SP_CS_CONFIG',
'REG_A6XX_SP_CS_CTRL_REG0', 'REG_A6XX_SP_CS_IBO',
'REG_A6XX_SP_CS_IBO_COUNT', 'REG_A6XX_SP_CS_INSTRLEN',
'REG_A6XX_SP_CS_OBJ_FIRST_EXEC_OFFSET',
'REG_A6XX_SP_CS_OBJ_START', 'REG_A6XX_SP_CS_PVT_MEM_ADDR',
'REG_A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET',
'REG_A6XX_SP_CS_PVT_MEM_PARAM', 'REG_A6XX_SP_CS_PVT_MEM_SIZE',
'REG_A6XX_SP_CS_TEX_CONST', 'REG_A6XX_SP_CS_TEX_COUNT',
'REG_A6XX_SP_CS_TEX_SAMP', 'REG_A6XX_SP_CS_UNKNOWN_A9B1',
'REG_A6XX_SP_DBG_ECO_CNTL', 'REG_A6XX_SP_DS_BRANCH_COND',
'REG_A6XX_SP_DS_CONFIG', 'REG_A6XX_SP_DS_CTRL_REG0',
'REG_A6XX_SP_DS_INSTRLEN', 'REG_A6XX_SP_DS_OBJ_FIRST_EXEC_OFFSET',
'REG_A6XX_SP_DS_OBJ_START', 'REG_A6XX_SP_DS_PRIMITIVE_CNTL',
'REG_A6XX_SP_DS_PVT_MEM_ADDR',
'REG_A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET',
'REG_A6XX_SP_DS_PVT_MEM_PARAM', 'REG_A6XX_SP_DS_PVT_MEM_SIZE',
'REG_A6XX_SP_DS_TEX_CONST', 'REG_A6XX_SP_DS_TEX_COUNT',
'REG_A6XX_SP_DS_TEX_SAMP', 'REG_A6XX_SP_FLOAT_CNTL',
'REG_A6XX_SP_FS_BRANCH_COND', 'REG_A6XX_SP_FS_CONFIG',
'REG_A6XX_SP_FS_CTRL_REG0', 'REG_A6XX_SP_FS_INSTRLEN',
'REG_A6XX_SP_FS_OBJ_FIRST_EXEC_OFFSET',
'REG_A6XX_SP_FS_OBJ_START', 'REG_A6XX_SP_FS_OUTPUT_CNTL0',
'REG_A6XX_SP_FS_OUTPUT_CNTL1', 'REG_A6XX_SP_FS_PREFETCH_CNTL',
'REG_A6XX_SP_FS_PVT_MEM_ADDR',
'REG_A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET',
'REG_A6XX_SP_FS_PVT_MEM_PARAM', 'REG_A6XX_SP_FS_PVT_MEM_SIZE',
'REG_A6XX_SP_FS_RENDER_COMPONENTS', 'REG_A6XX_SP_FS_TEX_CONST',
'REG_A6XX_SP_FS_TEX_COUNT', 'REG_A6XX_SP_FS_TEX_SAMP',
'REG_A6XX_SP_GS_BRANCH_COND', 'REG_A6XX_SP_GS_CONFIG',
'REG_A6XX_SP_GS_CTRL_REG0', 'REG_A6XX_SP_GS_INSTRLEN',
'REG_A6XX_SP_GS_OBJ_FIRST_EXEC_OFFSET',
'REG_A6XX_SP_GS_OBJ_START', 'REG_A6XX_SP_GS_PRIMITIVE_CNTL',
'REG_A6XX_SP_GS_PRIM_SIZE', 'REG_A6XX_SP_GS_PVT_MEM_ADDR',
'REG_A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET',
'REG_A6XX_SP_GS_PVT_MEM_PARAM', 'REG_A6XX_SP_GS_PVT_MEM_SIZE',
'REG_A6XX_SP_GS_TEX_CONST', 'REG_A6XX_SP_GS_TEX_COUNT',
'REG_A6XX_SP_GS_TEX_SAMP', 'REG_A6XX_SP_HS_BRANCH_COND',
'REG_A6XX_SP_HS_CONFIG', 'REG_A6XX_SP_HS_CTRL_REG0',
'REG_A6XX_SP_HS_INSTRLEN', 'REG_A6XX_SP_HS_OBJ_FIRST_EXEC_OFFSET',
'REG_A6XX_SP_HS_OBJ_START', 'REG_A6XX_SP_HS_PVT_MEM_ADDR',
'REG_A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET',
'REG_A6XX_SP_HS_PVT_MEM_PARAM', 'REG_A6XX_SP_HS_PVT_MEM_SIZE',
'REG_A6XX_SP_HS_TEX_CONST', 'REG_A6XX_SP_HS_TEX_COUNT',
'REG_A6XX_SP_HS_TEX_SAMP', 'REG_A6XX_SP_HS_WAVE_INPUT_SIZE',
'REG_A6XX_SP_IBO', 'REG_A6XX_SP_IBO_COUNT',
'REG_A6XX_SP_MODE_CONTROL', 'REG_A6XX_SP_NC_MODE_CNTL',
'REG_A6XX_SP_PERFCTR_ENABLE', 'REG_A6XX_SP_PS_2D_SRC',
'REG_A6XX_SP_PS_2D_SRC_FLAGS',
'REG_A6XX_SP_PS_2D_SRC_FLAGS_PITCH', 'REG_A6XX_SP_PS_2D_SRC_INFO',
'REG_A6XX_SP_PS_2D_SRC_PITCH', 'REG_A6XX_SP_PS_2D_SRC_PLANE1',
'REG_A6XX_SP_PS_2D_SRC_PLANE2',
'REG_A6XX_SP_PS_2D_SRC_PLANE_PITCH', 'REG_A6XX_SP_PS_2D_SRC_SIZE',
'REG_A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR',
'REG_A6XX_SP_PS_UNKNOWN_B4CD', 'REG_A6XX_SP_PS_UNKNOWN_B4CE',
'REG_A6XX_SP_PS_UNKNOWN_B4CF', 'REG_A6XX_SP_PS_UNKNOWN_B4D0',
'REG_A6XX_SP_SRGB_CNTL', 'REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR',
'REG_A6XX_SP_TP_DEST_MSAA_CNTL', 'REG_A6XX_SP_TP_MODE_CNTL',
'REG_A6XX_SP_TP_RAS_MSAA_CNTL', 'REG_A6XX_SP_TP_SAMPLE_CONFIG',
'REG_A6XX_SP_TP_SAMPLE_LOCATION_0',
'REG_A6XX_SP_TP_SAMPLE_LOCATION_1',
'REG_A6XX_SP_TP_WINDOW_OFFSET', 'REG_A6XX_SP_UNKNOWN_A9A8',
'REG_A6XX_SP_UNKNOWN_AAF2', 'REG_A6XX_SP_UNKNOWN_B182',
'REG_A6XX_SP_UNKNOWN_B183', 'REG_A6XX_SP_UNKNOWN_B190',
'REG_A6XX_SP_UNKNOWN_B191', 'REG_A6XX_SP_VS_BRANCH_COND',
'REG_A6XX_SP_VS_CONFIG', 'REG_A6XX_SP_VS_CTRL_REG0',
'REG_A6XX_SP_VS_INSTRLEN', 'REG_A6XX_SP_VS_OBJ_FIRST_EXEC_OFFSET',
'REG_A6XX_SP_VS_OBJ_START', 'REG_A6XX_SP_VS_PRIMITIVE_CNTL',
'REG_A6XX_SP_VS_PVT_MEM_ADDR',
'REG_A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET',
'REG_A6XX_SP_VS_PVT_MEM_PARAM', 'REG_A6XX_SP_VS_PVT_MEM_SIZE',
'REG_A6XX_SP_VS_TEX_CONST', 'REG_A6XX_SP_VS_TEX_COUNT',
'REG_A6XX_SP_VS_TEX_SAMP', 'REG_A6XX_SP_WINDOW_OFFSET',
'REG_A6XX_TEX_CONST_0', 'REG_A6XX_TEX_CONST_1',
'REG_A6XX_TEX_CONST_10', 'REG_A6XX_TEX_CONST_11',
'REG_A6XX_TEX_CONST_12', 'REG_A6XX_TEX_CONST_13',
'REG_A6XX_TEX_CONST_14', 'REG_A6XX_TEX_CONST_15',
'REG_A6XX_TEX_CONST_2', 'REG_A6XX_TEX_CONST_3',
'REG_A6XX_TEX_CONST_4', 'REG_A6XX_TEX_CONST_5',
'REG_A6XX_TEX_CONST_6', 'REG_A6XX_TEX_CONST_7',
'REG_A6XX_TEX_CONST_8', 'REG_A6XX_TEX_CONST_9',
'REG_A6XX_TEX_SAMP_0', 'REG_A6XX_TEX_SAMP_1',
'REG_A6XX_TEX_SAMP_2', 'REG_A6XX_TEX_SAMP_3',
'REG_A6XX_TPL1_ADDR_MODE_CNTL',
'REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0',
'REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1',
'REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2',
'REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3',
'REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4',
'REG_A6XX_TPL1_DBG_ECO_CNTL', 'REG_A6XX_TPL1_DBG_ECO_CNTL1',
'REG_A6XX_TPL1_NC_MODE_CNTL', 'REG_A6XX_TPL1_UNKNOWN_B605',
'REG_A6XX_UBO_0', 'REG_A6XX_UBO_1',
'REG_A6XX_UCHE_ADDR_MODE_CNTL', 'REG_A6XX_UCHE_CACHE_WAYS',
'REG_A6XX_UCHE_CLIENT_PF', 'REG_A6XX_UCHE_CMDQ_CONFIG',
'REG_A6XX_UCHE_FILTER_CNTL', 'REG_A6XX_UCHE_GBIF_GX_CONFIG',
'REG_A6XX_UCHE_GMEM_RANGE_MAX', 'REG_A6XX_UCHE_GMEM_RANGE_MIN',
'REG_A6XX_UCHE_MODE_CNTL', 'REG_A6XX_UCHE_TRAP_BASE',
'REG_A6XX_UCHE_UNKNOWN_0E12', 'REG_A6XX_UCHE_WRITE_RANGE_MAX',
'REG_A6XX_UCHE_WRITE_THRU_BASE', 'REG_A6XX_VBIF_CLKON',
'REG_A6XX_VBIF_GATE_OFF_WRREQ_EN', 'REG_A6XX_VBIF_PERF_CNT_HIGH0',
'REG_A6XX_VBIF_PERF_CNT_HIGH1', 'REG_A6XX_VBIF_PERF_CNT_HIGH2',
'REG_A6XX_VBIF_PERF_CNT_HIGH3', 'REG_A6XX_VBIF_PERF_CNT_LOW0',
'REG_A6XX_VBIF_PERF_CNT_LOW1', 'REG_A6XX_VBIF_PERF_CNT_LOW2',
'REG_A6XX_VBIF_PERF_CNT_LOW3', 'REG_A6XX_VBIF_PERF_CNT_SEL0',
'REG_A6XX_VBIF_PERF_CNT_SEL1', 'REG_A6XX_VBIF_PERF_CNT_SEL2',
'REG_A6XX_VBIF_PERF_CNT_SEL3', 'REG_A6XX_VBIF_PERF_PWR_CNT_EN0',
'REG_A6XX_VBIF_PERF_PWR_CNT_EN1',
'REG_A6XX_VBIF_PERF_PWR_CNT_EN2',
'REG_A6XX_VBIF_PERF_PWR_CNT_HIGH0',
'REG_A6XX_VBIF_PERF_PWR_CNT_HIGH1',
'REG_A6XX_VBIF_PERF_PWR_CNT_HIGH2',
'REG_A6XX_VBIF_PERF_PWR_CNT_LOW0',
'REG_A6XX_VBIF_PERF_PWR_CNT_LOW1',
'REG_A6XX_VBIF_PERF_PWR_CNT_LOW2',
'REG_A6XX_VBIF_TEST_BUS1_CTRL0', 'REG_A6XX_VBIF_TEST_BUS1_CTRL1',
'REG_A6XX_VBIF_TEST_BUS2_CTRL0', 'REG_A6XX_VBIF_TEST_BUS2_CTRL1',
'REG_A6XX_VBIF_TEST_BUS_OUT', 'REG_A6XX_VBIF_TEST_BUS_OUT_CTRL',
'REG_A6XX_VBIF_VERSION', 'REG_A6XX_VBIF_XIN_HALT_CTRL0',
'REG_A6XX_VBIF_XIN_HALT_CTRL1', 'REG_A6XX_VFD_ADDR_MODE_CNTL',
'REG_A6XX_VFD_ADD_OFFSET', 'REG_A6XX_VFD_CONTROL_0',
'REG_A6XX_VFD_CONTROL_1', 'REG_A6XX_VFD_CONTROL_2',
'REG_A6XX_VFD_CONTROL_3', 'REG_A6XX_VFD_CONTROL_4',
'REG_A6XX_VFD_CONTROL_5', 'REG_A6XX_VFD_CONTROL_6',
'REG_A6XX_VFD_INDEX_OFFSET', 'REG_A6XX_VFD_INSTANCE_START_OFFSET',
'REG_A6XX_VFD_MODE_CNTL', 'REG_A6XX_VFD_MULTIVIEW_CNTL',
'REG_A6XX_VFD_POWER_CNTL', 'REG_A6XX_VPC_ADDR_MODE_CNTL',
'REG_A6XX_VPC_CNTL_0', 'REG_A6XX_VPC_DBG_ECO_CNTL',
'REG_A6XX_VPC_DS_CLIP_CNTL', 'REG_A6XX_VPC_DS_CLIP_CNTL_V2',
'REG_A6XX_VPC_DS_LAYER_CNTL', 'REG_A6XX_VPC_DS_LAYER_CNTL_V2',
'REG_A6XX_VPC_DS_PACK', 'REG_A6XX_VPC_GS_CLIP_CNTL',
'REG_A6XX_VPC_GS_CLIP_CNTL_V2', 'REG_A6XX_VPC_GS_LAYER_CNTL',
'REG_A6XX_VPC_GS_LAYER_CNTL_V2', 'REG_A6XX_VPC_GS_PACK',
'REG_A6XX_VPC_GS_PARAM', 'REG_A6XX_VPC_POINT_COORD_INVERT',
'REG_A6XX_VPC_POLYGON_MODE', 'REG_A6XX_VPC_SO_CNTL',
'REG_A6XX_VPC_SO_DISABLE', 'REG_A6XX_VPC_SO_PROG',
'REG_A6XX_VPC_SO_STREAM_CNTL', 'REG_A6XX_VPC_SO_STREAM_COUNTS',
'REG_A6XX_VPC_UNKNOWN_9107', 'REG_A6XX_VPC_UNKNOWN_9210',
'REG_A6XX_VPC_UNKNOWN_9211', 'REG_A6XX_VPC_UNKNOWN_9300',
'REG_A6XX_VPC_UNKNOWN_9602', 'REG_A6XX_VPC_UNKNOWN_9603',
'REG_A6XX_VPC_VS_CLIP_CNTL', 'REG_A6XX_VPC_VS_CLIP_CNTL_V2',
'REG_A6XX_VPC_VS_LAYER_CNTL', 'REG_A6XX_VPC_VS_LAYER_CNTL_V2',
'REG_A6XX_VPC_VS_PACK', 'REG_A6XX_VSC_ADDR_MODE_CNTL',
'REG_A6XX_VSC_BIN_COUNT', 'REG_A6XX_VSC_BIN_SIZE',
'REG_A6XX_VSC_DBG_ECO_CNTL', 'REG_A6XX_VSC_DRAW_STRM_ADDRESS',
'REG_A6XX_VSC_DRAW_STRM_LIMIT', 'REG_A6XX_VSC_DRAW_STRM_PITCH',
'REG_A6XX_VSC_DRAW_STRM_SIZE_ADDRESS',
'REG_A6XX_VSC_PRIM_STRM_ADDRESS', 'REG_A6XX_VSC_PRIM_STRM_LIMIT',
'REG_A6XX_VSC_PRIM_STRM_PITCH', 'REG_A7XX_CP_APERTURE_CNTL_CD',
'REG_A7XX_CP_APERTURE_CNTL_HOST', 'REG_A7XX_CP_AQE_APRIV_CNTL',
'REG_A7XX_CP_AQE_INSTR_BASE_0', 'REG_A7XX_CP_AQE_INSTR_BASE_1',
'REG_A7XX_CP_AQE_ROQ_DBG_ADDR_0',
'REG_A7XX_CP_AQE_ROQ_DBG_ADDR_1',
'REG_A7XX_CP_AQE_ROQ_DBG_DATA_0',
'REG_A7XX_CP_AQE_ROQ_DBG_DATA_1', 'REG_A7XX_CP_AQE_STAT_ADDR_0',
'REG_A7XX_CP_AQE_STAT_ADDR_1', 'REG_A7XX_CP_AQE_STAT_DATA_0',
'REG_A7XX_CP_AQE_STAT_DATA_1', 'REG_A7XX_CP_AQE_UCODE_DBG_ADDR_0',
'REG_A7XX_CP_AQE_UCODE_DBG_ADDR_1',
'REG_A7XX_CP_AQE_UCODE_DBG_DATA_0',
'REG_A7XX_CP_AQE_UCODE_DBG_DATA_1', 'REG_A7XX_CP_BV_APRIV_CNTL',
'REG_A7XX_CP_BV_CHICKEN_DBG', 'REG_A7XX_CP_BV_DRAW_STATE_ADDR',
'REG_A7XX_CP_BV_DRAW_STATE_DATA', 'REG_A7XX_CP_BV_HW_FAULT',
'REG_A7XX_CP_BV_MEM_POOL_DBG_ADDR',
'REG_A7XX_CP_BV_MEM_POOL_DBG_DATA',
'REG_A7XX_CP_BV_PROTECT_STATUS', 'REG_A7XX_CP_BV_RB_RPTR_ADDR',
'REG_A7XX_CP_BV_ROQ_DBG_ADDR', 'REG_A7XX_CP_BV_ROQ_DBG_DATA',
'REG_A7XX_CP_BV_SQE_STAT_ADDR', 'REG_A7XX_CP_BV_SQE_STAT_DATA',
'REG_A7XX_CP_BV_SQE_UCODE_DBG_ADDR',
'REG_A7XX_CP_BV_SQE_UCODE_DBG_DATA',
'REG_A7XX_CP_CONTEXT_SWITCH_LEVEL_STATUS',
'REG_A7XX_CP_LPAC_APRIV_CNTL', 'REG_A7XX_CP_LPAC_DRAW_STATE_ADDR',
'REG_A7XX_CP_LPAC_DRAW_STATE_DATA',
'REG_A7XX_CP_LPAC_FIFO_DBG_ADDR',
'REG_A7XX_CP_LPAC_FIFO_DBG_DATA', 'REG_A7XX_CP_LPAC_ROQ_DBG_ADDR',
'REG_A7XX_CP_LPAC_ROQ_DBG_DATA',
'REG_A7XX_CP_RESOURCE_TBL_DBG_ADDR',
'REG_A7XX_CP_RESOURCE_TBL_DBG_DATA',
'REG_A7XX_CP_SQE_AC_STAT_ADDR', 'REG_A7XX_CP_SQE_AC_STAT_DATA',
'REG_A7XX_CP_SQE_AC_UCODE_DBG_ADDR',
'REG_A7XX_CP_SQE_AC_UCODE_DBG_DATA',
'REG_A7XX_CX_MISC_SW_FUSE_VALUE', 'REG_A7XX_CX_MISC_TCM_RET_CNTL',
'REG_A7XX_GRAS_LRZ_CLEAR_DEPTH_F32', 'REG_A7XX_GRAS_LRZ_CNTL2',
'REG_A7XX_GRAS_LRZ_DEPTH_BUFFER_INFO',
'REG_A7XX_GRAS_NC_MODE_CNTL', 'REG_A7XX_GRAS_SU_RENDER_CNTL',
'REG_A7XX_GRAS_UNKNOWN_8007', 'REG_A7XX_GRAS_UNKNOWN_8008',
'REG_A7XX_GRAS_UNKNOWN_8009', 'REG_A7XX_GRAS_UNKNOWN_800A',
'REG_A7XX_GRAS_UNKNOWN_800B', 'REG_A7XX_GRAS_UNKNOWN_800C',
'REG_A7XX_GRAS_UNKNOWN_80A7', 'REG_A7XX_GRAS_UNKNOWN_80F4',
'REG_A7XX_GRAS_UNKNOWN_80F5', 'REG_A7XX_GRAS_UNKNOWN_80F6',
'REG_A7XX_GRAS_UNKNOWN_80F8', 'REG_A7XX_GRAS_UNKNOWN_80F9',
'REG_A7XX_GRAS_UNKNOWN_80FA', 'REG_A7XX_GRAS_UNKNOWN_8120',
'REG_A7XX_GRAS_UNKNOWN_8121', 'REG_A7XX_HLSQ_CONTROL_1_REG',
'REG_A7XX_HLSQ_CONTROL_2_REG', 'REG_A7XX_HLSQ_CONTROL_3_REG',
'REG_A7XX_HLSQ_CONTROL_4_REG', 'REG_A7XX_HLSQ_CONTROL_5_REG',
'REG_A7XX_HLSQ_CS_CNTL', 'REG_A7XX_HLSQ_CS_CNTL_1',
'REG_A7XX_HLSQ_CS_KERNEL_GROUP_X',
'REG_A7XX_HLSQ_CS_KERNEL_GROUP_Y',
'REG_A7XX_HLSQ_CS_KERNEL_GROUP_Z', 'REG_A7XX_HLSQ_CS_LOCAL_SIZE',
'REG_A7XX_HLSQ_CS_NDRANGE_0', 'REG_A7XX_HLSQ_CS_NDRANGE_1',
'REG_A7XX_HLSQ_CS_NDRANGE_2', 'REG_A7XX_HLSQ_CS_NDRANGE_3',
'REG_A7XX_HLSQ_CS_NDRANGE_4', 'REG_A7XX_HLSQ_CS_NDRANGE_5',
'REG_A7XX_HLSQ_CS_NDRANGE_6', 'REG_A7XX_HLSQ_DISPATCH_CMD',
'REG_A7XX_HLSQ_DRAW_CMD', 'REG_A7XX_HLSQ_DS_CNTL',
'REG_A7XX_HLSQ_EVENT_CMD', 'REG_A7XX_HLSQ_FS_CNTL',
'REG_A7XX_HLSQ_FS_CNTL_0', 'REG_A7XX_HLSQ_FS_UNKNOWN_A9AA',
'REG_A7XX_HLSQ_GS_CNTL', 'REG_A7XX_HLSQ_HS_CNTL',
'REG_A7XX_HLSQ_INVALIDATE_CMD', 'REG_A7XX_HLSQ_UNKNOWN_A9AC',
'REG_A7XX_HLSQ_UNKNOWN_A9AD', 'REG_A7XX_HLSQ_UNKNOWN_A9AE',
'REG_A7XX_HLSQ_VS_CNTL', 'REG_A7XX_PC_ATTR_BUF_SIZE_GMEM',
'REG_A7XX_PC_POLYGON_MODE', 'REG_A7XX_PC_RASTER_CNTL',
'REG_A7XX_PC_RASTER_CNTL_V2', 'REG_A7XX_PC_TESSFACTOR_ADDR',
'REG_A7XX_PC_TESS_FACTOR_SIZE', 'REG_A7XX_PC_TESS_PARAM_SIZE',
'REG_A7XX_PC_UNKNOWN_9E24', 'REG_A7XX_RBBM_CGC_GLOBAL_LOAD_CMD',
'REG_A7XX_RBBM_CGC_P2S_STATUS', 'REG_A7XX_RBBM_CGC_P2S_TRIG_CMD',
'REG_A7XX_RBBM_CLOCK_CNTL_GLOBAL',
'REG_A7XX_RBBM_CLOCK_HYST2_VFD', 'REG_A7XX_RBBM_CLOCK_MODE2_GRAS',
'REG_A7XX_RBBM_CLOCK_MODE_BV_GPC',
'REG_A7XX_RBBM_CLOCK_MODE_BV_GRAS',
'REG_A7XX_RBBM_CLOCK_MODE_BV_LRZ',
'REG_A7XX_RBBM_CLOCK_MODE_BV_VFD', 'REG_A7XX_RBBM_CLOCK_MODE_CP',
'REG_A7XX_RBBM_GBIF_HALT', 'REG_A7XX_RBBM_GBIF_HALT_ACK',
'REG_A7XX_RBBM_INT_2_MASK', 'REG_A7XX_RBBM_NC_MODE_CNTL',
'REG_A7XX_RBBM_SECVID_TSB_STATUS',
'REG_A7XX_RBBM_SNAPSHOT_STATUS', 'REG_A7XX_RBBM_SW_FUSE_INT_MASK',
'REG_A7XX_RBBM_SW_FUSE_INT_STATUS', 'REG_A7XX_RB_BIN_CONTROL',
'REG_A7XX_RB_CCU_CNTL', 'REG_A7XX_RB_CCU_CNTL2',
'REG_A7XX_RB_DEPTH_BUFFER_INFO', 'REG_A7XX_RB_RENDER_CNTL',
'REG_A7XX_RB_STENCIL_INFO', 'REG_A7XX_RB_UNKNOWN_8812',
'REG_A7XX_RB_UNKNOWN_8899', 'REG_A7XX_RB_UNKNOWN_88E4',
'REG_A7XX_RB_UNKNOWN_88F5', 'REG_A7XX_RB_UNKNOWN_8C34',
'REG_A7XX_RB_UNKNOWN_8E06', 'REG_A7XX_RB_UNKNOWN_8E09',
'REG_A7XX_RB_UNKNOWN_8E79', 'REG_A7XX_SP_2D_DST_FORMAT',
'REG_A7XX_SP_AHB_READ_APERTURE', 'REG_A7XX_SP_CS_CNTL_1',
'REG_A7XX_SP_CS_UNKNOWN_A9BE', 'REG_A7XX_SP_CS_VGPR_CONFIG',
'REG_A7XX_SP_DBG_CNTL', 'REG_A7XX_SP_DS_VGPR_CONFIG',
'REG_A7XX_SP_FS_VGPR_CONFIG', 'REG_A7XX_SP_GS_VGPR_CONFIG',
'REG_A7XX_SP_HS_VGPR_CONFIG', 'REG_A7XX_SP_PS_2D_SRC',
'REG_A7XX_SP_PS_2D_SRC_FLAGS',
'REG_A7XX_SP_PS_2D_SRC_FLAGS_PITCH', 'REG_A7XX_SP_PS_2D_SRC_INFO',
'REG_A7XX_SP_PS_2D_SRC_PITCH', 'REG_A7XX_SP_PS_2D_SRC_PLANE1',
'REG_A7XX_SP_PS_2D_SRC_PLANE2',
'REG_A7XX_SP_PS_2D_SRC_PLANE_PITCH', 'REG_A7XX_SP_PS_2D_SRC_SIZE',
'REG_A7XX_SP_PS_2D_WINDOW_OFFSET',
'REG_A7XX_SP_PS_ALIASED_COMPONENTS',
'REG_A7XX_SP_PS_ALIASED_COMPONENTS_CONTROL',
'REG_A7XX_SP_PS_UNKNOWN_B2D2', 'REG_A7XX_SP_PS_UNKNOWN_B4CD',
'REG_A7XX_SP_PS_UNKNOWN_B4CE', 'REG_A7XX_SP_PS_UNKNOWN_B4CF',
'REG_A7XX_SP_PS_UNKNOWN_B4D0', 'REG_A7XX_SP_READ_SEL',
'REG_A7XX_SP_UNKNOWN_0CE2', 'REG_A7XX_SP_UNKNOWN_0CE4',
'REG_A7XX_SP_UNKNOWN_0CE6', 'REG_A7XX_SP_UNKNOWN_AB01',
'REG_A7XX_SP_UNKNOWN_AB02', 'REG_A7XX_SP_UNKNOWN_AB22',
'REG_A7XX_SP_UNKNOWN_AE06', 'REG_A7XX_SP_UNKNOWN_AE08',
'REG_A7XX_SP_UNKNOWN_AE09', 'REG_A7XX_SP_UNKNOWN_AE0A',
'REG_A7XX_SP_UNKNOWN_AE6A', 'REG_A7XX_SP_UNKNOWN_AE6B',
'REG_A7XX_SP_UNKNOWN_AE6C', 'REG_A7XX_SP_UNKNOWN_AE73',
'REG_A7XX_SP_UNKNOWN_B310', 'REG_A7XX_SP_VS_VGPR_CONFIG',
'REG_A7XX_SP_WINDOW_OFFSET',
'REG_A7XX_TPL1_BICUBIC_WEIGHTS_TABLE_0',
'REG_A7XX_TPL1_BICUBIC_WEIGHTS_TABLE_1',
'REG_A7XX_TPL1_BICUBIC_WEIGHTS_TABLE_2',
'REG_A7XX_TPL1_BICUBIC_WEIGHTS_TABLE_3',
'REG_A7XX_TPL1_BICUBIC_WEIGHTS_TABLE_4',
'REG_A7XX_UCHE_UNKNOWN_0E10', 'REG_A7XX_UCHE_UNKNOWN_0E11',
'REG_A7XX_VFD_UNKNOWN_A600', 'REG_A7XX_VPC_ATTR_BUF_BASE_GMEM',
'REG_A7XX_VPC_ATTR_BUF_SIZE_GMEM', 'REG_A7XX_VPC_MULTIVIEW_CNTL',
'REG_A7XX_VPC_MULTIVIEW_MASK', 'REG_A7XX_VPC_POLYGON_MODE2',
'REG_A7XX_VPC_PRIMITIVE_CNTL_0', 'REG_A7XX_VPC_PRIMITIVE_CNTL_5',
'REG_A7XX_VSC_UNKNOWN_0CD8', 'REG_A7XX_VSC_UNKNOWN_0D08',
'REG_AXXX_CP_BIN_MASK_HI', 'REG_AXXX_CP_BIN_MASK_LO',
'REG_AXXX_CP_BIN_SELECT_HI', 'REG_AXXX_CP_BIN_SELECT_LO',
'REG_AXXX_CP_CSQ_AVAIL', 'REG_AXXX_CP_CSQ_IB1_STAT',
'REG_AXXX_CP_CSQ_IB2_STAT', 'REG_AXXX_CP_CSQ_RB_STAT',
'REG_AXXX_CP_DEBUG', 'REG_AXXX_CP_IB1_BASE',
'REG_AXXX_CP_IB1_BUFSZ', 'REG_AXXX_CP_IB2_BASE',
'REG_AXXX_CP_IB2_BUFSZ', 'REG_AXXX_CP_INT_ACK',
'REG_AXXX_CP_INT_CNTL', 'REG_AXXX_CP_INT_STATUS',
'REG_AXXX_CP_MEQ_AVAIL', 'REG_AXXX_CP_MEQ_STAT',
'REG_AXXX_CP_MEQ_THRESHOLDS', 'REG_AXXX_CP_ME_CF_EVENT_ADDR',
'REG_AXXX_CP_ME_CF_EVENT_DATA', 'REG_AXXX_CP_ME_CF_EVENT_SRC',
'REG_AXXX_CP_ME_CNTL', 'REG_AXXX_CP_ME_NRT_ADDR',
'REG_AXXX_CP_ME_NRT_DATA', 'REG_AXXX_CP_ME_PS_EVENT_ADDR',
'REG_AXXX_CP_ME_PS_EVENT_ADDR_SWM',
'REG_AXXX_CP_ME_PS_EVENT_DATA',
'REG_AXXX_CP_ME_PS_EVENT_DATA_SWM', 'REG_AXXX_CP_ME_PS_EVENT_SRC',
'REG_AXXX_CP_ME_RAM_DATA', 'REG_AXXX_CP_ME_RAM_RADDR',
'REG_AXXX_CP_ME_RAM_WADDR', 'REG_AXXX_CP_ME_RDADDR',
'REG_AXXX_CP_ME_STATUS', 'REG_AXXX_CP_ME_VS_EVENT_ADDR',
'REG_AXXX_CP_ME_VS_EVENT_ADDR_SWM',
'REG_AXXX_CP_ME_VS_EVENT_DATA',
'REG_AXXX_CP_ME_VS_EVENT_DATA_SWM', 'REG_AXXX_CP_ME_VS_EVENT_SRC',
'REG_AXXX_CP_ME_VS_FETCH_DONE_ADDR',
'REG_AXXX_CP_ME_VS_FETCH_DONE_DATA',
'REG_AXXX_CP_ME_VS_FETCH_DONE_SRC', 'REG_AXXX_CP_MIU_TAG_STAT',
'REG_AXXX_CP_NON_PREFETCH_CNTRS', 'REG_AXXX_CP_QUEUE_THRESHOLDS',
'REG_AXXX_CP_RB_BASE', 'REG_AXXX_CP_RB_CNTL',
'REG_AXXX_CP_RB_RPTR', 'REG_AXXX_CP_RB_RPTR_ADDR',
'REG_AXXX_CP_RB_RPTR_WR', 'REG_AXXX_CP_RB_WPTR',
'REG_AXXX_CP_RB_WPTR_BASE', 'REG_AXXX_CP_RB_WPTR_DELAY',
'REG_AXXX_CP_SCRATCH_REG0', 'REG_AXXX_CP_SCRATCH_REG1',
'REG_AXXX_CP_SCRATCH_REG2', 'REG_AXXX_CP_SCRATCH_REG3',
'REG_AXXX_CP_SCRATCH_REG4', 'REG_AXXX_CP_SCRATCH_REG5',
'REG_AXXX_CP_SCRATCH_REG6', 'REG_AXXX_CP_SCRATCH_REG7',
'REG_AXXX_CP_STAT', 'REG_AXXX_CP_STATE_DEBUG_DATA',
'REG_AXXX_CP_STATE_DEBUG_INDEX', 'REG_AXXX_CP_STQ_AVAIL',
'REG_AXXX_CP_STQ_ST_STAT', 'REG_AXXX_CP_ST_BASE',
'REG_AXXX_CP_ST_BUFSZ', 'REG_AXXX_SCRATCH_ADDR',
'REG_AXXX_SCRATCH_UMSK', 'REG_COMPARE',
'REG_COMPARE_CP_COND_REG_EXEC_1_ONCHIP_MEM',
'REG_COMPARE_CP_COND_REG_EXEC_1_REG1__MASK',
'REG_COMPARE_CP_COND_REG_EXEC_1_REG1__SHIFT', 'REG_COMPARE_IMM',
'REG_COMPARE_IMM_CP_COND_REG_EXEC_1_IMM__MASK',
'REG_COMPARE_IMM_CP_COND_REG_EXEC_1_IMM__SHIFT', 'REG_CP_BLIT_0',
'REG_CP_BLIT_1', 'REG_CP_BLIT_2', 'REG_CP_BLIT_3',
'REG_CP_BLIT_4', 'REG_CP_BV_BR_COUNT_OPS_0',
'REG_CP_BV_BR_COUNT_OPS_1', 'REG_CP_COMPUTE_CHECKPOINT_0',
'REG_CP_COMPUTE_CHECKPOINT_1', 'REG_CP_COMPUTE_CHECKPOINT_2',
'REG_CP_COMPUTE_CHECKPOINT_3', 'REG_CP_COMPUTE_CHECKPOINT_4',
'REG_CP_COMPUTE_CHECKPOINT_5', 'REG_CP_COMPUTE_CHECKPOINT_6',
'REG_CP_COMPUTE_CHECKPOINT_7', 'REG_CP_COND_EXEC_0',
'REG_CP_COND_EXEC_1', 'REG_CP_COND_EXEC_2', 'REG_CP_COND_EXEC_3',
'REG_CP_COND_EXEC_4', 'REG_CP_COND_EXEC_5',
'REG_CP_COND_REG_EXEC_0', 'REG_CP_COND_REG_EXEC_2',
'REG_CP_COND_WRITE5_0', 'REG_CP_COND_WRITE5_1',
'REG_CP_COND_WRITE5_2', 'REG_CP_COND_WRITE5_3',
'REG_CP_COND_WRITE5_4', 'REG_CP_COND_WRITE5_5',
'REG_CP_COND_WRITE5_6', 'REG_CP_COND_WRITE5_7',
'REG_CP_COND_WRITE_0', 'REG_CP_COND_WRITE_1',
'REG_CP_COND_WRITE_2', 'REG_CP_COND_WRITE_3',
'REG_CP_COND_WRITE_4', 'REG_CP_COND_WRITE_5',
'REG_CP_DISPATCH_COMPUTE_0', 'REG_CP_DISPATCH_COMPUTE_1',
'REG_CP_DISPATCH_COMPUTE_2', 'REG_CP_DISPATCH_COMPUTE_3',
'REG_CP_DRAW_AUTO_0', 'REG_CP_DRAW_AUTO_1', 'REG_CP_DRAW_AUTO_4',
'REG_CP_DRAW_AUTO_5', 'REG_CP_DRAW_AUTO_NUM_VERTICES_BASE',
'REG_CP_DRAW_INDX_0', 'REG_CP_DRAW_INDX_1', 'REG_CP_DRAW_INDX_2',
'REG_CP_DRAW_INDX_2_0', 'REG_CP_DRAW_INDX_2_1',
'REG_CP_DRAW_INDX_2_2', 'REG_CP_DRAW_INDX_3',
'REG_CP_DRAW_INDX_4', 'REG_CP_DRAW_INDX_OFFSET_0',
'REG_CP_DRAW_INDX_OFFSET_1', 'REG_CP_DRAW_INDX_OFFSET_2',
'REG_CP_DRAW_INDX_OFFSET_3', 'REG_CP_DRAW_INDX_OFFSET_4',
'REG_CP_DRAW_INDX_OFFSET_5', 'REG_CP_DRAW_PRED_ENABLE_GLOBAL_0',
'REG_CP_DRAW_PRED_ENABLE_LOCAL_0', 'REG_CP_DRAW_PRED_SET_0',
'REG_CP_DRAW_PRED_SET_MEM_ADDR', 'REG_CP_EVENT_WRITE7_0',
'REG_CP_EVENT_WRITE_0', 'REG_CP_EVENT_WRITE_1',
'REG_CP_EVENT_WRITE_2', 'REG_CP_EVENT_WRITE_3',
'REG_CP_EXEC_CS_0', 'REG_CP_EXEC_CS_1', 'REG_CP_EXEC_CS_2',
'REG_CP_EXEC_CS_3', 'REG_CP_FIXED_STRIDE_DRAW_TABLE_2',
'REG_CP_FIXED_STRIDE_DRAW_TABLE_3',
'REG_CP_FIXED_STRIDE_DRAW_TABLE_IB_BASE', 'REG_CP_LOAD_STATE4_0',
'REG_CP_LOAD_STATE4_1', 'REG_CP_LOAD_STATE4_2',
'REG_CP_LOAD_STATE6_0', 'REG_CP_LOAD_STATE6_1',
'REG_CP_LOAD_STATE6_2', 'REG_CP_LOAD_STATE6_EXT_SRC_ADDR',
'REG_CP_LOAD_STATE_0', 'REG_CP_LOAD_STATE_1', 'REG_CP_MEMCPY_0',
'REG_CP_MEMCPY_1', 'REG_CP_MEMCPY_2', 'REG_CP_MEMCPY_3',
'REG_CP_MEMCPY_4', 'REG_CP_MEM_TO_MEM_0', 'REG_CP_MEM_TO_REG_0',
'REG_CP_MEM_TO_REG_1', 'REG_CP_MEM_TO_REG_2',
'REG_CP_MEM_TO_SCRATCH_MEM_0', 'REG_CP_MEM_TO_SCRATCH_MEM_1',
'REG_CP_MEM_TO_SCRATCH_MEM_2', 'REG_CP_MEM_TO_SCRATCH_MEM_3',
'REG_CP_MEM_WRITE_0', 'REG_CP_MEM_WRITE_1',
'REG_CP_MODIFY_TIMESTAMP_0', 'REG_CP_PERFCOUNTER_ACTION_0',
'REG_CP_PERFCOUNTER_ACTION_1', 'REG_CP_PERFCOUNTER_ACTION_2',
'REG_CP_REG_RMW_0', 'REG_CP_REG_RMW_1', 'REG_CP_REG_RMW_2',
'REG_CP_REG_TO_MEM_0', 'REG_CP_REG_TO_MEM_1',
'REG_CP_REG_TO_MEM_2', 'REG_CP_REG_TO_MEM_OFFSET_MEM_0',
'REG_CP_REG_TO_MEM_OFFSET_MEM_1',
'REG_CP_REG_TO_MEM_OFFSET_MEM_2',
'REG_CP_REG_TO_MEM_OFFSET_MEM_3',
'REG_CP_REG_TO_MEM_OFFSET_MEM_4',
'REG_CP_REG_TO_MEM_OFFSET_REG_0',
'REG_CP_REG_TO_MEM_OFFSET_REG_1',
'REG_CP_REG_TO_MEM_OFFSET_REG_2',
'REG_CP_REG_TO_MEM_OFFSET_REG_3', 'REG_CP_REG_TO_SCRATCH_0',
'REG_CP_REG_WRITE_0', 'REG_CP_REG_WRITE_1', 'REG_CP_REG_WRITE_2',
'REG_CP_RESET_CONTEXT_STATE_0', 'REG_CP_SCRATCH_TO_REG_0',
'REG_CP_SCRATCH_WRITE_0', 'REG_CP_SET_BIN_0', 'REG_CP_SET_BIN_1',
'REG_CP_SET_BIN_2', 'REG_CP_SET_BIN_DATA5_0',
'REG_CP_SET_BIN_DATA5_1', 'REG_CP_SET_BIN_DATA5_2',
'REG_CP_SET_BIN_DATA5_3', 'REG_CP_SET_BIN_DATA5_4',
'REG_CP_SET_BIN_DATA5_5', 'REG_CP_SET_BIN_DATA5_6',
'REG_CP_SET_BIN_DATA5_7', 'REG_CP_SET_BIN_DATA5_9',
'REG_CP_SET_BIN_DATA5_OFFSET_0', 'REG_CP_SET_BIN_DATA5_OFFSET_1',
'REG_CP_SET_BIN_DATA5_OFFSET_2', 'REG_CP_SET_BIN_DATA5_OFFSET_3',
'REG_CP_SET_BIN_DATA_0', 'REG_CP_SET_BIN_DATA_1',
'REG_CP_SET_CTXSWITCH_IB_0', 'REG_CP_SET_CTXSWITCH_IB_1',
'REG_CP_SET_CTXSWITCH_IB_2', 'REG_CP_SET_RENDER_MODE_0',
'REG_CP_SET_RENDER_MODE_1', 'REG_CP_SET_RENDER_MODE_2',
'REG_CP_SET_RENDER_MODE_3', 'REG_CP_SET_RENDER_MODE_4',
'REG_CP_SET_RENDER_MODE_5', 'REG_CP_SET_RENDER_MODE_6',
'REG_CP_SET_RENDER_MODE_7', 'REG_CP_SMMU_TABLE_UPDATE_0',
'REG_CP_SMMU_TABLE_UPDATE_1', 'REG_CP_SMMU_TABLE_UPDATE_2',
'REG_CP_SMMU_TABLE_UPDATE_3', 'REG_CP_START_BIN_BIN_COUNT',
'REG_CP_START_BIN_BODY_DWORDS', 'REG_CP_START_BIN_PREFIX_ADDR',
'REG_CP_START_BIN_PREFIX_DWORDS', 'REG_CP_THREAD_CONTROL_0',
'REG_CP_WAIT_MEM_GTE_0', 'REG_CP_WAIT_MEM_GTE_1',
'REG_CP_WAIT_MEM_GTE_2', 'REG_CP_WAIT_MEM_GTE_3',
'REG_CP_WAIT_REG_MEM_0', 'REG_CP_WAIT_REG_MEM_1',
'REG_CP_WAIT_REG_MEM_2', 'REG_CP_WAIT_REG_MEM_3',
'REG_CP_WAIT_REG_MEM_4', 'REG_CP_WAIT_REG_MEM_5',
'REG_CP_WAIT_TIMESTAMP_0', 'REG_CP_WAIT_TIMESTAMP_SRC_0',
'REG_CP_WAIT_TIMESTAMP_SRC_1', 'REG_CP_WAIT_TWO_REGS_0',
'REG_CP_WAIT_TWO_REGS_1', 'REG_CP_WAIT_TWO_REGS_2',
'REG_EV_DST_ONCHIP_CP_EVENT_WRITE7_1',
'REG_EV_DST_ONCHIP_CP_EVENT_WRITE7_3',
'REG_EV_DST_ONCHIP_CP_EVENT_WRITE7_4',
'REG_EV_DST_RAM_CP_EVENT_WRITE7_1',
'REG_EV_DST_RAM_CP_EVENT_WRITE7_2',
'REG_EV_DST_RAM_CP_EVENT_WRITE7_3',
'REG_EV_DST_RAM_CP_EVENT_WRITE7_4',
'REG_INDIRECT_OP_INDEXED_CP_DRAW_INDIRECT_MULTI_INDEX',
'REG_INDIRECT_OP_INDEXED_CP_DRAW_INDIRECT_MULTI_INDIRECT',
'REG_INDIRECT_OP_INDEXED_CP_DRAW_INDIRECT_MULTI_MAX_INDICES',
'REG_INDIRECT_OP_INDEXED_CP_DRAW_INDIRECT_MULTI_STRIDE',
'REG_INDIRECT_OP_INDIRECT_COUNT_CP_DRAW_INDIRECT_MULTI_INDIRECT',
'REG_INDIRECT_OP_INDIRECT_COUNT_CP_DRAW_INDIRECT_MULTI_INDIRECT_COUNT',
'REG_INDIRECT_OP_INDIRECT_COUNT_CP_DRAW_INDIRECT_MULTI_STRIDE',
'REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_INDEX',
'REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_INDIRECT',
'REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_INDIRECT_COUNT',
'REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_MAX_INDICES',
'REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_STRIDE',
'REG_INDIRECT_OP_NORMAL_CP_DRAW_INDIRECT_MULTI_INDIRECT',
'REG_INDIRECT_OP_NORMAL_CP_DRAW_INDIRECT_MULTI_STRIDE',
'REG_PRED_TEST_CP_COND_REG_EXEC_1',
'REG_REG_COMPARE_CP_COND_REG_EXEC_1',
'REG_REG_COMPARE_IMM_CP_COND_REG_EXEC_1',
'REG_RENDER_MODE_CP_COND_REG_EXEC_1',
'REG_THREAD_MODE_CP_COND_REG_EXEC_1',
'REG_TS_WAIT_ONCHIP_CP_WAIT_TIMESTAMP_ONCHIP_ADDR_0',
'REG_TS_WAIT_RAM_CP_WAIT_TIMESTAMP_ADDR', 'RENDERING_PASS',
'RENDER_MODE', 'RENDER_MODE_CP_COND_REG_EXEC_1_DWORDS__MASK',
'RENDER_MODE_CP_COND_REG_EXEC_1_DWORDS__SHIFT', 'RESTORE_IB',
'RL_TB', 'RM6_BINNING', 'RM6_BLIT2DSCALE', 'RM6_BYPASS',
'RM6_COMPUTE', 'RM6_ENDVIS', 'RM6_GMEM', 'RM6_IB1LIST_END',
'RM6_IB1LIST_START', 'RM6_IFPC_DISABLE', 'RM6_IFPC_ENABLE',
'RM6_RESOLVE', 'RM6_YIELD', 'ROP_AND', 'ROP_AND_INVERTED',
'ROP_AND_REVERSE', 'ROP_CLEAR', 'ROP_COPY', 'ROP_COPY_INVERTED',
'ROP_EQUIV', 'ROP_INVERT', 'ROP_NAND', 'ROP_NOOP', 'ROP_NOR',
'ROP_OR', 'ROP_OR_INVERTED', 'ROP_OR_REVERSE', 'ROP_SET',
'ROP_XOR', 'ROTATE_0', 'ROTATE_180', 'ROTATE_270', 'ROTATE_90',
'ROTATE_HFLIP', 'ROTATE_VFLIP', 'RST_PIX_CNT', 'RST_VTX_CNT',
'SAVE_IB', 'SB4_CS_SHADER', 'SB4_CS_SSBO', 'SB4_CS_TEX',
'SB4_DS_SHADER', 'SB4_DS_TEX', 'SB4_FS_SHADER', 'SB4_FS_TEX',
'SB4_GS_SHADER', 'SB4_GS_TEX', 'SB4_HS_SHADER', 'SB4_HS_TEX',
'SB4_SSBO', 'SB4_VS_SHADER', 'SB4_VS_TEX', 'SB6_CS_IBO',
'SB6_CS_SHADER', 'SB6_CS_TEX', 'SB6_DS_SHADER', 'SB6_DS_TEX',
'SB6_FS_SHADER', 'SB6_FS_TEX', 'SB6_GS_SHADER', 'SB6_GS_TEX',
'SB6_HS_SHADER', 'SB6_HS_TEX', 'SB6_IBO', 'SB6_VS_SHADER',
'SB6_VS_TEX', 'SB_COMPUTE_SHADER', 'SB_FRAG_MIPADDR',
'SB_FRAG_SHADER', 'SB_FRAG_TEX', 'SB_GEOM_SHADER',
'SB_VERT_MIPADDR', 'SB_VERT_SHADER', 'SB_VERT_TEX', 'SC_WAIT_WC',
'SECURE_SAVE_ADDR', 'SINGLE', 'SMMU_INFO', 'SOURCE_REG',
'SOURCE_SCRATCH_MEM', 'SS4_DIRECT', 'SS4_INDIRECT',
'SS6_BINDLESS', 'SS6_DIRECT', 'SS6_INDIRECT', 'SS6_UBO',
'SS_DIRECT', 'SS_INDIRECT', 'SS_INDIRECT_STM', 'SS_INDIRECT_TCM',
'SS_INVALID_ALL_IC', 'SS_INVALID_PART_IC', 'ST4_CONSTANTS',
'ST4_SHADER', 'ST4_UBO', 'ST6_CONSTANTS', 'ST6_IBO', 'ST6_SHADER',
'ST6_UBO', 'START_COMPUTE_CTRS', 'START_FRAGMENT_CTRS',
'START_PRIMITIVE_CTRS', 'STAT_EVENT', 'STENCIL_DECR_CLAMP',
'STENCIL_DECR_WRAP', 'STENCIL_INCR_CLAMP', 'STENCIL_INCR_WRAP',
'STENCIL_INVERT', 'STENCIL_KEEP', 'STENCIL_REPLACE',
'STENCIL_ZERO', 'STOP_COMPUTE_CTRS', 'STOP_FRAGMENT_CTRS',
'STOP_PRIMITIVE_CTRS', 'ST_CONSTANTS', 'ST_SHADER',
'TESS_CCW_TRIS', 'TESS_CW_TRIS', 'TESS_EQUAL',
'TESS_FRACTIONAL_EVEN', 'TESS_FRACTIONAL_ODD', 'TESS_ISOLINES',
'TESS_LINES', 'TESS_POINTS', 'TESS_QUADS', 'TESS_TRIANGLES',
'TEX_PREFETCH_GATHER4A', 'TEX_PREFETCH_GATHER4B',
'TEX_PREFETCH_GATHER4G', 'TEX_PREFETCH_GATHER4R',
'TEX_PREFETCH_SAM', 'TEX_PREFETCH_UNK0', 'TEX_PREFETCH_UNK6',
'TEX_PREFETCH_UNK7', 'THREAD128', 'THREAD64', 'THREAD_MODE',
'THREAD_MODE_CP_COND_REG_EXEC_1_DWORDS__MASK',
'THREAD_MODE_CP_COND_REG_EXEC_1_DWORDS__SHIFT', 'TILE6_2',
'TILE6_3', 'TILE6_LINEAR', 'TILE_FLUSH', 'TRACK_CNTL_REG',
'TRACK_LRZ', 'TRACK_RENDER_CNTL', 'TS_WAIT_GE_32B',
'TS_WAIT_GE_64B', 'TS_WAIT_GE_TIMESTAMP_SUM', 'TS_WAIT_ONCHIP',
'TS_WAIT_RAM', 'TWO_QUADS', 'TYPE_TILED', 'TYPE_WRITER', 'UNK_2C',
'UNK_2D', 'UNK_40', 'UNK_EVENT_WRITE', 'UNK_STRM_ADDRESS',
'UNK_STRM_SIZE_ADDRESS', 'USE_VISIBILITY', 'VIZQUERY_END',
'VIZQUERY_START', 'VS_DEALLOC', 'VS_DONE_TS', 'VS_FETCH_DONE',
'WRITE_ALWAYS', 'WRITE_EQ', 'WRITE_GE', 'WRITE_GT', 'WRITE_LE',
'WRITE_LT', 'WRITE_NE', 'WRITE_PRIMITIVE_COUNTS', 'WT_DONE_TS',
'WXYZ', 'WZYX', 'XYZW', 'YIELD_RESTORE_IB', 'ZPASS_DONE', 'ZYXW',
'a3xx_color_swap', 'a3xx_instrbuffermode', 'a3xx_msaa_samples',
'a3xx_rb_blend_opcode', 'a3xx_render_mode', 'a3xx_rop_code',
'a3xx_threadmode', 'a3xx_threadsize', 'a4xx_index_size',
'a4xx_state_block', 'a4xx_state_src', 'a4xx_state_type',
'a4xx_tess_spacing', 'a5xx_address_mode', 'a5xx_line_mode',
'a6xx_2d_ifmt', 'a6xx_bindless_descriptor_size',
'a6xx_buffers_location', 'a6xx_ccu_cache_size',
'a6xx_ccu_perfcounter_select', 'a6xx_cmp_perfcounter_select',
'a6xx_cp_perfcounter_select', 'a6xx_debugbus_id',
'a6xx_depth_format', 'a6xx_draw_indirect_opcode', 'a6xx_format',
'a6xx_fragcoord_sample_mode', 'a6xx_hlsq_perfcounter_select',
'a6xx_isam_mode', 'a6xx_lrz_dir_status',
'a6xx_lrz_perfcounter_select', 'a6xx_marker', 'a6xx_patch_type',
'a6xx_pc_perfcounter_select', 'a6xx_polygon_mode',
'a6xx_ras_perfcounter_select', 'a6xx_raster_direction',
'a6xx_raster_mode', 'a6xx_rb_perfcounter_select',
'a6xx_rbbm_perfcounter_select', 'a6xx_reduction_mode',
'a6xx_render_mode', 'a6xx_rotation', 'a6xx_sequenced_thread_dist',
'a6xx_shader_id', 'a6xx_single_prim_mode',
'a6xx_sp_perfcounter_select', 'a6xx_state_block',
'a6xx_state_src', 'a6xx_state_type', 'a6xx_tess_output',
'a6xx_tess_spacing', 'a6xx_tex_aniso', 'a6xx_tex_clamp',
'a6xx_tex_filter', 'a6xx_tex_prefetch_cmd', 'a6xx_tex_swiz',
'a6xx_tex_type', 'a6xx_threadsize', 'a6xx_tile_mode',
'a6xx_tp_perfcounter_select', 'a6xx_tse_perfcounter_select',
'a6xx_uche_perfcounter_select', 'a6xx_varying_interp_mode',
'a6xx_varying_ps_repl_mode', 'a6xx_vfd_perfcounter_select',
'a6xx_vpc_perfcounter_select', 'a6xx_vsc_perfcounter_select',
'a6xx_ztest_mode', 'a7xx_ccu_perfcounter_select', 'a7xx_cluster',
'a7xx_cmp_perfcounter_select', 'a7xx_cp_perfcounter_select',
'a7xx_cs_yalign', 'a7xx_debugbus_id',
'a7xx_gbif_perfcounter_select', 'a7xx_hlsq_perfcounter_select',
'a7xx_lrz_perfcounter_select', 'a7xx_pc_perfcounter_select',
'a7xx_pipe', 'a7xx_ras_perfcounter_select',
'a7xx_rb_perfcounter_select', 'a7xx_rbbm_perfcounter_select',
'a7xx_sp_perfcounter_select', 'a7xx_state_location',
'a7xx_statetype_id', 'a7xx_tp_perfcounter_select',
'a7xx_tse_perfcounter_select', 'a7xx_uche_perfcounter_select',
'a7xx_ufc_perfcounter_select', 'a7xx_vfd_perfcounter_select',
'a7xx_vpc_perfcounter_select', 'a7xx_vsc_perfcounter_select',
'adreno_compare_func', 'adreno_pa_su_sc_draw',
'adreno_pm4_packet_type', 'adreno_pm4_type3_packets',
'adreno_rb_blend_factor', 'adreno_rb_copy_control_mode',
'adreno_rb_depth_format', 'adreno_rb_dither_mode',
'adreno_rb_surface_endian', 'adreno_state_block',
'adreno_state_src', 'adreno_state_type', 'adreno_stencil_op',
'chip', 'compare_mode', 'cp_blit_cmd', 'cp_cond_function',
'cp_draw_pred_src', 'cp_draw_pred_test', 'cp_thread',
'ctxswitch_ib', 'event_write_dst', 'event_write_src',
'pc_di_face_cull_sel', 'pc_di_index_size', 'pc_di_primtype',
'pc_di_src_sel', 'pc_di_vis_cull_mode', 'pipe_count_op',
'poll_memory_type', 'pseudo_reg', 'reg_tracker',
'render_mode_cmd', 'source_type', 'timestamp_op', 'ts_wait_type',
'ts_wait_value_src', 'vgt_event_type']
def CP_LOAD_STATE_0_DST_OFF(val): return (val << CP_LOAD_STATE_0_DST_OFF__SHIFT) & CP_LOAD_STATE_0_DST_OFF__MASK
def CP_LOAD_STATE_0_STATE_SRC(val): return (val << CP_LOAD_STATE_0_STATE_SRC__SHIFT) & CP_LOAD_STATE_0_STATE_SRC__MASK
def CP_LOAD_STATE_0_STATE_BLOCK(val): return (val << CP_LOAD_STATE_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE_0_STATE_BLOCK__MASK
def CP_LOAD_STATE_0_NUM_UNIT(val): return (val << CP_LOAD_STATE_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE_0_NUM_UNIT__MASK
def CP_LOAD_STATE_1_STATE_TYPE(val): return (val << CP_LOAD_STATE_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE_1_STATE_TYPE__MASK
def CP_LOAD_STATE_1_EXT_SRC_ADDR(val): return (val << CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK
def CP_LOAD_STATE4_0_DST_OFF(val): return (val << CP_LOAD_STATE4_0_DST_OFF__SHIFT) & CP_LOAD_STATE4_0_DST_OFF__MASK
def CP_LOAD_STATE4_0_STATE_SRC(val): return (val << CP_LOAD_STATE4_0_STATE_SRC__SHIFT) & CP_LOAD_STATE4_0_STATE_SRC__MASK
def CP_LOAD_STATE4_0_STATE_BLOCK(val): return (val << CP_LOAD_STATE4_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE4_0_STATE_BLOCK__MASK
def CP_LOAD_STATE4_0_NUM_UNIT(val): return (val << CP_LOAD_STATE4_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE4_0_NUM_UNIT__MASK
def CP_LOAD_STATE4_1_STATE_TYPE(val): return (val << CP_LOAD_STATE4_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE4_1_STATE_TYPE__MASK
def CP_LOAD_STATE4_1_EXT_SRC_ADDR(val): return (val << CP_LOAD_STATE4_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE4_1_EXT_SRC_ADDR__MASK
def CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(val): return (val << CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__SHIFT) & CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__MASK
def CP_LOAD_STATE6_0_DST_OFF(val): return (val << CP_LOAD_STATE6_0_DST_OFF__SHIFT) & CP_LOAD_STATE6_0_DST_OFF__MASK
def CP_LOAD_STATE6_0_STATE_TYPE(val): return (val << CP_LOAD_STATE6_0_STATE_TYPE__SHIFT) & CP_LOAD_STATE6_0_STATE_TYPE__MASK
def CP_LOAD_STATE6_0_STATE_SRC(val): return (val << CP_LOAD_STATE6_0_STATE_SRC__SHIFT) & CP_LOAD_STATE6_0_STATE_SRC__MASK
def CP_LOAD_STATE6_0_STATE_BLOCK(val): return (val << CP_LOAD_STATE6_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE6_0_STATE_BLOCK__MASK
def CP_LOAD_STATE6_0_NUM_UNIT(val): return (val << CP_LOAD_STATE6_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE6_0_NUM_UNIT__MASK
def CP_LOAD_STATE6_1_EXT_SRC_ADDR(val): return (val << CP_LOAD_STATE6_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE6_1_EXT_SRC_ADDR__MASK
def CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(val): return (val << CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__SHIFT) & CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__MASK
def CP_DRAW_INDX_0_VIZ_QUERY(val): return (val << CP_DRAW_INDX_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_0_VIZ_QUERY__MASK
def CP_DRAW_INDX_1_PRIM_TYPE(val): return (val << CP_DRAW_INDX_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_1_PRIM_TYPE__MASK
def CP_DRAW_INDX_1_SOURCE_SELECT(val): return (val << CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_1_SOURCE_SELECT__MASK
def CP_DRAW_INDX_1_VIS_CULL(val): return (val << CP_DRAW_INDX_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_1_VIS_CULL__MASK
def CP_DRAW_INDX_1_INDEX_SIZE(val): return (val << CP_DRAW_INDX_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_1_INDEX_SIZE__MASK
def CP_DRAW_INDX_1_NUM_INSTANCES(val): return (val << CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_1_NUM_INSTANCES__MASK
def CP_DRAW_INDX_2_NUM_INDICES(val): return (val << CP_DRAW_INDX_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_NUM_INDICES__MASK
def CP_DRAW_INDX_3_INDX_BASE(val): return (val << CP_DRAW_INDX_3_INDX_BASE__SHIFT) & CP_DRAW_INDX_3_INDX_BASE__MASK
def CP_DRAW_INDX_4_INDX_SIZE(val): return (val << CP_DRAW_INDX_4_INDX_SIZE__SHIFT) & CP_DRAW_INDX_4_INDX_SIZE__MASK
def CP_DRAW_INDX_2_0_VIZ_QUERY(val): return (val << CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_2_0_VIZ_QUERY__MASK
def CP_DRAW_INDX_2_1_PRIM_TYPE(val): return (val << CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_2_1_PRIM_TYPE__MASK
def CP_DRAW_INDX_2_1_SOURCE_SELECT(val): return (val << CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK
def CP_DRAW_INDX_2_1_VIS_CULL(val): return (val << CP_DRAW_INDX_2_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_2_1_VIS_CULL__MASK
def CP_DRAW_INDX_2_1_INDEX_SIZE(val): return (val << CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_2_1_INDEX_SIZE__MASK
def CP_DRAW_INDX_2_1_NUM_INSTANCES(val): return (val << CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK
def CP_DRAW_INDX_2_2_NUM_INDICES(val): return (val << CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_2_NUM_INDICES__MASK
def CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(val): return (val << CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK
def CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(val): return (val << CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK
def CP_DRAW_INDX_OFFSET_0_VIS_CULL(val): return (val << CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT) & CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK
def CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(val): return (val << CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK
def CP_DRAW_INDX_OFFSET_0_PATCH_TYPE(val): return (val << CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__SHIFT) & CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__MASK
def CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES(val): return (val << CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK
def CP_DRAW_INDX_OFFSET_2_NUM_INDICES(val): return (val << CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK
def CP_DRAW_INDX_OFFSET_3_FIRST_INDX(val): return (val << CP_DRAW_INDX_OFFSET_3_FIRST_INDX__SHIFT) & CP_DRAW_INDX_OFFSET_3_FIRST_INDX__MASK
def A5XX_CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO(val): return (val << A5XX_CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__SHIFT) & A5XX_CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__MASK
def A5XX_CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI(val): return (val << A5XX_CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__SHIFT) & A5XX_CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__MASK
def A5XX_CP_DRAW_INDX_OFFSET_6_MAX_INDICES(val): return (val << A5XX_CP_DRAW_INDX_OFFSET_6_MAX_INDICES__SHIFT) & A5XX_CP_DRAW_INDX_OFFSET_6_MAX_INDICES__MASK
def CP_DRAW_INDX_OFFSET_4_INDX_BASE(val): return (val << CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT) & CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK
def CP_DRAW_INDX_OFFSET_5_INDX_SIZE(val): return (val << CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK
def A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE(val): return (val << A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__MASK
def A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT(val): return (val << A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__MASK
def A4XX_CP_DRAW_INDIRECT_0_VIS_CULL(val): return (val << A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__MASK
def A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE(val): return (val << A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__MASK
def A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE(val): return (val << A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__MASK
def A4XX_CP_DRAW_INDIRECT_1_INDIRECT(val): return (val << A4XX_CP_DRAW_INDIRECT_1_INDIRECT__SHIFT) & A4XX_CP_DRAW_INDIRECT_1_INDIRECT__MASK
def A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO(val): return (val << A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__SHIFT) & A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__MASK
def A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI(val): return (val << A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__SHIFT) & A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__MASK
def A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE(val): return (val << A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__MASK
def A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT(val): return (val << A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__MASK
def A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL(val): return (val << A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__MASK
def A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE(val): return (val << A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__MASK
def A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE(val): return (val << A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE__MASK
def A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE(val): return (val << A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__MASK
def A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE(val): return (val << A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__MASK
def A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT(val): return (val << A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__MASK
def A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO(val): return (val << A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__MASK
def A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI(val): return (val << A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__MASK
def A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES(val): return (val << A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__MASK
def A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO(val): return (val << A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__MASK
def A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI(val): return (val << A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__MASK
def A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE(val): return (val << A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE__MASK
def A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT(val): return (val << A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT__MASK
def A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL(val): return (val << A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL__MASK
def A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE(val): return (val << A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE__MASK
def A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE(val): return (val << A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE__MASK
def A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE(val): return (val << A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE__MASK
def A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF(val): return (val << A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__MASK
def CP_DRAW_AUTO_0_PRIM_TYPE(val): return (val << CP_DRAW_AUTO_0_PRIM_TYPE__SHIFT) & CP_DRAW_AUTO_0_PRIM_TYPE__MASK
def CP_DRAW_AUTO_0_SOURCE_SELECT(val): return (val << CP_DRAW_AUTO_0_SOURCE_SELECT__SHIFT) & CP_DRAW_AUTO_0_SOURCE_SELECT__MASK
def CP_DRAW_AUTO_0_VIS_CULL(val): return (val << CP_DRAW_AUTO_0_VIS_CULL__SHIFT) & CP_DRAW_AUTO_0_VIS_CULL__MASK
def CP_DRAW_AUTO_0_INDEX_SIZE(val): return (val << CP_DRAW_AUTO_0_INDEX_SIZE__SHIFT) & CP_DRAW_AUTO_0_INDEX_SIZE__MASK
def CP_DRAW_AUTO_0_PATCH_TYPE(val): return (val << CP_DRAW_AUTO_0_PATCH_TYPE__SHIFT) & CP_DRAW_AUTO_0_PATCH_TYPE__MASK
def CP_DRAW_AUTO_1_NUM_INSTANCES(val): return (val << CP_DRAW_AUTO_1_NUM_INSTANCES__SHIFT) & CP_DRAW_AUTO_1_NUM_INSTANCES__MASK
def CP_DRAW_AUTO_4_NUM_VERTICES_OFFSET(val): return (val << CP_DRAW_AUTO_4_NUM_VERTICES_OFFSET__SHIFT) & CP_DRAW_AUTO_4_NUM_VERTICES_OFFSET__MASK
def CP_DRAW_AUTO_5_STRIDE(val): return (val << CP_DRAW_AUTO_5_STRIDE__SHIFT) & CP_DRAW_AUTO_5_STRIDE__MASK
def CP_DRAW_PRED_SET_0_SRC(val): return (val << CP_DRAW_PRED_SET_0_SRC__SHIFT) & CP_DRAW_PRED_SET_0_SRC__MASK
def CP_DRAW_PRED_SET_0_TEST(val): return (val << CP_DRAW_PRED_SET_0_TEST__SHIFT) & CP_DRAW_PRED_SET_0_TEST__MASK
def CP_SET_DRAW_STATE__0_COUNT(val): return (val << CP_SET_DRAW_STATE__0_COUNT__SHIFT) & CP_SET_DRAW_STATE__0_COUNT__MASK
def CP_SET_DRAW_STATE__0_GROUP_ID(val): return (val << CP_SET_DRAW_STATE__0_GROUP_ID__SHIFT) & CP_SET_DRAW_STATE__0_GROUP_ID__MASK
def CP_SET_DRAW_STATE__1_ADDR_LO(val): return (val << CP_SET_DRAW_STATE__1_ADDR_LO__SHIFT) & CP_SET_DRAW_STATE__1_ADDR_LO__MASK
def CP_SET_DRAW_STATE__2_ADDR_HI(val): return (val << CP_SET_DRAW_STATE__2_ADDR_HI__SHIFT) & CP_SET_DRAW_STATE__2_ADDR_HI__MASK
def CP_SET_BIN_1_X1(val): return (val << CP_SET_BIN_1_X1__SHIFT) & CP_SET_BIN_1_X1__MASK
def CP_SET_BIN_1_Y1(val): return (val << CP_SET_BIN_1_Y1__SHIFT) & CP_SET_BIN_1_Y1__MASK
def CP_SET_BIN_2_X2(val): return (val << CP_SET_BIN_2_X2__SHIFT) & CP_SET_BIN_2_X2__MASK
def CP_SET_BIN_2_Y2(val): return (val << CP_SET_BIN_2_Y2__SHIFT) & CP_SET_BIN_2_Y2__MASK
def CP_SET_BIN_DATA_0_BIN_DATA_ADDR(val): return (val << CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT) & CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK
def CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS(val): return (val << CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT) & CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK
def CP_SET_BIN_DATA5_0_VSC_SIZE(val): return (val << CP_SET_BIN_DATA5_0_VSC_SIZE__SHIFT) & CP_SET_BIN_DATA5_0_VSC_SIZE__MASK
def CP_SET_BIN_DATA5_0_VSC_N(val): return (val << CP_SET_BIN_DATA5_0_VSC_N__SHIFT) & CP_SET_BIN_DATA5_0_VSC_N__MASK
def CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO(val): return (val << CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__SHIFT) & CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__MASK
def CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI(val): return (val << CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__SHIFT) & CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__MASK
def CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO(val): return (val << CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__SHIFT) & CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__MASK
def CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI(val): return (val << CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__SHIFT) & CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__MASK
def CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO(val): return (val << CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO__SHIFT) & CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO__MASK
def CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI(val): return (val << CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI__SHIFT) & CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI__MASK
def CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE(val): return (val << CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__SHIFT) & CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__MASK
def CP_SET_BIN_DATA5_OFFSET_0_VSC_N(val): return (val << CP_SET_BIN_DATA5_OFFSET_0_VSC_N__SHIFT) & CP_SET_BIN_DATA5_OFFSET_0_VSC_N__MASK
def CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET(val): return (val << CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET__SHIFT) & CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET__MASK
def CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET(val): return (val << CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET__SHIFT) & CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET__MASK
def CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET(val): return (val << CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET__SHIFT) & CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET__MASK
def CP_REG_RMW_0_DST_REG(val): return (val << CP_REG_RMW_0_DST_REG__SHIFT) & CP_REG_RMW_0_DST_REG__MASK
def CP_REG_RMW_0_ROTATE(val): return (val << CP_REG_RMW_0_ROTATE__SHIFT) & CP_REG_RMW_0_ROTATE__MASK
def CP_REG_RMW_1_SRC0(val): return (val << CP_REG_RMW_1_SRC0__SHIFT) & CP_REG_RMW_1_SRC0__MASK
def CP_REG_RMW_2_SRC1(val): return (val << CP_REG_RMW_2_SRC1__SHIFT) & CP_REG_RMW_2_SRC1__MASK
def CP_REG_TO_MEM_0_REG(val): return (val << CP_REG_TO_MEM_0_REG__SHIFT) & CP_REG_TO_MEM_0_REG__MASK
def CP_REG_TO_MEM_0_CNT(val): return (val << CP_REG_TO_MEM_0_CNT__SHIFT) & CP_REG_TO_MEM_0_CNT__MASK
def CP_REG_TO_MEM_1_DEST(val): return (val << CP_REG_TO_MEM_1_DEST__SHIFT) & CP_REG_TO_MEM_1_DEST__MASK
def CP_REG_TO_MEM_2_DEST_HI(val): return (val << CP_REG_TO_MEM_2_DEST_HI__SHIFT) & CP_REG_TO_MEM_2_DEST_HI__MASK
def CP_REG_TO_MEM_OFFSET_REG_0_REG(val): return (val << CP_REG_TO_MEM_OFFSET_REG_0_REG__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_0_REG__MASK
def CP_REG_TO_MEM_OFFSET_REG_0_CNT(val): return (val << CP_REG_TO_MEM_OFFSET_REG_0_CNT__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_0_CNT__MASK
def CP_REG_TO_MEM_OFFSET_REG_1_DEST(val): return (val << CP_REG_TO_MEM_OFFSET_REG_1_DEST__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_1_DEST__MASK
def CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI(val): return (val << CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__MASK
def CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0(val): return (val << CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__MASK
def CP_REG_TO_MEM_OFFSET_MEM_0_REG(val): return (val << CP_REG_TO_MEM_OFFSET_MEM_0_REG__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_0_REG__MASK
def CP_REG_TO_MEM_OFFSET_MEM_0_CNT(val): return (val << CP_REG_TO_MEM_OFFSET_MEM_0_CNT__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_0_CNT__MASK
def CP_REG_TO_MEM_OFFSET_MEM_1_DEST(val): return (val << CP_REG_TO_MEM_OFFSET_MEM_1_DEST__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_1_DEST__MASK
def CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI(val): return (val << CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__MASK
def CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO(val): return (val << CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO__MASK
def CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI(val): return (val << CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI__MASK
def CP_MEM_TO_REG_0_REG(val): return (val << CP_MEM_TO_REG_0_REG__SHIFT) & CP_MEM_TO_REG_0_REG__MASK
def CP_MEM_TO_REG_0_CNT(val): return (val << CP_MEM_TO_REG_0_CNT__SHIFT) & CP_MEM_TO_REG_0_CNT__MASK
def CP_MEM_TO_REG_1_SRC(val): return (val << CP_MEM_TO_REG_1_SRC__SHIFT) & CP_MEM_TO_REG_1_SRC__MASK
def CP_MEM_TO_REG_2_SRC_HI(val): return (val << CP_MEM_TO_REG_2_SRC_HI__SHIFT) & CP_MEM_TO_REG_2_SRC_HI__MASK
def CP_MEMCPY_0_DWORDS(val): return (val << CP_MEMCPY_0_DWORDS__SHIFT) & CP_MEMCPY_0_DWORDS__MASK
def CP_MEMCPY_1_SRC_LO(val): return (val << CP_MEMCPY_1_SRC_LO__SHIFT) & CP_MEMCPY_1_SRC_LO__MASK
def CP_MEMCPY_2_SRC_HI(val): return (val << CP_MEMCPY_2_SRC_HI__SHIFT) & CP_MEMCPY_2_SRC_HI__MASK
def CP_MEMCPY_3_DST_LO(val): return (val << CP_MEMCPY_3_DST_LO__SHIFT) & CP_MEMCPY_3_DST_LO__MASK
def CP_MEMCPY_4_DST_HI(val): return (val << CP_MEMCPY_4_DST_HI__SHIFT) & CP_MEMCPY_4_DST_HI__MASK
def CP_REG_TO_SCRATCH_0_REG(val): return (val << CP_REG_TO_SCRATCH_0_REG__SHIFT) & CP_REG_TO_SCRATCH_0_REG__MASK
def CP_REG_TO_SCRATCH_0_SCRATCH(val): return (val << CP_REG_TO_SCRATCH_0_SCRATCH__SHIFT) & CP_REG_TO_SCRATCH_0_SCRATCH__MASK
def CP_REG_TO_SCRATCH_0_CNT(val): return (val << CP_REG_TO_SCRATCH_0_CNT__SHIFT) & CP_REG_TO_SCRATCH_0_CNT__MASK
def CP_SCRATCH_TO_REG_0_REG(val): return (val << CP_SCRATCH_TO_REG_0_REG__SHIFT) & CP_SCRATCH_TO_REG_0_REG__MASK
def CP_SCRATCH_TO_REG_0_SCRATCH(val): return (val << CP_SCRATCH_TO_REG_0_SCRATCH__SHIFT) & CP_SCRATCH_TO_REG_0_SCRATCH__MASK
def CP_SCRATCH_TO_REG_0_CNT(val): return (val << CP_SCRATCH_TO_REG_0_CNT__SHIFT) & CP_SCRATCH_TO_REG_0_CNT__MASK
def CP_SCRATCH_WRITE_0_SCRATCH(val): return (val << CP_SCRATCH_WRITE_0_SCRATCH__SHIFT) & CP_SCRATCH_WRITE_0_SCRATCH__MASK
def CP_MEM_WRITE_0_ADDR_LO(val): return (val << CP_MEM_WRITE_0_ADDR_LO__SHIFT) & CP_MEM_WRITE_0_ADDR_LO__MASK
def CP_MEM_WRITE_1_ADDR_HI(val): return (val << CP_MEM_WRITE_1_ADDR_HI__SHIFT) & CP_MEM_WRITE_1_ADDR_HI__MASK
def CP_COND_WRITE_0_FUNCTION(val): return (val << CP_COND_WRITE_0_FUNCTION__SHIFT) & CP_COND_WRITE_0_FUNCTION__MASK
def CP_COND_WRITE_1_POLL_ADDR(val): return (val << CP_COND_WRITE_1_POLL_ADDR__SHIFT) & CP_COND_WRITE_1_POLL_ADDR__MASK
def CP_COND_WRITE_2_REF(val): return (val << CP_COND_WRITE_2_REF__SHIFT) & CP_COND_WRITE_2_REF__MASK
def CP_COND_WRITE_3_MASK(val): return (val << CP_COND_WRITE_3_MASK__SHIFT) & CP_COND_WRITE_3_MASK__MASK
def CP_COND_WRITE_4_WRITE_ADDR(val): return (val << CP_COND_WRITE_4_WRITE_ADDR__SHIFT) & CP_COND_WRITE_4_WRITE_ADDR__MASK
def CP_COND_WRITE_5_WRITE_DATA(val): return (val << CP_COND_WRITE_5_WRITE_DATA__SHIFT) & CP_COND_WRITE_5_WRITE_DATA__MASK
def CP_COND_WRITE5_0_FUNCTION(val): return (val << CP_COND_WRITE5_0_FUNCTION__SHIFT) & CP_COND_WRITE5_0_FUNCTION__MASK
def CP_COND_WRITE5_0_POLL(val): return (val << CP_COND_WRITE5_0_POLL__SHIFT) & CP_COND_WRITE5_0_POLL__MASK
def CP_COND_WRITE5_1_POLL_ADDR_LO(val): return (val << CP_COND_WRITE5_1_POLL_ADDR_LO__SHIFT) & CP_COND_WRITE5_1_POLL_ADDR_LO__MASK
def CP_COND_WRITE5_2_POLL_ADDR_HI(val): return (val << CP_COND_WRITE5_2_POLL_ADDR_HI__SHIFT) & CP_COND_WRITE5_2_POLL_ADDR_HI__MASK
def CP_COND_WRITE5_3_REF(val): return (val << CP_COND_WRITE5_3_REF__SHIFT) & CP_COND_WRITE5_3_REF__MASK
def CP_COND_WRITE5_4_MASK(val): return (val << CP_COND_WRITE5_4_MASK__SHIFT) & CP_COND_WRITE5_4_MASK__MASK
def CP_COND_WRITE5_5_WRITE_ADDR_LO(val): return (val << CP_COND_WRITE5_5_WRITE_ADDR_LO__SHIFT) & CP_COND_WRITE5_5_WRITE_ADDR_LO__MASK
def CP_COND_WRITE5_6_WRITE_ADDR_HI(val): return (val << CP_COND_WRITE5_6_WRITE_ADDR_HI__SHIFT) & CP_COND_WRITE5_6_WRITE_ADDR_HI__MASK
def CP_COND_WRITE5_7_WRITE_DATA(val): return (val << CP_COND_WRITE5_7_WRITE_DATA__SHIFT) & CP_COND_WRITE5_7_WRITE_DATA__MASK
def CP_WAIT_MEM_GTE_0_RESERVED(val): return (val << CP_WAIT_MEM_GTE_0_RESERVED__SHIFT) & CP_WAIT_MEM_GTE_0_RESERVED__MASK
def CP_WAIT_MEM_GTE_1_POLL_ADDR_LO(val): return (val << CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__SHIFT) & CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__MASK
def CP_WAIT_MEM_GTE_2_POLL_ADDR_HI(val): return (val << CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__SHIFT) & CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__MASK
def CP_WAIT_MEM_GTE_3_REF(val): return (val << CP_WAIT_MEM_GTE_3_REF__SHIFT) & CP_WAIT_MEM_GTE_3_REF__MASK
def CP_WAIT_REG_MEM_0_FUNCTION(val): return (val << CP_WAIT_REG_MEM_0_FUNCTION__SHIFT) & CP_WAIT_REG_MEM_0_FUNCTION__MASK
def CP_WAIT_REG_MEM_0_POLL(val): return (val << CP_WAIT_REG_MEM_0_POLL__SHIFT) & CP_WAIT_REG_MEM_0_POLL__MASK
def CP_WAIT_REG_MEM_1_POLL_ADDR_LO(val): return (val << CP_WAIT_REG_MEM_1_POLL_ADDR_LO__SHIFT) & CP_WAIT_REG_MEM_1_POLL_ADDR_LO__MASK
def CP_WAIT_REG_MEM_2_POLL_ADDR_HI(val): return (val << CP_WAIT_REG_MEM_2_POLL_ADDR_HI__SHIFT) & CP_WAIT_REG_MEM_2_POLL_ADDR_HI__MASK
def CP_WAIT_REG_MEM_3_REF(val): return (val << CP_WAIT_REG_MEM_3_REF__SHIFT) & CP_WAIT_REG_MEM_3_REF__MASK
def CP_WAIT_REG_MEM_4_MASK(val): return (val << CP_WAIT_REG_MEM_4_MASK__SHIFT) & CP_WAIT_REG_MEM_4_MASK__MASK
def CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(val): return (val << CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES__SHIFT) & CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES__MASK
def CP_WAIT_TWO_REGS_0_REG0(val): return (val << CP_WAIT_TWO_REGS_0_REG0__SHIFT) & CP_WAIT_TWO_REGS_0_REG0__MASK
def CP_WAIT_TWO_REGS_1_REG1(val): return (val << CP_WAIT_TWO_REGS_1_REG1__SHIFT) & CP_WAIT_TWO_REGS_1_REG1__MASK
def CP_WAIT_TWO_REGS_2_REF(val): return (val << CP_WAIT_TWO_REGS_2_REF__SHIFT) & CP_WAIT_TWO_REGS_2_REF__MASK
def CP_DISPATCH_COMPUTE_1_X(val): return (val << CP_DISPATCH_COMPUTE_1_X__SHIFT) & CP_DISPATCH_COMPUTE_1_X__MASK
def CP_DISPATCH_COMPUTE_2_Y(val): return (val << CP_DISPATCH_COMPUTE_2_Y__SHIFT) & CP_DISPATCH_COMPUTE_2_Y__MASK
def CP_DISPATCH_COMPUTE_3_Z(val): return (val << CP_DISPATCH_COMPUTE_3_Z__SHIFT) & CP_DISPATCH_COMPUTE_3_Z__MASK
def CP_SET_RENDER_MODE_0_MODE(val): return (val << CP_SET_RENDER_MODE_0_MODE__SHIFT) & CP_SET_RENDER_MODE_0_MODE__MASK
def CP_SET_RENDER_MODE_1_ADDR_0_LO(val): return (val << CP_SET_RENDER_MODE_1_ADDR_0_LO__SHIFT) & CP_SET_RENDER_MODE_1_ADDR_0_LO__MASK
def CP_SET_RENDER_MODE_2_ADDR_0_HI(val): return (val << CP_SET_RENDER_MODE_2_ADDR_0_HI__SHIFT) & CP_SET_RENDER_MODE_2_ADDR_0_HI__MASK
def CP_SET_RENDER_MODE_5_ADDR_1_LEN(val): return (val << CP_SET_RENDER_MODE_5_ADDR_1_LEN__SHIFT) & CP_SET_RENDER_MODE_5_ADDR_1_LEN__MASK
def CP_SET_RENDER_MODE_6_ADDR_1_LO(val): return (val << CP_SET_RENDER_MODE_6_ADDR_1_LO__SHIFT) & CP_SET_RENDER_MODE_6_ADDR_1_LO__MASK
def CP_SET_RENDER_MODE_7_ADDR_1_HI(val): return (val << CP_SET_RENDER_MODE_7_ADDR_1_HI__SHIFT) & CP_SET_RENDER_MODE_7_ADDR_1_HI__MASK
def CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO(val): return (val << CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__SHIFT) & CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__MASK
def CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI(val): return (val << CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__SHIFT) & CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__MASK
def CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN(val): return (val << CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__SHIFT) & CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__MASK
def CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO(val): return (val << CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__SHIFT) & CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__MASK
def CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI(val): return (val << CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__SHIFT) & CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__MASK
def CP_PERFCOUNTER_ACTION_1_ADDR_0_LO(val): return (val << CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__SHIFT) & CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__MASK
def CP_PERFCOUNTER_ACTION_2_ADDR_0_HI(val): return (val << CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__SHIFT) & CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__MASK
def CP_EVENT_WRITE_0_EVENT(val): return (val << CP_EVENT_WRITE_0_EVENT__SHIFT) & CP_EVENT_WRITE_0_EVENT__MASK
def CP_EVENT_WRITE_1_ADDR_0_LO(val): return (val << CP_EVENT_WRITE_1_ADDR_0_LO__SHIFT) & CP_EVENT_WRITE_1_ADDR_0_LO__MASK
def CP_EVENT_WRITE_2_ADDR_0_HI(val): return (val << CP_EVENT_WRITE_2_ADDR_0_HI__SHIFT) & CP_EVENT_WRITE_2_ADDR_0_HI__MASK
def CP_EVENT_WRITE7_0_EVENT(val): return (val << CP_EVENT_WRITE7_0_EVENT__SHIFT) & CP_EVENT_WRITE7_0_EVENT__MASK
def CP_EVENT_WRITE7_0_WRITE_SRC(val): return (val << CP_EVENT_WRITE7_0_WRITE_SRC__SHIFT) & CP_EVENT_WRITE7_0_WRITE_SRC__MASK
def CP_EVENT_WRITE7_0_WRITE_DST(val): return (val << CP_EVENT_WRITE7_0_WRITE_DST__SHIFT) & CP_EVENT_WRITE7_0_WRITE_DST__MASK
def EV_DST_RAM_CP_EVENT_WRITE7_1_ADDR_0_LO(val): return (val << EV_DST_RAM_CP_EVENT_WRITE7_1_ADDR_0_LO__SHIFT) & EV_DST_RAM_CP_EVENT_WRITE7_1_ADDR_0_LO__MASK
def EV_DST_RAM_CP_EVENT_WRITE7_2_ADDR_0_HI(val): return (val << EV_DST_RAM_CP_EVENT_WRITE7_2_ADDR_0_HI__SHIFT) & EV_DST_RAM_CP_EVENT_WRITE7_2_ADDR_0_HI__MASK
def EV_DST_RAM_CP_EVENT_WRITE7_3_PAYLOAD_0(val): return (val << EV_DST_RAM_CP_EVENT_WRITE7_3_PAYLOAD_0__SHIFT) & EV_DST_RAM_CP_EVENT_WRITE7_3_PAYLOAD_0__MASK
def EV_DST_RAM_CP_EVENT_WRITE7_4_PAYLOAD_1(val): return (val << EV_DST_RAM_CP_EVENT_WRITE7_4_PAYLOAD_1__SHIFT) & EV_DST_RAM_CP_EVENT_WRITE7_4_PAYLOAD_1__MASK
def EV_DST_ONCHIP_CP_EVENT_WRITE7_1_ONCHIP_ADDR_0(val): return (val << EV_DST_ONCHIP_CP_EVENT_WRITE7_1_ONCHIP_ADDR_0__SHIFT) & EV_DST_ONCHIP_CP_EVENT_WRITE7_1_ONCHIP_ADDR_0__MASK
def EV_DST_ONCHIP_CP_EVENT_WRITE7_3_PAYLOAD_0(val): return (val << EV_DST_ONCHIP_CP_EVENT_WRITE7_3_PAYLOAD_0__SHIFT) & EV_DST_ONCHIP_CP_EVENT_WRITE7_3_PAYLOAD_0__MASK
def EV_DST_ONCHIP_CP_EVENT_WRITE7_4_PAYLOAD_1(val): return (val << EV_DST_ONCHIP_CP_EVENT_WRITE7_4_PAYLOAD_1__SHIFT) & EV_DST_ONCHIP_CP_EVENT_WRITE7_4_PAYLOAD_1__MASK
def CP_BLIT_0_OP(val): return (val << CP_BLIT_0_OP__SHIFT) & CP_BLIT_0_OP__MASK
def CP_BLIT_1_SRC_X1(val): return (val << CP_BLIT_1_SRC_X1__SHIFT) & CP_BLIT_1_SRC_X1__MASK
def CP_BLIT_1_SRC_Y1(val): return (val << CP_BLIT_1_SRC_Y1__SHIFT) & CP_BLIT_1_SRC_Y1__MASK
def CP_BLIT_2_SRC_X2(val): return (val << CP_BLIT_2_SRC_X2__SHIFT) & CP_BLIT_2_SRC_X2__MASK
def CP_BLIT_2_SRC_Y2(val): return (val << CP_BLIT_2_SRC_Y2__SHIFT) & CP_BLIT_2_SRC_Y2__MASK
def CP_BLIT_3_DST_X1(val): return (val << CP_BLIT_3_DST_X1__SHIFT) & CP_BLIT_3_DST_X1__MASK
def CP_BLIT_3_DST_Y1(val): return (val << CP_BLIT_3_DST_Y1__SHIFT) & CP_BLIT_3_DST_Y1__MASK
def CP_BLIT_4_DST_X2(val): return (val << CP_BLIT_4_DST_X2__SHIFT) & CP_BLIT_4_DST_X2__MASK
def CP_BLIT_4_DST_Y2(val): return (val << CP_BLIT_4_DST_Y2__SHIFT) & CP_BLIT_4_DST_Y2__MASK
def CP_EXEC_CS_1_NGROUPS_X(val): return (val << CP_EXEC_CS_1_NGROUPS_X__SHIFT) & CP_EXEC_CS_1_NGROUPS_X__MASK
def CP_EXEC_CS_2_NGROUPS_Y(val): return (val << CP_EXEC_CS_2_NGROUPS_Y__SHIFT) & CP_EXEC_CS_2_NGROUPS_Y__MASK
def CP_EXEC_CS_3_NGROUPS_Z(val): return (val << CP_EXEC_CS_3_NGROUPS_Z__SHIFT) & CP_EXEC_CS_3_NGROUPS_Z__MASK
def A4XX_CP_EXEC_CS_INDIRECT_1_ADDR(val): return (val << A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__MASK
def A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX(val): return (val << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__MASK
def A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY(val): return (val << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__MASK
def A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ(val): return (val << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__MASK
def A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO(val): return (val << A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__MASK
def A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI(val): return (val << A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__MASK
def A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(val): return (val << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__MASK
def A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(val): return (val << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__MASK
def A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(val): return (val << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__MASK
def A6XX_CP_SET_MARKER_0_MODE(val): return (val << A6XX_CP_SET_MARKER_0_MODE__SHIFT) & A6XX_CP_SET_MARKER_0_MODE__MASK
def A6XX_CP_SET_MARKER_0_MARKER(val): return (val << A6XX_CP_SET_MARKER_0_MARKER__SHIFT) & A6XX_CP_SET_MARKER_0_MARKER__MASK
def A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG(val): return (val << A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__SHIFT) & A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__MASK
def A6XX_CP_SET_PSEUDO_REG__1_LO(val): return (val << A6XX_CP_SET_PSEUDO_REG__1_LO__SHIFT) & A6XX_CP_SET_PSEUDO_REG__1_LO__MASK
def A6XX_CP_SET_PSEUDO_REG__2_HI(val): return (val << A6XX_CP_SET_PSEUDO_REG__2_HI__SHIFT) & A6XX_CP_SET_PSEUDO_REG__2_HI__MASK
def A6XX_CP_REG_TEST_0_REG(val): return (val << A6XX_CP_REG_TEST_0_REG__SHIFT) & A6XX_CP_REG_TEST_0_REG__MASK
def A6XX_CP_REG_TEST_0_SCRATCH_MEM_OFFSET(val): return (val << A6XX_CP_REG_TEST_0_SCRATCH_MEM_OFFSET__SHIFT) & A6XX_CP_REG_TEST_0_SCRATCH_MEM_OFFSET__MASK
def A6XX_CP_REG_TEST_0_SOURCE(val): return (val << A6XX_CP_REG_TEST_0_SOURCE__SHIFT) & A6XX_CP_REG_TEST_0_SOURCE__MASK
def A6XX_CP_REG_TEST_0_BIT(val): return (val << A6XX_CP_REG_TEST_0_BIT__SHIFT) & A6XX_CP_REG_TEST_0_BIT__MASK
def A6XX_CP_REG_TEST_0_PRED_BIT(val): return (val << A6XX_CP_REG_TEST_0_PRED_BIT__SHIFT) & A6XX_CP_REG_TEST_0_PRED_BIT__MASK
def CP_COND_REG_EXEC_0_REG0(val): return (val << CP_COND_REG_EXEC_0_REG0__SHIFT) & CP_COND_REG_EXEC_0_REG0__MASK
def CP_COND_REG_EXEC_0_PRED_BIT(val): return (val << CP_COND_REG_EXEC_0_PRED_BIT__SHIFT) & CP_COND_REG_EXEC_0_PRED_BIT__MASK
def CP_COND_REG_EXEC_0_MODE(val): return (val << CP_COND_REG_EXEC_0_MODE__SHIFT) & CP_COND_REG_EXEC_0_MODE__MASK
def PRED_TEST_CP_COND_REG_EXEC_1_DWORDS(val): return (val << PRED_TEST_CP_COND_REG_EXEC_1_DWORDS__SHIFT) & PRED_TEST_CP_COND_REG_EXEC_1_DWORDS__MASK
def REG_COMPARE_CP_COND_REG_EXEC_1_REG1(val): return (val << REG_COMPARE_CP_COND_REG_EXEC_1_REG1__SHIFT) & REG_COMPARE_CP_COND_REG_EXEC_1_REG1__MASK
def RENDER_MODE_CP_COND_REG_EXEC_1_DWORDS(val): return (val << RENDER_MODE_CP_COND_REG_EXEC_1_DWORDS__SHIFT) & RENDER_MODE_CP_COND_REG_EXEC_1_DWORDS__MASK
def REG_COMPARE_IMM_CP_COND_REG_EXEC_1_IMM(val): return (val << REG_COMPARE_IMM_CP_COND_REG_EXEC_1_IMM__SHIFT) & REG_COMPARE_IMM_CP_COND_REG_EXEC_1_IMM__MASK
def THREAD_MODE_CP_COND_REG_EXEC_1_DWORDS(val): return (val << THREAD_MODE_CP_COND_REG_EXEC_1_DWORDS__SHIFT) & THREAD_MODE_CP_COND_REG_EXEC_1_DWORDS__MASK
def CP_COND_REG_EXEC_2_DWORDS(val): return (val << CP_COND_REG_EXEC_2_DWORDS__SHIFT) & CP_COND_REG_EXEC_2_DWORDS__MASK
def CP_COND_EXEC_0_ADDR0_LO(val): return (val << CP_COND_EXEC_0_ADDR0_LO__SHIFT) & CP_COND_EXEC_0_ADDR0_LO__MASK
def CP_COND_EXEC_1_ADDR0_HI(val): return (val << CP_COND_EXEC_1_ADDR0_HI__SHIFT) & CP_COND_EXEC_1_ADDR0_HI__MASK
def CP_COND_EXEC_2_ADDR1_LO(val): return (val << CP_COND_EXEC_2_ADDR1_LO__SHIFT) & CP_COND_EXEC_2_ADDR1_LO__MASK
def CP_COND_EXEC_3_ADDR1_HI(val): return (val << CP_COND_EXEC_3_ADDR1_HI__SHIFT) & CP_COND_EXEC_3_ADDR1_HI__MASK
def CP_COND_EXEC_4_REF(val): return (val << CP_COND_EXEC_4_REF__SHIFT) & CP_COND_EXEC_4_REF__MASK
def CP_COND_EXEC_5_DWORDS(val): return (val << CP_COND_EXEC_5_DWORDS__SHIFT) & CP_COND_EXEC_5_DWORDS__MASK
def CP_SET_CTXSWITCH_IB_0_ADDR_LO(val): return (val << CP_SET_CTXSWITCH_IB_0_ADDR_LO__SHIFT) & CP_SET_CTXSWITCH_IB_0_ADDR_LO__MASK
def CP_SET_CTXSWITCH_IB_1_ADDR_HI(val): return (val << CP_SET_CTXSWITCH_IB_1_ADDR_HI__SHIFT) & CP_SET_CTXSWITCH_IB_1_ADDR_HI__MASK
def CP_SET_CTXSWITCH_IB_2_DWORDS(val): return (val << CP_SET_CTXSWITCH_IB_2_DWORDS__SHIFT) & CP_SET_CTXSWITCH_IB_2_DWORDS__MASK
def CP_SET_CTXSWITCH_IB_2_TYPE(val): return (val << CP_SET_CTXSWITCH_IB_2_TYPE__SHIFT) & CP_SET_CTXSWITCH_IB_2_TYPE__MASK
def CP_REG_WRITE_0_TRACKER(val): return (val << CP_REG_WRITE_0_TRACKER__SHIFT) & CP_REG_WRITE_0_TRACKER__MASK
def CP_SMMU_TABLE_UPDATE_0_TTBR0_LO(val): return (val << CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__SHIFT) & CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__MASK
def CP_SMMU_TABLE_UPDATE_1_TTBR0_HI(val): return (val << CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__SHIFT) & CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__MASK
def CP_SMMU_TABLE_UPDATE_1_ASID(val): return (val << CP_SMMU_TABLE_UPDATE_1_ASID__SHIFT) & CP_SMMU_TABLE_UPDATE_1_ASID__MASK
def CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR(val): return (val << CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__SHIFT) & CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__MASK
def CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK(val): return (val << CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__SHIFT) & CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__MASK
def CP_WAIT_TIMESTAMP_0_WAIT_VALUE_SRC(val): return (val << CP_WAIT_TIMESTAMP_0_WAIT_VALUE_SRC__SHIFT) & CP_WAIT_TIMESTAMP_0_WAIT_VALUE_SRC__MASK
def CP_WAIT_TIMESTAMP_0_WAIT_DST(val): return (val << CP_WAIT_TIMESTAMP_0_WAIT_DST__SHIFT) & CP_WAIT_TIMESTAMP_0_WAIT_DST__MASK
def CP_BV_BR_COUNT_OPS_0_OP(val): return (val << CP_BV_BR_COUNT_OPS_0_OP__SHIFT) & CP_BV_BR_COUNT_OPS_0_OP__MASK
def CP_BV_BR_COUNT_OPS_1_BR_OFFSET(val): return (val << CP_BV_BR_COUNT_OPS_1_BR_OFFSET__SHIFT) & CP_BV_BR_COUNT_OPS_1_BR_OFFSET__MASK
def CP_MODIFY_TIMESTAMP_0_ADD(val): return (val << CP_MODIFY_TIMESTAMP_0_ADD__SHIFT) & CP_MODIFY_TIMESTAMP_0_ADD__MASK
def CP_MODIFY_TIMESTAMP_0_OP(val): return (val << CP_MODIFY_TIMESTAMP_0_OP__SHIFT) & CP_MODIFY_TIMESTAMP_0_OP__MASK
def CP_MEM_TO_SCRATCH_MEM_0_CNT(val): return (val << CP_MEM_TO_SCRATCH_MEM_0_CNT__SHIFT) & CP_MEM_TO_SCRATCH_MEM_0_CNT__MASK
def CP_MEM_TO_SCRATCH_MEM_1_OFFSET(val): return (val << CP_MEM_TO_SCRATCH_MEM_1_OFFSET__SHIFT) & CP_MEM_TO_SCRATCH_MEM_1_OFFSET__MASK
def CP_MEM_TO_SCRATCH_MEM_2_SRC(val): return (val << CP_MEM_TO_SCRATCH_MEM_2_SRC__SHIFT) & CP_MEM_TO_SCRATCH_MEM_2_SRC__MASK
def CP_MEM_TO_SCRATCH_MEM_3_SRC_HI(val): return (val << CP_MEM_TO_SCRATCH_MEM_3_SRC_HI__SHIFT) & CP_MEM_TO_SCRATCH_MEM_3_SRC_HI__MASK
def CP_THREAD_CONTROL_0_THREAD(val): return (val << CP_THREAD_CONTROL_0_THREAD__SHIFT) & CP_THREAD_CONTROL_0_THREAD__MASK
def CP_FIXED_STRIDE_DRAW_TABLE_2_IB_SIZE(val): return (val << CP_FIXED_STRIDE_DRAW_TABLE_2_IB_SIZE__SHIFT) & CP_FIXED_STRIDE_DRAW_TABLE_2_IB_SIZE__MASK
def CP_FIXED_STRIDE_DRAW_TABLE_2_STRIDE(val): return (val << CP_FIXED_STRIDE_DRAW_TABLE_2_STRIDE__SHIFT) & CP_FIXED_STRIDE_DRAW_TABLE_2_STRIDE__MASK
def CP_FIXED_STRIDE_DRAW_TABLE_3_COUNT(val): return (val << CP_FIXED_STRIDE_DRAW_TABLE_3_COUNT__SHIFT) & CP_FIXED_STRIDE_DRAW_TABLE_3_COUNT__MASK
def AXXX_CP_RB_CNTL_BUFSZ(val): return (val << AXXX_CP_RB_CNTL_BUFSZ__SHIFT) & AXXX_CP_RB_CNTL_BUFSZ__MASK
def AXXX_CP_RB_CNTL_BLKSZ(val): return (val << AXXX_CP_RB_CNTL_BLKSZ__SHIFT) & AXXX_CP_RB_CNTL_BLKSZ__MASK
def AXXX_CP_RB_CNTL_BUF_SWAP(val): return (val << AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT) & AXXX_CP_RB_CNTL_BUF_SWAP__MASK
def AXXX_CP_RB_RPTR_ADDR_SWAP(val): return (val << AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT) & AXXX_CP_RB_RPTR_ADDR_SWAP__MASK
def AXXX_CP_RB_RPTR_ADDR_ADDR(val): return (val << AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT) & AXXX_CP_RB_RPTR_ADDR_ADDR__MASK
def AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START(val): return (val << AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__MASK
def AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START(val): return (val << AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__MASK
def AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START(val): return (val << AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__MASK
def AXXX_CP_MEQ_THRESHOLDS_MEQ_END(val): return (val << AXXX_CP_MEQ_THRESHOLDS_MEQ_END__SHIFT) & AXXX_CP_MEQ_THRESHOLDS_MEQ_END__MASK
def AXXX_CP_MEQ_THRESHOLDS_ROQ_END(val): return (val << AXXX_CP_MEQ_THRESHOLDS_ROQ_END__SHIFT) & AXXX_CP_MEQ_THRESHOLDS_ROQ_END__MASK
def AXXX_CP_CSQ_AVAIL_RING(val): return (val << AXXX_CP_CSQ_AVAIL_RING__SHIFT) & AXXX_CP_CSQ_AVAIL_RING__MASK
def AXXX_CP_CSQ_AVAIL_IB1(val): return (val << AXXX_CP_CSQ_AVAIL_IB1__SHIFT) & AXXX_CP_CSQ_AVAIL_IB1__MASK
def AXXX_CP_CSQ_AVAIL_IB2(val): return (val << AXXX_CP_CSQ_AVAIL_IB2__SHIFT) & AXXX_CP_CSQ_AVAIL_IB2__MASK
def AXXX_CP_STQ_AVAIL_ST(val): return (val << AXXX_CP_STQ_AVAIL_ST__SHIFT) & AXXX_CP_STQ_AVAIL_ST__MASK
def AXXX_CP_MEQ_AVAIL_MEQ(val): return (val << AXXX_CP_MEQ_AVAIL_MEQ__SHIFT) & AXXX_CP_MEQ_AVAIL_MEQ__MASK
def AXXX_SCRATCH_UMSK_UMSK(val): return (val << AXXX_SCRATCH_UMSK_UMSK__SHIFT) & AXXX_SCRATCH_UMSK_UMSK__MASK
def AXXX_SCRATCH_UMSK_SWAP(val): return (val << AXXX_SCRATCH_UMSK_SWAP__SHIFT) & AXXX_SCRATCH_UMSK_SWAP__MASK
def AXXX_CP_CSQ_RB_STAT_RPTR(val): return (val << AXXX_CP_CSQ_RB_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_RB_STAT_RPTR__MASK
def AXXX_CP_CSQ_RB_STAT_WPTR(val): return (val << AXXX_CP_CSQ_RB_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_RB_STAT_WPTR__MASK
def AXXX_CP_CSQ_IB1_STAT_RPTR(val): return (val << AXXX_CP_CSQ_IB1_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_IB1_STAT_RPTR__MASK
def AXXX_CP_CSQ_IB1_STAT_WPTR(val): return (val << AXXX_CP_CSQ_IB1_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_IB1_STAT_WPTR__MASK
def AXXX_CP_CSQ_IB2_STAT_RPTR(val): return (val << AXXX_CP_CSQ_IB2_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_IB2_STAT_RPTR__MASK
def AXXX_CP_CSQ_IB2_STAT_WPTR(val): return (val << AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_IB2_STAT_WPTR__MASK
def A6XX_CP_ROQ_THRESHOLDS_1_MRB_START(val): return (val << A6XX_CP_ROQ_THRESHOLDS_1_MRB_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_MRB_START__MASK
def A6XX_CP_ROQ_THRESHOLDS_1_VSD_START(val): return (val << A6XX_CP_ROQ_THRESHOLDS_1_VSD_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_VSD_START__MASK
def A6XX_CP_ROQ_THRESHOLDS_1_IB1_START(val): return (val << A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__MASK
def A6XX_CP_ROQ_THRESHOLDS_1_IB2_START(val): return (val << A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__MASK
def A6XX_CP_ROQ_THRESHOLDS_2_SDS_START(val): return (val << A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__MASK
def A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE(val): return (val << A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__MASK
def A6XX_CP_PROTECT_REG_BASE_ADDR(val): return (val << A6XX_CP_PROTECT_REG_BASE_ADDR__SHIFT) & A6XX_CP_PROTECT_REG_BASE_ADDR__MASK
def A6XX_CP_PROTECT_REG_MASK_LEN(val): return (val << A6XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A6XX_CP_PROTECT_REG_MASK_LEN__MASK
def A6XX_CP_ROQ_RB_STAT_RPTR(val): return (val << A6XX_CP_ROQ_RB_STAT_RPTR__SHIFT) & A6XX_CP_ROQ_RB_STAT_RPTR__MASK
def A6XX_CP_ROQ_RB_STAT_WPTR(val): return (val << A6XX_CP_ROQ_RB_STAT_WPTR__SHIFT) & A6XX_CP_ROQ_RB_STAT_WPTR__MASK
def A6XX_CP_ROQ_IB1_STAT_RPTR(val): return (val << A6XX_CP_ROQ_IB1_STAT_RPTR__SHIFT) & A6XX_CP_ROQ_IB1_STAT_RPTR__MASK
def A6XX_CP_ROQ_IB1_STAT_WPTR(val): return (val << A6XX_CP_ROQ_IB1_STAT_WPTR__SHIFT) & A6XX_CP_ROQ_IB1_STAT_WPTR__MASK
def A6XX_CP_ROQ_IB2_STAT_RPTR(val): return (val << A6XX_CP_ROQ_IB2_STAT_RPTR__SHIFT) & A6XX_CP_ROQ_IB2_STAT_RPTR__MASK
def A6XX_CP_ROQ_IB2_STAT_WPTR(val): return (val << A6XX_CP_ROQ_IB2_STAT_WPTR__SHIFT) & A6XX_CP_ROQ_IB2_STAT_WPTR__MASK
def A6XX_CP_ROQ_SDS_STAT_RPTR(val): return (val << A6XX_CP_ROQ_SDS_STAT_RPTR__SHIFT) & A6XX_CP_ROQ_SDS_STAT_RPTR__MASK
def A6XX_CP_ROQ_SDS_STAT_WPTR(val): return (val << A6XX_CP_ROQ_SDS_STAT_WPTR__SHIFT) & A6XX_CP_ROQ_SDS_STAT_WPTR__MASK
def A6XX_CP_ROQ_MRB_STAT_RPTR(val): return (val << A6XX_CP_ROQ_MRB_STAT_RPTR__SHIFT) & A6XX_CP_ROQ_MRB_STAT_RPTR__MASK
def A6XX_CP_ROQ_MRB_STAT_WPTR(val): return (val << A6XX_CP_ROQ_MRB_STAT_WPTR__SHIFT) & A6XX_CP_ROQ_MRB_STAT_WPTR__MASK
def A6XX_CP_ROQ_VSD_STAT_RPTR(val): return (val << A6XX_CP_ROQ_VSD_STAT_RPTR__SHIFT) & A6XX_CP_ROQ_VSD_STAT_RPTR__MASK
def A6XX_CP_ROQ_VSD_STAT_WPTR(val): return (val << A6XX_CP_ROQ_VSD_STAT_WPTR__SHIFT) & A6XX_CP_ROQ_VSD_STAT_WPTR__MASK
def A6XX_CP_ROQ_AVAIL_RB_REM(val): return (val << A6XX_CP_ROQ_AVAIL_RB_REM__SHIFT) & A6XX_CP_ROQ_AVAIL_RB_REM__MASK
def A6XX_CP_ROQ_AVAIL_IB1_REM(val): return (val << A6XX_CP_ROQ_AVAIL_IB1_REM__SHIFT) & A6XX_CP_ROQ_AVAIL_IB1_REM__MASK
def A6XX_CP_ROQ_AVAIL_IB2_REM(val): return (val << A6XX_CP_ROQ_AVAIL_IB2_REM__SHIFT) & A6XX_CP_ROQ_AVAIL_IB2_REM__MASK
def A6XX_CP_ROQ_AVAIL_SDS_REM(val): return (val << A6XX_CP_ROQ_AVAIL_SDS_REM__SHIFT) & A6XX_CP_ROQ_AVAIL_SDS_REM__MASK
def A6XX_CP_ROQ_AVAIL_MRB_REM(val): return (val << A6XX_CP_ROQ_AVAIL_MRB_REM__SHIFT) & A6XX_CP_ROQ_AVAIL_MRB_REM__MASK
def A6XX_CP_ROQ_AVAIL_VSD_REM(val): return (val << A6XX_CP_ROQ_AVAIL_VSD_REM__SHIFT) & A6XX_CP_ROQ_AVAIL_VSD_REM__MASK
def A7XX_CP_APERTURE_CNTL_HOST_PIPE(val): return (val << A7XX_CP_APERTURE_CNTL_HOST_PIPE__SHIFT) & A7XX_CP_APERTURE_CNTL_HOST_PIPE__MASK
def A7XX_CP_APERTURE_CNTL_HOST_CLUSTER(val): return (val << A7XX_CP_APERTURE_CNTL_HOST_CLUSTER__SHIFT) & A7XX_CP_APERTURE_CNTL_HOST_CLUSTER__MASK
def A7XX_CP_APERTURE_CNTL_HOST_CONTEXT(val): return (val << A7XX_CP_APERTURE_CNTL_HOST_CONTEXT__SHIFT) & A7XX_CP_APERTURE_CNTL_HOST_CONTEXT__MASK
def A7XX_CP_APERTURE_CNTL_CD_PIPE(val): return (val << A7XX_CP_APERTURE_CNTL_CD_PIPE__SHIFT) & A7XX_CP_APERTURE_CNTL_CD_PIPE__MASK
def A7XX_CP_APERTURE_CNTL_CD_CLUSTER(val): return (val << A7XX_CP_APERTURE_CNTL_CD_CLUSTER__SHIFT) & A7XX_CP_APERTURE_CNTL_CD_CLUSTER__MASK
def A7XX_CP_APERTURE_CNTL_CD_CONTEXT(val): return (val << A7XX_CP_APERTURE_CNTL_CD_CONTEXT__SHIFT) & A7XX_CP_APERTURE_CNTL_CD_CONTEXT__MASK
def A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX(val): return (val << A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__SHIFT) & A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__MASK
def A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL(val): return (val << A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__SHIFT) & A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__MASK
def A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN(val): return (val << A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK
def A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU(val): return (val << A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK
def A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT(val): return (val << A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK
def A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(val): return (val << A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK
def A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0(val): return (val << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK
def A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1(val): return (val << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK
def A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2(val): return (val << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK
def A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3(val): return (val << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK
def A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4(val): return (val << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK
def A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5(val): return (val << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK
def A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6(val): return (val << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK
def A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7(val): return (val << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK
def A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8(val): return (val << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK
def A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9(val): return (val << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK
def A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10(val): return (val << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK
def A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11(val): return (val << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK
def A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12(val): return (val << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK
def A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13(val): return (val << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK
def A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14(val): return (val << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK
def A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(val): return (val << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK
def A6XX_UCHE_CLIENT_PF_PERFSEL(val): return (val << A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT) & A6XX_UCHE_CLIENT_PF_PERFSEL__MASK
def A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL(val): return (val << A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__SHIFT) & A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__MASK
def A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL(val): return (val << A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__SHIFT) & A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__MASK
def A6XX_VSC_BIN_SIZE_WIDTH(val): return (val << A6XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A6XX_VSC_BIN_SIZE_WIDTH__MASK
def A6XX_VSC_BIN_SIZE_HEIGHT(val): return (val << A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A6XX_VSC_BIN_SIZE_HEIGHT__MASK
def A6XX_VSC_BIN_COUNT_NX(val): return (val << A6XX_VSC_BIN_COUNT_NX__SHIFT) & A6XX_VSC_BIN_COUNT_NX__MASK
def A6XX_VSC_BIN_COUNT_NY(val): return (val << A6XX_VSC_BIN_COUNT_NY__SHIFT) & A6XX_VSC_BIN_COUNT_NY__MASK
def A6XX_VSC_PIPE_CONFIG_REG_X(val): return (val << A6XX_VSC_PIPE_CONFIG_REG_X__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_X__MASK
def A6XX_VSC_PIPE_CONFIG_REG_Y(val): return (val << A6XX_VSC_PIPE_CONFIG_REG_Y__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_Y__MASK
def A6XX_VSC_PIPE_CONFIG_REG_W(val): return (val << A6XX_VSC_PIPE_CONFIG_REG_W__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_W__MASK
def A6XX_VSC_PIPE_CONFIG_REG_H(val): return (val << A6XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_H__MASK
def A6XX_GRAS_VS_CL_CNTL_CLIP_MASK(val): return (val << A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__SHIFT) & A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__MASK
def A6XX_GRAS_VS_CL_CNTL_CULL_MASK(val): return (val << A6XX_GRAS_VS_CL_CNTL_CULL_MASK__SHIFT) & A6XX_GRAS_VS_CL_CNTL_CULL_MASK__MASK
def A6XX_GRAS_DS_CL_CNTL_CLIP_MASK(val): return (val << A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__SHIFT) & A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__MASK
def A6XX_GRAS_DS_CL_CNTL_CULL_MASK(val): return (val << A6XX_GRAS_DS_CL_CNTL_CULL_MASK__SHIFT) & A6XX_GRAS_DS_CL_CNTL_CULL_MASK__MASK
def A6XX_GRAS_GS_CL_CNTL_CLIP_MASK(val): return (val << A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__SHIFT) & A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__MASK
def A6XX_GRAS_GS_CL_CNTL_CULL_MASK(val): return (val << A6XX_GRAS_GS_CL_CNTL_CULL_MASK__SHIFT) & A6XX_GRAS_GS_CL_CNTL_CULL_MASK__MASK
def A6XX_GRAS_CNTL_COORD_MASK(val): return (val << A6XX_GRAS_CNTL_COORD_MASK__SHIFT) & A6XX_GRAS_CNTL_COORD_MASK__MASK
def A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(val): return (val << A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT) & A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK
def A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(val): return (val << A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT) & A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK
def A6XX_GRAS_CL_VPORT_XOFFSET(val): return (val << A6XX_GRAS_CL_VPORT_XOFFSET__SHIFT) & A6XX_GRAS_CL_VPORT_XOFFSET__MASK
def A6XX_GRAS_CL_VPORT_XSCALE(val): return (val << A6XX_GRAS_CL_VPORT_XSCALE__SHIFT) & A6XX_GRAS_CL_VPORT_XSCALE__MASK
def A6XX_GRAS_CL_VPORT_YOFFSET(val): return (val << A6XX_GRAS_CL_VPORT_YOFFSET__SHIFT) & A6XX_GRAS_CL_VPORT_YOFFSET__MASK
def A6XX_GRAS_CL_VPORT_YSCALE(val): return (val << A6XX_GRAS_CL_VPORT_YSCALE__SHIFT) & A6XX_GRAS_CL_VPORT_YSCALE__MASK
def A6XX_GRAS_CL_VPORT_ZOFFSET(val): return (val << A6XX_GRAS_CL_VPORT_ZOFFSET__SHIFT) & A6XX_GRAS_CL_VPORT_ZOFFSET__MASK
def A6XX_GRAS_CL_VPORT_ZSCALE(val): return (val << A6XX_GRAS_CL_VPORT_ZSCALE__SHIFT) & A6XX_GRAS_CL_VPORT_ZSCALE__MASK
def A6XX_GRAS_CL_Z_CLAMP_MIN(val): return (val << A6XX_GRAS_CL_Z_CLAMP_MIN__SHIFT) & A6XX_GRAS_CL_Z_CLAMP_MIN__MASK
def A6XX_GRAS_CL_Z_CLAMP_MAX(val): return (val << A6XX_GRAS_CL_Z_CLAMP_MAX__SHIFT) & A6XX_GRAS_CL_Z_CLAMP_MAX__MASK
def A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(val): return (val << A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT) & A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK
def A6XX_GRAS_SU_CNTL_LINE_MODE(val): return (val << A6XX_GRAS_SU_CNTL_LINE_MODE__SHIFT) & A6XX_GRAS_SU_CNTL_LINE_MODE__MASK
def A6XX_GRAS_SU_CNTL_UNK15(val): return (val << A6XX_GRAS_SU_CNTL_UNK15__SHIFT) & A6XX_GRAS_SU_CNTL_UNK15__MASK
def A6XX_GRAS_SU_CNTL_UNK20(val): return (val << A6XX_GRAS_SU_CNTL_UNK20__SHIFT) & A6XX_GRAS_SU_CNTL_UNK20__MASK
def A6XX_GRAS_SU_POINT_MINMAX_MIN(val): return (val << A6XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A6XX_GRAS_SU_POINT_MINMAX_MIN__MASK
def A6XX_GRAS_SU_POINT_MINMAX_MAX(val): return (val << A6XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A6XX_GRAS_SU_POINT_MINMAX_MAX__MASK
def A6XX_GRAS_SU_POINT_SIZE(val): return (val << A6XX_GRAS_SU_POINT_SIZE__SHIFT) & A6XX_GRAS_SU_POINT_SIZE__MASK
def A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE(val): return (val << A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__SHIFT) & A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__MASK
def A6XX_GRAS_SU_POLY_OFFSET_SCALE(val): return (val << A6XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_SCALE__MASK
def A6XX_GRAS_SU_POLY_OFFSET_OFFSET(val): return (val << A6XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK
def A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(val): return (val << A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK
def A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(val): return (val << A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK
def A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT(val): return (val << A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT__SHIFT) & A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT__MASK
def A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4(val): return (val << A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4__SHIFT) & A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4__MASK
def A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE(val): return (val << A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE__SHIFT) & A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE__MASK
def A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE(val): return (val << A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE__SHIFT) & A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE__MASK
def A6XX_GRAS_SC_CNTL_RASTER_MODE(val): return (val << A6XX_GRAS_SC_CNTL_RASTER_MODE__SHIFT) & A6XX_GRAS_SC_CNTL_RASTER_MODE__MASK
def A6XX_GRAS_SC_CNTL_RASTER_DIRECTION(val): return (val << A6XX_GRAS_SC_CNTL_RASTER_DIRECTION__SHIFT) & A6XX_GRAS_SC_CNTL_RASTER_DIRECTION__MASK
def A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION(val): return (val << A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION__SHIFT) & A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION__MASK
def A6XX_GRAS_SC_CNTL_ROTATION(val): return (val << A6XX_GRAS_SC_CNTL_ROTATION__SHIFT) & A6XX_GRAS_SC_CNTL_ROTATION__MASK
def A6XX_GRAS_BIN_CONTROL_BINW(val): return (val << A6XX_GRAS_BIN_CONTROL_BINW__SHIFT) & A6XX_GRAS_BIN_CONTROL_BINW__MASK
def A6XX_GRAS_BIN_CONTROL_BINH(val): return (val << A6XX_GRAS_BIN_CONTROL_BINH__SHIFT) & A6XX_GRAS_BIN_CONTROL_BINH__MASK
def A6XX_GRAS_BIN_CONTROL_RENDER_MODE(val): return (val << A6XX_GRAS_BIN_CONTROL_RENDER_MODE__SHIFT) & A6XX_GRAS_BIN_CONTROL_RENDER_MODE__MASK
def A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION(val): return (val << A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION__SHIFT) & A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION__MASK
def A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK(val): return (val << A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT) & A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK
def A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES(val): return (val << A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__MASK
def A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES(val): return (val << A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__MASK
def A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X(val): return (val << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK
def A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y(val): return (val << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK
def A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X(val): return (val << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK
def A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y(val): return (val << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK
def A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X(val): return (val << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK
def A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y(val): return (val << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK
def A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X(val): return (val << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK
def A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y(val): return (val << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK
def A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X(val): return (val << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK
def A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y(val): return (val << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK
def A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X(val): return (val << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK
def A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y(val): return (val << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK
def A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X(val): return (val << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK
def A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y(val): return (val << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK
def A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X(val): return (val << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK
def A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y(val): return (val << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK
def A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X(val): return (val << A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK
def A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(val): return (val << A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK
def A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X(val): return (val << A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK
def A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(val): return (val << A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK
def A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X(val): return (val << A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__MASK
def A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y(val): return (val << A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__MASK
def A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X(val): return (val << A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__MASK
def A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y(val): return (val << A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__MASK
def A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X(val): return (val << A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK
def A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(val): return (val << A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK
def A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X(val): return (val << A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK
def A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(val): return (val << A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK
def A6XX_GRAS_LRZ_CNTL_DIR(val): return (val << A6XX_GRAS_LRZ_CNTL_DIR__SHIFT) & A6XX_GRAS_LRZ_CNTL_DIR__MASK
def A6XX_GRAS_LRZ_CNTL_Z_FUNC(val): return (val << A6XX_GRAS_LRZ_CNTL_Z_FUNC__SHIFT) & A6XX_GRAS_LRZ_CNTL_Z_FUNC__MASK
def A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE(val): return (val << A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE__SHIFT) & A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE__MASK
def A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT(val): return (val << A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT__SHIFT) & A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT__MASK
def A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH(val): return (val << A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__SHIFT) & A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__MASK
def A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH(val): return (val << A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK
def A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_LAYER(val): return (val << A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_LAYER__SHIFT) & A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_LAYER__MASK
def A6XX_GRAS_LRZ_DEPTH_VIEW_LAYER_COUNT(val): return (val << A6XX_GRAS_LRZ_DEPTH_VIEW_LAYER_COUNT__SHIFT) & A6XX_GRAS_LRZ_DEPTH_VIEW_LAYER_COUNT__MASK
def A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_MIP_LEVEL(val): return (val << A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_MIP_LEVEL__SHIFT) & A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_MIP_LEVEL__MASK
def A7XX_GRAS_LRZ_CLEAR_DEPTH_F32(val): return (val << A7XX_GRAS_LRZ_CLEAR_DEPTH_F32__SHIFT) & A7XX_GRAS_LRZ_CLEAR_DEPTH_F32__MASK
def A7XX_GRAS_LRZ_DEPTH_BUFFER_INFO_DEPTH_FORMAT(val): return (val << A7XX_GRAS_LRZ_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A7XX_GRAS_LRZ_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK
def A6XX_GRAS_2D_BLIT_CNTL_ROTATE(val): return (val << A6XX_GRAS_2D_BLIT_CNTL_ROTATE__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_ROTATE__MASK
def A6XX_GRAS_2D_BLIT_CNTL_UNK4(val): return (val << A6XX_GRAS_2D_BLIT_CNTL_UNK4__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_UNK4__MASK
def A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT(val): return (val << A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__MASK
def A6XX_GRAS_2D_BLIT_CNTL_UNK17(val): return (val << A6XX_GRAS_2D_BLIT_CNTL_UNK17__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_UNK17__MASK
def A6XX_GRAS_2D_BLIT_CNTL_MASK(val): return (val << A6XX_GRAS_2D_BLIT_CNTL_MASK__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_MASK__MASK
def A6XX_GRAS_2D_BLIT_CNTL_IFMT(val): return (val << A6XX_GRAS_2D_BLIT_CNTL_IFMT__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_IFMT__MASK
def A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE(val): return (val << A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE__MASK
def A6XX_GRAS_2D_SRC_TL_X(val): return (val << A6XX_GRAS_2D_SRC_TL_X__SHIFT) & A6XX_GRAS_2D_SRC_TL_X__MASK
def A6XX_GRAS_2D_SRC_BR_X(val): return (val << A6XX_GRAS_2D_SRC_BR_X__SHIFT) & A6XX_GRAS_2D_SRC_BR_X__MASK
def A6XX_GRAS_2D_SRC_TL_Y(val): return (val << A6XX_GRAS_2D_SRC_TL_Y__SHIFT) & A6XX_GRAS_2D_SRC_TL_Y__MASK
def A6XX_GRAS_2D_SRC_BR_Y(val): return (val << A6XX_GRAS_2D_SRC_BR_Y__SHIFT) & A6XX_GRAS_2D_SRC_BR_Y__MASK
def A6XX_GRAS_2D_DST_TL_X(val): return (val << A6XX_GRAS_2D_DST_TL_X__SHIFT) & A6XX_GRAS_2D_DST_TL_X__MASK
def A6XX_GRAS_2D_DST_TL_Y(val): return (val << A6XX_GRAS_2D_DST_TL_Y__SHIFT) & A6XX_GRAS_2D_DST_TL_Y__MASK
def A6XX_GRAS_2D_DST_BR_X(val): return (val << A6XX_GRAS_2D_DST_BR_X__SHIFT) & A6XX_GRAS_2D_DST_BR_X__MASK
def A6XX_GRAS_2D_DST_BR_Y(val): return (val << A6XX_GRAS_2D_DST_BR_Y__SHIFT) & A6XX_GRAS_2D_DST_BR_Y__MASK
def A6XX_GRAS_2D_RESOLVE_CNTL_1_X(val): return (val << A6XX_GRAS_2D_RESOLVE_CNTL_1_X__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_1_X__MASK
def A6XX_GRAS_2D_RESOLVE_CNTL_1_Y(val): return (val << A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__MASK
def A6XX_GRAS_2D_RESOLVE_CNTL_2_X(val): return (val << A6XX_GRAS_2D_RESOLVE_CNTL_2_X__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_2_X__MASK
def A6XX_GRAS_2D_RESOLVE_CNTL_2_Y(val): return (val << A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__MASK
def A6XX_RB_BIN_CONTROL_BINW(val): return (val << A6XX_RB_BIN_CONTROL_BINW__SHIFT) & A6XX_RB_BIN_CONTROL_BINW__MASK
def A6XX_RB_BIN_CONTROL_BINH(val): return (val << A6XX_RB_BIN_CONTROL_BINH__SHIFT) & A6XX_RB_BIN_CONTROL_BINH__MASK
def A6XX_RB_BIN_CONTROL_RENDER_MODE(val): return (val << A6XX_RB_BIN_CONTROL_RENDER_MODE__SHIFT) & A6XX_RB_BIN_CONTROL_RENDER_MODE__MASK
def A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION(val): return (val << A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION__SHIFT) & A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION__MASK
def A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK(val): return (val << A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT) & A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK
def A7XX_RB_BIN_CONTROL_BINW(val): return (val << A7XX_RB_BIN_CONTROL_BINW__SHIFT) & A7XX_RB_BIN_CONTROL_BINW__MASK
def A7XX_RB_BIN_CONTROL_BINH(val): return (val << A7XX_RB_BIN_CONTROL_BINH__SHIFT) & A7XX_RB_BIN_CONTROL_BINH__MASK
def A7XX_RB_BIN_CONTROL_RENDER_MODE(val): return (val << A7XX_RB_BIN_CONTROL_RENDER_MODE__SHIFT) & A7XX_RB_BIN_CONTROL_RENDER_MODE__MASK
def A7XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK(val): return (val << A7XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT) & A7XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK
def A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE(val): return (val << A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE__SHIFT) & A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE__MASK
def A6XX_RB_RENDER_CNTL_UNK8(val): return (val << A6XX_RB_RENDER_CNTL_UNK8__SHIFT) & A6XX_RB_RENDER_CNTL_UNK8__MASK
def A6XX_RB_RENDER_CNTL_RASTER_MODE(val): return (val << A6XX_RB_RENDER_CNTL_RASTER_MODE__SHIFT) & A6XX_RB_RENDER_CNTL_RASTER_MODE__MASK
def A6XX_RB_RENDER_CNTL_RASTER_DIRECTION(val): return (val << A6XX_RB_RENDER_CNTL_RASTER_DIRECTION__SHIFT) & A6XX_RB_RENDER_CNTL_RASTER_DIRECTION__MASK
def A6XX_RB_RENDER_CNTL_FLAG_MRTS(val): return (val << A6XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT) & A6XX_RB_RENDER_CNTL_FLAG_MRTS__MASK
def A7XX_RB_RENDER_CNTL_RASTER_MODE(val): return (val << A7XX_RB_RENDER_CNTL_RASTER_MODE__SHIFT) & A7XX_RB_RENDER_CNTL_RASTER_MODE__MASK
def A7XX_RB_RENDER_CNTL_RASTER_DIRECTION(val): return (val << A7XX_RB_RENDER_CNTL_RASTER_DIRECTION__SHIFT) & A7XX_RB_RENDER_CNTL_RASTER_DIRECTION__MASK
def A6XX_RB_RAS_MSAA_CNTL_SAMPLES(val): return (val << A6XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK
def A6XX_RB_DEST_MSAA_CNTL_SAMPLES(val): return (val << A6XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK
def A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X(val): return (val << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK
def A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y(val): return (val << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK
def A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X(val): return (val << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK
def A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y(val): return (val << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK
def A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X(val): return (val << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK
def A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y(val): return (val << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK
def A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X(val): return (val << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK
def A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y(val): return (val << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK
def A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X(val): return (val << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK
def A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y(val): return (val << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK
def A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X(val): return (val << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK
def A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y(val): return (val << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK
def A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X(val): return (val << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK
def A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y(val): return (val << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK
def A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X(val): return (val << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK
def A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y(val): return (val << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK
def A6XX_RB_RENDER_CONTROL0_COORD_MASK(val): return (val << A6XX_RB_RENDER_CONTROL0_COORD_MASK__SHIFT) & A6XX_RB_RENDER_CONTROL0_COORD_MASK__MASK
def A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE(val): return (val << A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE__SHIFT) & A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE__MASK
def A6XX_RB_FS_OUTPUT_CNTL1_MRT(val): return (val << A6XX_RB_FS_OUTPUT_CNTL1_MRT__SHIFT) & A6XX_RB_FS_OUTPUT_CNTL1_MRT__MASK
def A6XX_RB_RENDER_COMPONENTS_RT0(val): return (val << A6XX_RB_RENDER_COMPONENTS_RT0__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT0__MASK
def A6XX_RB_RENDER_COMPONENTS_RT1(val): return (val << A6XX_RB_RENDER_COMPONENTS_RT1__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT1__MASK
def A6XX_RB_RENDER_COMPONENTS_RT2(val): return (val << A6XX_RB_RENDER_COMPONENTS_RT2__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT2__MASK
def A6XX_RB_RENDER_COMPONENTS_RT3(val): return (val << A6XX_RB_RENDER_COMPONENTS_RT3__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT3__MASK
def A6XX_RB_RENDER_COMPONENTS_RT4(val): return (val << A6XX_RB_RENDER_COMPONENTS_RT4__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT4__MASK
def A6XX_RB_RENDER_COMPONENTS_RT5(val): return (val << A6XX_RB_RENDER_COMPONENTS_RT5__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT5__MASK
def A6XX_RB_RENDER_COMPONENTS_RT6(val): return (val << A6XX_RB_RENDER_COMPONENTS_RT6__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT6__MASK
def A6XX_RB_RENDER_COMPONENTS_RT7(val): return (val << A6XX_RB_RENDER_COMPONENTS_RT7__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT7__MASK
def A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0(val): return (val << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__MASK
def A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1(val): return (val << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__MASK
def A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2(val): return (val << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__MASK
def A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3(val): return (val << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__MASK
def A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4(val): return (val << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__MASK
def A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5(val): return (val << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__MASK
def A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6(val): return (val << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__MASK
def A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7(val): return (val << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__MASK
def A6XX_RB_MRT_CONTROL_ROP_CODE(val): return (val << A6XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A6XX_RB_MRT_CONTROL_ROP_CODE__MASK
def A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE(val): return (val << A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK
def A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(val): return (val << A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK
def A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(val): return (val << A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK
def A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(val): return (val << A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK
def A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(val): return (val << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK
def A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(val): return (val << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK
def A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(val): return (val << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK
def A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT(val): return (val << A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK
def A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(val): return (val << A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK
def A6XX_RB_MRT_BUF_INFO_COLOR_SWAP(val): return (val << A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK
def A7XX_RB_MRT_BUF_INFO_COLOR_FORMAT(val): return (val << A7XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A7XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK
def A7XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(val): return (val << A7XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A7XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK
def A7XX_RB_MRT_BUF_INFO_COLOR_SWAP(val): return (val << A7XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A7XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK
def A6XX_RB_MRT_PITCH(val): return (val << A6XX_RB_MRT_PITCH__SHIFT) & A6XX_RB_MRT_PITCH__MASK
def A6XX_RB_MRT_ARRAY_PITCH(val): return (val << A6XX_RB_MRT_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_ARRAY_PITCH__MASK
def A6XX_RB_BLEND_RED_F32(val): return (val << A6XX_RB_BLEND_RED_F32__SHIFT) & A6XX_RB_BLEND_RED_F32__MASK
def A6XX_RB_BLEND_GREEN_F32(val): return (val << A6XX_RB_BLEND_GREEN_F32__SHIFT) & A6XX_RB_BLEND_GREEN_F32__MASK
def A6XX_RB_BLEND_BLUE_F32(val): return (val << A6XX_RB_BLEND_BLUE_F32__SHIFT) & A6XX_RB_BLEND_BLUE_F32__MASK
def A6XX_RB_BLEND_ALPHA_F32(val): return (val << A6XX_RB_BLEND_ALPHA_F32__SHIFT) & A6XX_RB_BLEND_ALPHA_F32__MASK
def A6XX_RB_ALPHA_CONTROL_ALPHA_REF(val): return (val << A6XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT) & A6XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK
def A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(val): return (val << A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK
def A6XX_RB_BLEND_CNTL_ENABLE_BLEND(val): return (val << A6XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A6XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK
def A6XX_RB_BLEND_CNTL_SAMPLE_MASK(val): return (val << A6XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT) & A6XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK
def A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE(val): return (val << A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__SHIFT) & A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__MASK
def A6XX_RB_DEPTH_CNTL_ZFUNC(val): return (val << A6XX_RB_DEPTH_CNTL_ZFUNC__SHIFT) & A6XX_RB_DEPTH_CNTL_ZFUNC__MASK
def A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(val): return (val << A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK
def A6XX_RB_DEPTH_BUFFER_INFO_UNK3(val): return (val << A6XX_RB_DEPTH_BUFFER_INFO_UNK3__SHIFT) & A6XX_RB_DEPTH_BUFFER_INFO_UNK3__MASK
def A7XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(val): return (val << A7XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A7XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK
def A7XX_RB_DEPTH_BUFFER_INFO_UNK3(val): return (val << A7XX_RB_DEPTH_BUFFER_INFO_UNK3__SHIFT) & A7XX_RB_DEPTH_BUFFER_INFO_UNK3__MASK
def A7XX_RB_DEPTH_BUFFER_INFO_TILEMODE(val): return (val << A7XX_RB_DEPTH_BUFFER_INFO_TILEMODE__SHIFT) & A7XX_RB_DEPTH_BUFFER_INFO_TILEMODE__MASK
def A6XX_RB_DEPTH_BUFFER_PITCH(val): return (val << A6XX_RB_DEPTH_BUFFER_PITCH__SHIFT) & A6XX_RB_DEPTH_BUFFER_PITCH__MASK
def A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(val): return (val << A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK
def A6XX_RB_Z_BOUNDS_MIN(val): return (val << A6XX_RB_Z_BOUNDS_MIN__SHIFT) & A6XX_RB_Z_BOUNDS_MIN__MASK
def A6XX_RB_Z_BOUNDS_MAX(val): return (val << A6XX_RB_Z_BOUNDS_MAX__SHIFT) & A6XX_RB_Z_BOUNDS_MAX__MASK
def A6XX_RB_STENCIL_CONTROL_FUNC(val): return (val << A6XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A6XX_RB_STENCIL_CONTROL_FUNC__MASK
def A6XX_RB_STENCIL_CONTROL_FAIL(val): return (val << A6XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A6XX_RB_STENCIL_CONTROL_FAIL__MASK
def A6XX_RB_STENCIL_CONTROL_ZPASS(val): return (val << A6XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZPASS__MASK
def A6XX_RB_STENCIL_CONTROL_ZFAIL(val): return (val << A6XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZFAIL__MASK
def A6XX_RB_STENCIL_CONTROL_FUNC_BF(val): return (val << A6XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_FUNC_BF__MASK
def A6XX_RB_STENCIL_CONTROL_FAIL_BF(val): return (val << A6XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_FAIL_BF__MASK
def A6XX_RB_STENCIL_CONTROL_ZPASS_BF(val): return (val << A6XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK
def A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(val): return (val << A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK
def A7XX_RB_STENCIL_INFO_TILEMODE(val): return (val << A7XX_RB_STENCIL_INFO_TILEMODE__SHIFT) & A7XX_RB_STENCIL_INFO_TILEMODE__MASK
def A6XX_RB_STENCIL_BUFFER_PITCH(val): return (val << A6XX_RB_STENCIL_BUFFER_PITCH__SHIFT) & A6XX_RB_STENCIL_BUFFER_PITCH__MASK
def A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH(val): return (val << A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK
def A6XX_RB_STENCILREF_REF(val): return (val << A6XX_RB_STENCILREF_REF__SHIFT) & A6XX_RB_STENCILREF_REF__MASK
def A6XX_RB_STENCILREF_BFREF(val): return (val << A6XX_RB_STENCILREF_BFREF__SHIFT) & A6XX_RB_STENCILREF_BFREF__MASK
def A6XX_RB_STENCILMASK_MASK(val): return (val << A6XX_RB_STENCILMASK_MASK__SHIFT) & A6XX_RB_STENCILMASK_MASK__MASK
def A6XX_RB_STENCILMASK_BFMASK(val): return (val << A6XX_RB_STENCILMASK_BFMASK__SHIFT) & A6XX_RB_STENCILMASK_BFMASK__MASK
def A6XX_RB_STENCILWRMASK_WRMASK(val): return (val << A6XX_RB_STENCILWRMASK_WRMASK__SHIFT) & A6XX_RB_STENCILWRMASK_WRMASK__MASK
def A6XX_RB_STENCILWRMASK_BFWRMASK(val): return (val << A6XX_RB_STENCILWRMASK_BFWRMASK__SHIFT) & A6XX_RB_STENCILWRMASK_BFWRMASK__MASK
def A6XX_RB_WINDOW_OFFSET_X(val): return (val << A6XX_RB_WINDOW_OFFSET_X__SHIFT) & A6XX_RB_WINDOW_OFFSET_X__MASK
def A6XX_RB_WINDOW_OFFSET_Y(val): return (val << A6XX_RB_WINDOW_OFFSET_Y__SHIFT) & A6XX_RB_WINDOW_OFFSET_Y__MASK
def A6XX_RB_Z_CLAMP_MIN(val): return (val << A6XX_RB_Z_CLAMP_MIN__SHIFT) & A6XX_RB_Z_CLAMP_MIN__MASK
def A6XX_RB_Z_CLAMP_MAX(val): return (val << A6XX_RB_Z_CLAMP_MAX__SHIFT) & A6XX_RB_Z_CLAMP_MAX__MASK
def A6XX_RB_UNKNOWN_88D0_UNK0(val): return (val << A6XX_RB_UNKNOWN_88D0_UNK0__SHIFT) & A6XX_RB_UNKNOWN_88D0_UNK0__MASK
def A6XX_RB_UNKNOWN_88D0_UNK16(val): return (val << A6XX_RB_UNKNOWN_88D0_UNK16__SHIFT) & A6XX_RB_UNKNOWN_88D0_UNK16__MASK
def A6XX_RB_BLIT_SCISSOR_TL_X(val): return (val << A6XX_RB_BLIT_SCISSOR_TL_X__SHIFT) & A6XX_RB_BLIT_SCISSOR_TL_X__MASK
def A6XX_RB_BLIT_SCISSOR_TL_Y(val): return (val << A6XX_RB_BLIT_SCISSOR_TL_Y__SHIFT) & A6XX_RB_BLIT_SCISSOR_TL_Y__MASK
def A6XX_RB_BLIT_SCISSOR_BR_X(val): return (val << A6XX_RB_BLIT_SCISSOR_BR_X__SHIFT) & A6XX_RB_BLIT_SCISSOR_BR_X__MASK
def A6XX_RB_BLIT_SCISSOR_BR_Y(val): return (val << A6XX_RB_BLIT_SCISSOR_BR_Y__SHIFT) & A6XX_RB_BLIT_SCISSOR_BR_Y__MASK
def A6XX_RB_BIN_CONTROL2_BINW(val): return (val << A6XX_RB_BIN_CONTROL2_BINW__SHIFT) & A6XX_RB_BIN_CONTROL2_BINW__MASK
def A6XX_RB_BIN_CONTROL2_BINH(val): return (val << A6XX_RB_BIN_CONTROL2_BINH__SHIFT) & A6XX_RB_BIN_CONTROL2_BINH__MASK
def A6XX_RB_WINDOW_OFFSET2_X(val): return (val << A6XX_RB_WINDOW_OFFSET2_X__SHIFT) & A6XX_RB_WINDOW_OFFSET2_X__MASK
def A6XX_RB_WINDOW_OFFSET2_Y(val): return (val << A6XX_RB_WINDOW_OFFSET2_Y__SHIFT) & A6XX_RB_WINDOW_OFFSET2_Y__MASK
def A6XX_RB_BLIT_GMEM_MSAA_CNTL_SAMPLES(val): return (val << A6XX_RB_BLIT_GMEM_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_BLIT_GMEM_MSAA_CNTL_SAMPLES__MASK
def A6XX_RB_BLIT_DST_INFO_TILE_MODE(val): return (val << A6XX_RB_BLIT_DST_INFO_TILE_MODE__SHIFT) & A6XX_RB_BLIT_DST_INFO_TILE_MODE__MASK
def A6XX_RB_BLIT_DST_INFO_SAMPLES(val): return (val << A6XX_RB_BLIT_DST_INFO_SAMPLES__SHIFT) & A6XX_RB_BLIT_DST_INFO_SAMPLES__MASK
def A6XX_RB_BLIT_DST_INFO_COLOR_SWAP(val): return (val << A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__MASK
def A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(val): return (val << A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__MASK
def A6XX_RB_BLIT_DST_PITCH(val): return (val << A6XX_RB_BLIT_DST_PITCH__SHIFT) & A6XX_RB_BLIT_DST_PITCH__MASK
def A6XX_RB_BLIT_DST_ARRAY_PITCH(val): return (val << A6XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT) & A6XX_RB_BLIT_DST_ARRAY_PITCH__MASK
def A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH(val): return (val << A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__SHIFT) & A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__MASK
def A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH(val): return (val << A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__MASK
def A6XX_RB_BLIT_INFO_CLEAR_MASK(val): return (val << A6XX_RB_BLIT_INFO_CLEAR_MASK__SHIFT) & A6XX_RB_BLIT_INFO_CLEAR_MASK__MASK
def A6XX_RB_BLIT_INFO_LAST(val): return (val << A6XX_RB_BLIT_INFO_LAST__SHIFT) & A6XX_RB_BLIT_INFO_LAST__MASK
def A6XX_RB_BLIT_INFO_BUFFER_ID(val): return (val << A6XX_RB_BLIT_INFO_BUFFER_ID__SHIFT) & A6XX_RB_BLIT_INFO_BUFFER_ID__MASK
def A7XX_RB_CCU_CNTL2_DEPTH_OFFSET_HI(val): return (val << A7XX_RB_CCU_CNTL2_DEPTH_OFFSET_HI__SHIFT) & A7XX_RB_CCU_CNTL2_DEPTH_OFFSET_HI__MASK
def A7XX_RB_CCU_CNTL2_COLOR_OFFSET_HI(val): return (val << A7XX_RB_CCU_CNTL2_COLOR_OFFSET_HI__SHIFT) & A7XX_RB_CCU_CNTL2_COLOR_OFFSET_HI__MASK
def A7XX_RB_CCU_CNTL2_DEPTH_CACHE_SIZE(val): return (val << A7XX_RB_CCU_CNTL2_DEPTH_CACHE_SIZE__SHIFT) & A7XX_RB_CCU_CNTL2_DEPTH_CACHE_SIZE__MASK
def A7XX_RB_CCU_CNTL2_DEPTH_OFFSET(val): return (val << A7XX_RB_CCU_CNTL2_DEPTH_OFFSET__SHIFT) & A7XX_RB_CCU_CNTL2_DEPTH_OFFSET__MASK
def A7XX_RB_CCU_CNTL2_COLOR_CACHE_SIZE(val): return (val << A7XX_RB_CCU_CNTL2_COLOR_CACHE_SIZE__SHIFT) & A7XX_RB_CCU_CNTL2_COLOR_CACHE_SIZE__MASK
def A7XX_RB_CCU_CNTL2_COLOR_OFFSET(val): return (val << A7XX_RB_CCU_CNTL2_COLOR_OFFSET__SHIFT) & A7XX_RB_CCU_CNTL2_COLOR_OFFSET__MASK
def A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH(val): return (val << A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__MASK
def A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH(val): return (val << A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK
def A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH(val): return (val << A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__MASK
def A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8(val): return (val << A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__MASK
def A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH(val): return (val << A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK
def A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH(val): return (val << A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__MASK
def A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH(val): return (val << A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK
def A6XX_RB_2D_BLIT_CNTL_ROTATE(val): return (val << A6XX_RB_2D_BLIT_CNTL_ROTATE__SHIFT) & A6XX_RB_2D_BLIT_CNTL_ROTATE__MASK
def A6XX_RB_2D_BLIT_CNTL_UNK4(val): return (val << A6XX_RB_2D_BLIT_CNTL_UNK4__SHIFT) & A6XX_RB_2D_BLIT_CNTL_UNK4__MASK
def A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT(val): return (val << A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT) & A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__MASK
def A6XX_RB_2D_BLIT_CNTL_UNK17(val): return (val << A6XX_RB_2D_BLIT_CNTL_UNK17__SHIFT) & A6XX_RB_2D_BLIT_CNTL_UNK17__MASK
def A6XX_RB_2D_BLIT_CNTL_MASK(val): return (val << A6XX_RB_2D_BLIT_CNTL_MASK__SHIFT) & A6XX_RB_2D_BLIT_CNTL_MASK__MASK
def A6XX_RB_2D_BLIT_CNTL_IFMT(val): return (val << A6XX_RB_2D_BLIT_CNTL_IFMT__SHIFT) & A6XX_RB_2D_BLIT_CNTL_IFMT__MASK
def A6XX_RB_2D_BLIT_CNTL_RASTER_MODE(val): return (val << A6XX_RB_2D_BLIT_CNTL_RASTER_MODE__SHIFT) & A6XX_RB_2D_BLIT_CNTL_RASTER_MODE__MASK
def A6XX_RB_2D_DST_INFO_COLOR_FORMAT(val): return (val << A6XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK
def A6XX_RB_2D_DST_INFO_TILE_MODE(val): return (val << A6XX_RB_2D_DST_INFO_TILE_MODE__SHIFT) & A6XX_RB_2D_DST_INFO_TILE_MODE__MASK
def A6XX_RB_2D_DST_INFO_COLOR_SWAP(val): return (val << A6XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_2D_DST_INFO_COLOR_SWAP__MASK
def A6XX_RB_2D_DST_INFO_SAMPLES(val): return (val << A6XX_RB_2D_DST_INFO_SAMPLES__SHIFT) & A6XX_RB_2D_DST_INFO_SAMPLES__MASK
def A6XX_RB_2D_DST_INFO_UNK23(val): return (val << A6XX_RB_2D_DST_INFO_UNK23__SHIFT) & A6XX_RB_2D_DST_INFO_UNK23__MASK
def A6XX_RB_2D_DST_PITCH(val): return (val << A6XX_RB_2D_DST_PITCH__SHIFT) & A6XX_RB_2D_DST_PITCH__MASK
def A6XX_RB_2D_DST_PLANE_PITCH(val): return (val << A6XX_RB_2D_DST_PLANE_PITCH__SHIFT) & A6XX_RB_2D_DST_PLANE_PITCH__MASK
def A6XX_RB_2D_DST_FLAGS_PITCH(val): return (val << A6XX_RB_2D_DST_FLAGS_PITCH__SHIFT) & A6XX_RB_2D_DST_FLAGS_PITCH__MASK
def A6XX_RB_2D_DST_FLAGS_PLANE_PITCH(val): return (val << A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__SHIFT) & A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__MASK
def A6XX_RB_CCU_CNTL_DEPTH_OFFSET_HI(val): return (val << A6XX_RB_CCU_CNTL_DEPTH_OFFSET_HI__SHIFT) & A6XX_RB_CCU_CNTL_DEPTH_OFFSET_HI__MASK
def A6XX_RB_CCU_CNTL_COLOR_OFFSET_HI(val): return (val << A6XX_RB_CCU_CNTL_COLOR_OFFSET_HI__SHIFT) & A6XX_RB_CCU_CNTL_COLOR_OFFSET_HI__MASK
def A6XX_RB_CCU_CNTL_DEPTH_CACHE_SIZE(val): return (val << A6XX_RB_CCU_CNTL_DEPTH_CACHE_SIZE__SHIFT) & A6XX_RB_CCU_CNTL_DEPTH_CACHE_SIZE__MASK
def A6XX_RB_CCU_CNTL_DEPTH_OFFSET(val): return (val << A6XX_RB_CCU_CNTL_DEPTH_OFFSET__SHIFT) & A6XX_RB_CCU_CNTL_DEPTH_OFFSET__MASK
def A6XX_RB_CCU_CNTL_COLOR_CACHE_SIZE(val): return (val << A6XX_RB_CCU_CNTL_COLOR_CACHE_SIZE__SHIFT) & A6XX_RB_CCU_CNTL_COLOR_CACHE_SIZE__MASK
def A6XX_RB_CCU_CNTL_COLOR_OFFSET(val): return (val << A6XX_RB_CCU_CNTL_COLOR_OFFSET__SHIFT) & A6XX_RB_CCU_CNTL_COLOR_OFFSET__MASK
def A6XX_RB_NC_MODE_CNTL_LOWER_BIT(val): return (val << A6XX_RB_NC_MODE_CNTL_LOWER_BIT__SHIFT) & A6XX_RB_NC_MODE_CNTL_LOWER_BIT__MASK
def A6XX_RB_NC_MODE_CNTL_UPPER_BIT(val): return (val << A6XX_RB_NC_MODE_CNTL_UPPER_BIT__SHIFT) & A6XX_RB_NC_MODE_CNTL_UPPER_BIT__MASK
def A6XX_RB_NC_MODE_CNTL_UNK12(val): return (val << A6XX_RB_NC_MODE_CNTL_UNK12__SHIFT) & A6XX_RB_NC_MODE_CNTL_UNK12__MASK
def A6XX_VPC_GS_PARAM_LINELENGTHLOC(val): return (val << A6XX_VPC_GS_PARAM_LINELENGTHLOC__SHIFT) & A6XX_VPC_GS_PARAM_LINELENGTHLOC__MASK
def A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK(val): return (val << A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__MASK
def A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC(val): return (val << A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK
def A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC(val): return (val << A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK
def A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK(val): return (val << A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__MASK
def A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC(val): return (val << A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK
def A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC(val): return (val << A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK
def A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK(val): return (val << A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__MASK
def A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC(val): return (val << A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK
def A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC(val): return (val << A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK
def A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_MASK(val): return (val << A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_MASK__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_MASK__MASK
def A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_03_LOC(val): return (val << A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__MASK
def A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_47_LOC(val): return (val << A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__MASK
def A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_MASK(val): return (val << A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_MASK__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_MASK__MASK
def A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_03_LOC(val): return (val << A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__MASK
def A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_47_LOC(val): return (val << A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__MASK
def A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_MASK(val): return (val << A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_MASK__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_MASK__MASK
def A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_03_LOC(val): return (val << A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__MASK
def A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_47_LOC(val): return (val << A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__MASK
def A6XX_VPC_VS_LAYER_CNTL_LAYERLOC(val): return (val << A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__SHIFT) & A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__MASK
def A6XX_VPC_VS_LAYER_CNTL_VIEWLOC(val): return (val << A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__SHIFT) & A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__MASK
def A6XX_VPC_VS_LAYER_CNTL_SHADINGRATELOC(val): return (val << A6XX_VPC_VS_LAYER_CNTL_SHADINGRATELOC__SHIFT) & A6XX_VPC_VS_LAYER_CNTL_SHADINGRATELOC__MASK
def A6XX_VPC_GS_LAYER_CNTL_LAYERLOC(val): return (val << A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__SHIFT) & A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__MASK
def A6XX_VPC_GS_LAYER_CNTL_VIEWLOC(val): return (val << A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__SHIFT) & A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__MASK
def A6XX_VPC_GS_LAYER_CNTL_SHADINGRATELOC(val): return (val << A6XX_VPC_GS_LAYER_CNTL_SHADINGRATELOC__SHIFT) & A6XX_VPC_GS_LAYER_CNTL_SHADINGRATELOC__MASK
def A6XX_VPC_DS_LAYER_CNTL_LAYERLOC(val): return (val << A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__SHIFT) & A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__MASK
def A6XX_VPC_DS_LAYER_CNTL_VIEWLOC(val): return (val << A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__SHIFT) & A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__MASK
def A6XX_VPC_DS_LAYER_CNTL_SHADINGRATELOC(val): return (val << A6XX_VPC_DS_LAYER_CNTL_SHADINGRATELOC__SHIFT) & A6XX_VPC_DS_LAYER_CNTL_SHADINGRATELOC__MASK
def A6XX_VPC_VS_LAYER_CNTL_V2_LAYERLOC(val): return (val << A6XX_VPC_VS_LAYER_CNTL_V2_LAYERLOC__SHIFT) & A6XX_VPC_VS_LAYER_CNTL_V2_LAYERLOC__MASK
def A6XX_VPC_VS_LAYER_CNTL_V2_VIEWLOC(val): return (val << A6XX_VPC_VS_LAYER_CNTL_V2_VIEWLOC__SHIFT) & A6XX_VPC_VS_LAYER_CNTL_V2_VIEWLOC__MASK
def A6XX_VPC_VS_LAYER_CNTL_V2_SHADINGRATELOC(val): return (val << A6XX_VPC_VS_LAYER_CNTL_V2_SHADINGRATELOC__SHIFT) & A6XX_VPC_VS_LAYER_CNTL_V2_SHADINGRATELOC__MASK
def A6XX_VPC_GS_LAYER_CNTL_V2_LAYERLOC(val): return (val << A6XX_VPC_GS_LAYER_CNTL_V2_LAYERLOC__SHIFT) & A6XX_VPC_GS_LAYER_CNTL_V2_LAYERLOC__MASK
def A6XX_VPC_GS_LAYER_CNTL_V2_VIEWLOC(val): return (val << A6XX_VPC_GS_LAYER_CNTL_V2_VIEWLOC__SHIFT) & A6XX_VPC_GS_LAYER_CNTL_V2_VIEWLOC__MASK
def A6XX_VPC_GS_LAYER_CNTL_V2_SHADINGRATELOC(val): return (val << A6XX_VPC_GS_LAYER_CNTL_V2_SHADINGRATELOC__SHIFT) & A6XX_VPC_GS_LAYER_CNTL_V2_SHADINGRATELOC__MASK
def A6XX_VPC_DS_LAYER_CNTL_V2_LAYERLOC(val): return (val << A6XX_VPC_DS_LAYER_CNTL_V2_LAYERLOC__SHIFT) & A6XX_VPC_DS_LAYER_CNTL_V2_LAYERLOC__MASK
def A6XX_VPC_DS_LAYER_CNTL_V2_VIEWLOC(val): return (val << A6XX_VPC_DS_LAYER_CNTL_V2_VIEWLOC__SHIFT) & A6XX_VPC_DS_LAYER_CNTL_V2_VIEWLOC__MASK
def A6XX_VPC_DS_LAYER_CNTL_V2_SHADINGRATELOC(val): return (val << A6XX_VPC_DS_LAYER_CNTL_V2_SHADINGRATELOC__SHIFT) & A6XX_VPC_DS_LAYER_CNTL_V2_SHADINGRATELOC__MASK
def A6XX_VPC_POLYGON_MODE_MODE(val): return (val << A6XX_VPC_POLYGON_MODE_MODE__SHIFT) & A6XX_VPC_POLYGON_MODE_MODE__MASK
def A7XX_VPC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT(val): return (val << A7XX_VPC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__SHIFT) & A7XX_VPC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__MASK
def A7XX_VPC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(val): return (val << A7XX_VPC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__SHIFT) & A7XX_VPC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__MASK
def A7XX_VPC_PRIMITIVE_CNTL_5_GS_OUTPUT(val): return (val << A7XX_VPC_PRIMITIVE_CNTL_5_GS_OUTPUT__SHIFT) & A7XX_VPC_PRIMITIVE_CNTL_5_GS_OUTPUT__MASK
def A7XX_VPC_MULTIVIEW_CNTL_VIEWS(val): return (val << A7XX_VPC_MULTIVIEW_CNTL_VIEWS__SHIFT) & A7XX_VPC_MULTIVIEW_CNTL_VIEWS__MASK
def A6XX_VPC_SO_CNTL_ADDR(val): return (val << A6XX_VPC_SO_CNTL_ADDR__SHIFT) & A6XX_VPC_SO_CNTL_ADDR__MASK
def A6XX_VPC_SO_PROG_A_BUF(val): return (val << A6XX_VPC_SO_PROG_A_BUF__SHIFT) & A6XX_VPC_SO_PROG_A_BUF__MASK
def A6XX_VPC_SO_PROG_A_OFF(val): return (val << A6XX_VPC_SO_PROG_A_OFF__SHIFT) & A6XX_VPC_SO_PROG_A_OFF__MASK
def A6XX_VPC_SO_PROG_B_BUF(val): return (val << A6XX_VPC_SO_PROG_B_BUF__SHIFT) & A6XX_VPC_SO_PROG_B_BUF__MASK
def A6XX_VPC_SO_PROG_B_OFF(val): return (val << A6XX_VPC_SO_PROG_B_OFF__SHIFT) & A6XX_VPC_SO_PROG_B_OFF__MASK
def A6XX_VPC_VS_PACK_STRIDE_IN_VPC(val): return (val << A6XX_VPC_VS_PACK_STRIDE_IN_VPC__SHIFT) & A6XX_VPC_VS_PACK_STRIDE_IN_VPC__MASK
def A6XX_VPC_VS_PACK_POSITIONLOC(val): return (val << A6XX_VPC_VS_PACK_POSITIONLOC__SHIFT) & A6XX_VPC_VS_PACK_POSITIONLOC__MASK
def A6XX_VPC_VS_PACK_PSIZELOC(val): return (val << A6XX_VPC_VS_PACK_PSIZELOC__SHIFT) & A6XX_VPC_VS_PACK_PSIZELOC__MASK
def A6XX_VPC_VS_PACK_EXTRAPOS(val): return (val << A6XX_VPC_VS_PACK_EXTRAPOS__SHIFT) & A6XX_VPC_VS_PACK_EXTRAPOS__MASK
def A6XX_VPC_GS_PACK_STRIDE_IN_VPC(val): return (val << A6XX_VPC_GS_PACK_STRIDE_IN_VPC__SHIFT) & A6XX_VPC_GS_PACK_STRIDE_IN_VPC__MASK
def A6XX_VPC_GS_PACK_POSITIONLOC(val): return (val << A6XX_VPC_GS_PACK_POSITIONLOC__SHIFT) & A6XX_VPC_GS_PACK_POSITIONLOC__MASK
def A6XX_VPC_GS_PACK_PSIZELOC(val): return (val << A6XX_VPC_GS_PACK_PSIZELOC__SHIFT) & A6XX_VPC_GS_PACK_PSIZELOC__MASK
def A6XX_VPC_GS_PACK_EXTRAPOS(val): return (val << A6XX_VPC_GS_PACK_EXTRAPOS__SHIFT) & A6XX_VPC_GS_PACK_EXTRAPOS__MASK
def A6XX_VPC_DS_PACK_STRIDE_IN_VPC(val): return (val << A6XX_VPC_DS_PACK_STRIDE_IN_VPC__SHIFT) & A6XX_VPC_DS_PACK_STRIDE_IN_VPC__MASK
def A6XX_VPC_DS_PACK_POSITIONLOC(val): return (val << A6XX_VPC_DS_PACK_POSITIONLOC__SHIFT) & A6XX_VPC_DS_PACK_POSITIONLOC__MASK
def A6XX_VPC_DS_PACK_PSIZELOC(val): return (val << A6XX_VPC_DS_PACK_PSIZELOC__SHIFT) & A6XX_VPC_DS_PACK_PSIZELOC__MASK
def A6XX_VPC_DS_PACK_EXTRAPOS(val): return (val << A6XX_VPC_DS_PACK_EXTRAPOS__SHIFT) & A6XX_VPC_DS_PACK_EXTRAPOS__MASK
def A6XX_VPC_CNTL_0_NUMNONPOSVAR(val): return (val << A6XX_VPC_CNTL_0_NUMNONPOSVAR__SHIFT) & A6XX_VPC_CNTL_0_NUMNONPOSVAR__MASK
def A6XX_VPC_CNTL_0_PRIMIDLOC(val): return (val << A6XX_VPC_CNTL_0_PRIMIDLOC__SHIFT) & A6XX_VPC_CNTL_0_PRIMIDLOC__MASK
def A6XX_VPC_CNTL_0_VIEWIDLOC(val): return (val << A6XX_VPC_CNTL_0_VIEWIDLOC__SHIFT) & A6XX_VPC_CNTL_0_VIEWIDLOC__MASK
def A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM(val): return (val << A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__MASK
def A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM(val): return (val << A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__MASK
def A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM(val): return (val << A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__MASK
def A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM(val): return (val << A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__MASK
def A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE(val): return (val << A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__MASK
def A7XX_VPC_POLYGON_MODE2_MODE(val): return (val << A7XX_VPC_POLYGON_MODE2_MODE__SHIFT) & A7XX_VPC_POLYGON_MODE2_MODE__MASK
def A7XX_VPC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM(val): return (val << A7XX_VPC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__SHIFT) & A7XX_VPC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__MASK
def A7XX_VPC_ATTR_BUF_BASE_GMEM_BASE_GMEM(val): return (val << A7XX_VPC_ATTR_BUF_BASE_GMEM_BASE_GMEM__SHIFT) & A7XX_VPC_ATTR_BUF_BASE_GMEM_BASE_GMEM__MASK
def A7XX_PC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM(val): return (val << A7XX_PC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__SHIFT) & A7XX_PC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__MASK
def A6XX_PC_HS_INPUT_SIZE_SIZE(val): return (val << A6XX_PC_HS_INPUT_SIZE_SIZE__SHIFT) & A6XX_PC_HS_INPUT_SIZE_SIZE__MASK
def A6XX_PC_TESS_CNTL_SPACING(val): return (val << A6XX_PC_TESS_CNTL_SPACING__SHIFT) & A6XX_PC_TESS_CNTL_SPACING__MASK
def A6XX_PC_TESS_CNTL_OUTPUT(val): return (val << A6XX_PC_TESS_CNTL_OUTPUT__SHIFT) & A6XX_PC_TESS_CNTL_OUTPUT__MASK
def A6XX_PC_SO_STREAM_CNTL_STREAM_ENABLE(val): return (val << A6XX_PC_SO_STREAM_CNTL_STREAM_ENABLE__SHIFT) & A6XX_PC_SO_STREAM_CNTL_STREAM_ENABLE__MASK
def A6XX_PC_DRAW_CMD_STATE_ID(val): return (val << A6XX_PC_DRAW_CMD_STATE_ID__SHIFT) & A6XX_PC_DRAW_CMD_STATE_ID__MASK
def A6XX_PC_DISPATCH_CMD_STATE_ID(val): return (val << A6XX_PC_DISPATCH_CMD_STATE_ID__SHIFT) & A6XX_PC_DISPATCH_CMD_STATE_ID__MASK
def A6XX_PC_EVENT_CMD_STATE_ID(val): return (val << A6XX_PC_EVENT_CMD_STATE_ID__SHIFT) & A6XX_PC_EVENT_CMD_STATE_ID__MASK
def A6XX_PC_EVENT_CMD_EVENT(val): return (val << A6XX_PC_EVENT_CMD_EVENT__SHIFT) & A6XX_PC_EVENT_CMD_EVENT__MASK
def A6XX_PC_POLYGON_MODE_MODE(val): return (val << A6XX_PC_POLYGON_MODE_MODE__SHIFT) & A6XX_PC_POLYGON_MODE_MODE__MASK
def A7XX_PC_POLYGON_MODE_MODE(val): return (val << A7XX_PC_POLYGON_MODE_MODE__SHIFT) & A7XX_PC_POLYGON_MODE_MODE__MASK
def A6XX_PC_RASTER_CNTL_STREAM(val): return (val << A6XX_PC_RASTER_CNTL_STREAM__SHIFT) & A6XX_PC_RASTER_CNTL_STREAM__MASK
def A7XX_PC_RASTER_CNTL_STREAM(val): return (val << A7XX_PC_RASTER_CNTL_STREAM__SHIFT) & A7XX_PC_RASTER_CNTL_STREAM__MASK
def A7XX_PC_RASTER_CNTL_V2_STREAM(val): return (val << A7XX_PC_RASTER_CNTL_V2_STREAM__SHIFT) & A7XX_PC_RASTER_CNTL_V2_STREAM__MASK
def A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC(val): return (val << A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__SHIFT) & A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__MASK
def A6XX_PC_VS_OUT_CNTL_CLIP_MASK(val): return (val << A6XX_PC_VS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_VS_OUT_CNTL_CLIP_MASK__MASK
def A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC(val): return (val << A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__SHIFT) & A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__MASK
def A6XX_PC_GS_OUT_CNTL_CLIP_MASK(val): return (val << A6XX_PC_GS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_GS_OUT_CNTL_CLIP_MASK__MASK
def A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC(val): return (val << A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC__SHIFT) & A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC__MASK
def A6XX_PC_HS_OUT_CNTL_CLIP_MASK(val): return (val << A6XX_PC_HS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_HS_OUT_CNTL_CLIP_MASK__MASK
def A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC(val): return (val << A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__SHIFT) & A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__MASK
def A6XX_PC_DS_OUT_CNTL_CLIP_MASK(val): return (val << A6XX_PC_DS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_DS_OUT_CNTL_CLIP_MASK__MASK
def A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT(val): return (val << A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__MASK
def A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(val): return (val << A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__MASK
def A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT(val): return (val << A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__MASK
def A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC(val): return (val << A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__MASK
def A6XX_PC_MULTIVIEW_CNTL_VIEWS(val): return (val << A6XX_PC_MULTIVIEW_CNTL_VIEWS__SHIFT) & A6XX_PC_MULTIVIEW_CNTL_VIEWS__MASK
def A6XX_PC_2D_EVENT_CMD_EVENT(val): return (val << A6XX_PC_2D_EVENT_CMD_EVENT__SHIFT) & A6XX_PC_2D_EVENT_CMD_EVENT__MASK
def A6XX_PC_2D_EVENT_CMD_STATE_ID(val): return (val << A6XX_PC_2D_EVENT_CMD_STATE_ID__SHIFT) & A6XX_PC_2D_EVENT_CMD_STATE_ID__MASK
def A6XX_PC_DRAW_INITIATOR_PRIM_TYPE(val): return (val << A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__SHIFT) & A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__MASK
def A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT(val): return (val << A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__SHIFT) & A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__MASK
def A6XX_PC_DRAW_INITIATOR_VIS_CULL(val): return (val << A6XX_PC_DRAW_INITIATOR_VIS_CULL__SHIFT) & A6XX_PC_DRAW_INITIATOR_VIS_CULL__MASK
def A6XX_PC_DRAW_INITIATOR_INDEX_SIZE(val): return (val << A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__SHIFT) & A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__MASK
def A6XX_PC_DRAW_INITIATOR_PATCH_TYPE(val): return (val << A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__SHIFT) & A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__MASK
def A6XX_PC_VSTREAM_CONTROL_UNK0(val): return (val << A6XX_PC_VSTREAM_CONTROL_UNK0__SHIFT) & A6XX_PC_VSTREAM_CONTROL_UNK0__MASK
def A6XX_PC_VSTREAM_CONTROL_VSC_SIZE(val): return (val << A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__SHIFT) & A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__MASK
def A6XX_PC_VSTREAM_CONTROL_VSC_N(val): return (val << A6XX_PC_VSTREAM_CONTROL_VSC_N__SHIFT) & A6XX_PC_VSTREAM_CONTROL_VSC_N__MASK
def A6XX_VFD_CONTROL_0_FETCH_CNT(val): return (val << A6XX_VFD_CONTROL_0_FETCH_CNT__SHIFT) & A6XX_VFD_CONTROL_0_FETCH_CNT__MASK
def A6XX_VFD_CONTROL_0_DECODE_CNT(val): return (val << A6XX_VFD_CONTROL_0_DECODE_CNT__SHIFT) & A6XX_VFD_CONTROL_0_DECODE_CNT__MASK
def A6XX_VFD_CONTROL_1_REGID4VTX(val): return (val << A6XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A6XX_VFD_CONTROL_1_REGID4VTX__MASK
def A6XX_VFD_CONTROL_1_REGID4INST(val): return (val << A6XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A6XX_VFD_CONTROL_1_REGID4INST__MASK
def A6XX_VFD_CONTROL_1_REGID4PRIMID(val): return (val << A6XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT) & A6XX_VFD_CONTROL_1_REGID4PRIMID__MASK
def A6XX_VFD_CONTROL_1_REGID4VIEWID(val): return (val << A6XX_VFD_CONTROL_1_REGID4VIEWID__SHIFT) & A6XX_VFD_CONTROL_1_REGID4VIEWID__MASK
def A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID(val): return (val << A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID__SHIFT) & A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID__MASK
def A6XX_VFD_CONTROL_2_REGID_INVOCATIONID(val): return (val << A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__SHIFT) & A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__MASK
def A6XX_VFD_CONTROL_3_REGID_DSPRIMID(val): return (val << A6XX_VFD_CONTROL_3_REGID_DSPRIMID__SHIFT) & A6XX_VFD_CONTROL_3_REGID_DSPRIMID__MASK
def A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID(val): return (val << A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID__SHIFT) & A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID__MASK
def A6XX_VFD_CONTROL_3_REGID_TESSX(val): return (val << A6XX_VFD_CONTROL_3_REGID_TESSX__SHIFT) & A6XX_VFD_CONTROL_3_REGID_TESSX__MASK
def A6XX_VFD_CONTROL_3_REGID_TESSY(val): return (val << A6XX_VFD_CONTROL_3_REGID_TESSY__SHIFT) & A6XX_VFD_CONTROL_3_REGID_TESSY__MASK
def A6XX_VFD_CONTROL_4_UNK0(val): return (val << A6XX_VFD_CONTROL_4_UNK0__SHIFT) & A6XX_VFD_CONTROL_4_UNK0__MASK
def A6XX_VFD_CONTROL_5_REGID_GSHEADER(val): return (val << A6XX_VFD_CONTROL_5_REGID_GSHEADER__SHIFT) & A6XX_VFD_CONTROL_5_REGID_GSHEADER__MASK
def A6XX_VFD_CONTROL_5_UNK8(val): return (val << A6XX_VFD_CONTROL_5_UNK8__SHIFT) & A6XX_VFD_CONTROL_5_UNK8__MASK
def A6XX_VFD_MODE_CNTL_RENDER_MODE(val): return (val << A6XX_VFD_MODE_CNTL_RENDER_MODE__SHIFT) & A6XX_VFD_MODE_CNTL_RENDER_MODE__MASK
def A6XX_VFD_MULTIVIEW_CNTL_VIEWS(val): return (val << A6XX_VFD_MULTIVIEW_CNTL_VIEWS__SHIFT) & A6XX_VFD_MULTIVIEW_CNTL_VIEWS__MASK
def A6XX_VFD_DECODE_INSTR_IDX(val): return (val << A6XX_VFD_DECODE_INSTR_IDX__SHIFT) & A6XX_VFD_DECODE_INSTR_IDX__MASK
def A6XX_VFD_DECODE_INSTR_OFFSET(val): return (val << A6XX_VFD_DECODE_INSTR_OFFSET__SHIFT) & A6XX_VFD_DECODE_INSTR_OFFSET__MASK
def A6XX_VFD_DECODE_INSTR_FORMAT(val): return (val << A6XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A6XX_VFD_DECODE_INSTR_FORMAT__MASK
def A6XX_VFD_DECODE_INSTR_SWAP(val): return (val << A6XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A6XX_VFD_DECODE_INSTR_SWAP__MASK
def A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK(val): return (val << A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT) & A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK
def A6XX_VFD_DEST_CNTL_INSTR_REGID(val): return (val << A6XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT) & A6XX_VFD_DEST_CNTL_INSTR_REGID__MASK
def A6XX_SP_VS_CTRL_REG0_THREADMODE(val): return (val << A6XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_VS_CTRL_REG0_THREADMODE__MASK
def A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(val): return (val << A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK
def A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(val): return (val << A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK
def A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(val): return (val << A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK
def A6XX_SP_VS_PRIMITIVE_CNTL_OUT(val): return (val << A6XX_SP_VS_PRIMITIVE_CNTL_OUT__SHIFT) & A6XX_SP_VS_PRIMITIVE_CNTL_OUT__MASK
def A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID(val): return (val << A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT) & A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__MASK
def A6XX_SP_VS_OUT_REG_A_REGID(val): return (val << A6XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A6XX_SP_VS_OUT_REG_A_REGID__MASK
def A6XX_SP_VS_OUT_REG_A_COMPMASK(val): return (val << A6XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A6XX_SP_VS_OUT_REG_A_COMPMASK__MASK
def A6XX_SP_VS_OUT_REG_B_REGID(val): return (val << A6XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A6XX_SP_VS_OUT_REG_B_REGID__MASK
def A6XX_SP_VS_OUT_REG_B_COMPMASK(val): return (val << A6XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A6XX_SP_VS_OUT_REG_B_COMPMASK__MASK
def A6XX_SP_VS_VPC_DST_REG_OUTLOC0(val): return (val << A6XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK
def A6XX_SP_VS_VPC_DST_REG_OUTLOC1(val): return (val << A6XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK
def A6XX_SP_VS_VPC_DST_REG_OUTLOC2(val): return (val << A6XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK
def A6XX_SP_VS_VPC_DST_REG_OUTLOC3(val): return (val << A6XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK
def A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM(val): return (val << A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK
def A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(val): return (val << A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK
def A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(val): return (val << A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK
def A6XX_SP_VS_CONFIG_NTEX(val): return (val << A6XX_SP_VS_CONFIG_NTEX__SHIFT) & A6XX_SP_VS_CONFIG_NTEX__MASK
def A6XX_SP_VS_CONFIG_NSAMP(val): return (val << A6XX_SP_VS_CONFIG_NSAMP__SHIFT) & A6XX_SP_VS_CONFIG_NSAMP__MASK
def A6XX_SP_VS_CONFIG_NIBO(val): return (val << A6XX_SP_VS_CONFIG_NIBO__SHIFT) & A6XX_SP_VS_CONFIG_NIBO__MASK
def A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET(val): return (val << A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK
def A6XX_SP_HS_CTRL_REG0_THREADMODE(val): return (val << A6XX_SP_HS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_HS_CTRL_REG0_THREADMODE__MASK
def A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT(val): return (val << A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK
def A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT(val): return (val << A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK
def A6XX_SP_HS_CTRL_REG0_BRANCHSTACK(val): return (val << A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK
def A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM(val): return (val << A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK
def A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(val): return (val << A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK
def A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(val): return (val << A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK
def A6XX_SP_HS_CONFIG_NTEX(val): return (val << A6XX_SP_HS_CONFIG_NTEX__SHIFT) & A6XX_SP_HS_CONFIG_NTEX__MASK
def A6XX_SP_HS_CONFIG_NSAMP(val): return (val << A6XX_SP_HS_CONFIG_NSAMP__SHIFT) & A6XX_SP_HS_CONFIG_NSAMP__MASK
def A6XX_SP_HS_CONFIG_NIBO(val): return (val << A6XX_SP_HS_CONFIG_NIBO__SHIFT) & A6XX_SP_HS_CONFIG_NIBO__MASK
def A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET(val): return (val << A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK
def A6XX_SP_DS_CTRL_REG0_THREADMODE(val): return (val << A6XX_SP_DS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_DS_CTRL_REG0_THREADMODE__MASK
def A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT(val): return (val << A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK
def A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT(val): return (val << A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK
def A6XX_SP_DS_CTRL_REG0_BRANCHSTACK(val): return (val << A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK
def A6XX_SP_DS_PRIMITIVE_CNTL_OUT(val): return (val << A6XX_SP_DS_PRIMITIVE_CNTL_OUT__SHIFT) & A6XX_SP_DS_PRIMITIVE_CNTL_OUT__MASK
def A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID(val): return (val << A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT) & A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__MASK
def A6XX_SP_DS_OUT_REG_A_REGID(val): return (val << A6XX_SP_DS_OUT_REG_A_REGID__SHIFT) & A6XX_SP_DS_OUT_REG_A_REGID__MASK
def A6XX_SP_DS_OUT_REG_A_COMPMASK(val): return (val << A6XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT) & A6XX_SP_DS_OUT_REG_A_COMPMASK__MASK
def A6XX_SP_DS_OUT_REG_B_REGID(val): return (val << A6XX_SP_DS_OUT_REG_B_REGID__SHIFT) & A6XX_SP_DS_OUT_REG_B_REGID__MASK
def A6XX_SP_DS_OUT_REG_B_COMPMASK(val): return (val << A6XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT) & A6XX_SP_DS_OUT_REG_B_COMPMASK__MASK
def A6XX_SP_DS_VPC_DST_REG_OUTLOC0(val): return (val << A6XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK
def A6XX_SP_DS_VPC_DST_REG_OUTLOC1(val): return (val << A6XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK
def A6XX_SP_DS_VPC_DST_REG_OUTLOC2(val): return (val << A6XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK
def A6XX_SP_DS_VPC_DST_REG_OUTLOC3(val): return (val << A6XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK
def A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM(val): return (val << A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK
def A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(val): return (val << A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK
def A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(val): return (val << A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK
def A6XX_SP_DS_CONFIG_NTEX(val): return (val << A6XX_SP_DS_CONFIG_NTEX__SHIFT) & A6XX_SP_DS_CONFIG_NTEX__MASK
def A6XX_SP_DS_CONFIG_NSAMP(val): return (val << A6XX_SP_DS_CONFIG_NSAMP__SHIFT) & A6XX_SP_DS_CONFIG_NSAMP__MASK
def A6XX_SP_DS_CONFIG_NIBO(val): return (val << A6XX_SP_DS_CONFIG_NIBO__SHIFT) & A6XX_SP_DS_CONFIG_NIBO__MASK
def A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET(val): return (val << A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK
def A6XX_SP_GS_CTRL_REG0_THREADMODE(val): return (val << A6XX_SP_GS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_GS_CTRL_REG0_THREADMODE__MASK
def A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT(val): return (val << A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK
def A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT(val): return (val << A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK
def A6XX_SP_GS_CTRL_REG0_BRANCHSTACK(val): return (val << A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK
def A6XX_SP_GS_PRIMITIVE_CNTL_OUT(val): return (val << A6XX_SP_GS_PRIMITIVE_CNTL_OUT__SHIFT) & A6XX_SP_GS_PRIMITIVE_CNTL_OUT__MASK
def A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID(val): return (val << A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT) & A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__MASK
def A6XX_SP_GS_OUT_REG_A_REGID(val): return (val << A6XX_SP_GS_OUT_REG_A_REGID__SHIFT) & A6XX_SP_GS_OUT_REG_A_REGID__MASK
def A6XX_SP_GS_OUT_REG_A_COMPMASK(val): return (val << A6XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT) & A6XX_SP_GS_OUT_REG_A_COMPMASK__MASK
def A6XX_SP_GS_OUT_REG_B_REGID(val): return (val << A6XX_SP_GS_OUT_REG_B_REGID__SHIFT) & A6XX_SP_GS_OUT_REG_B_REGID__MASK
def A6XX_SP_GS_OUT_REG_B_COMPMASK(val): return (val << A6XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT) & A6XX_SP_GS_OUT_REG_B_COMPMASK__MASK
def A6XX_SP_GS_VPC_DST_REG_OUTLOC0(val): return (val << A6XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK
def A6XX_SP_GS_VPC_DST_REG_OUTLOC1(val): return (val << A6XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK
def A6XX_SP_GS_VPC_DST_REG_OUTLOC2(val): return (val << A6XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK
def A6XX_SP_GS_VPC_DST_REG_OUTLOC3(val): return (val << A6XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK
def A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM(val): return (val << A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK
def A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(val): return (val << A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK
def A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(val): return (val << A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK
def A6XX_SP_GS_CONFIG_NTEX(val): return (val << A6XX_SP_GS_CONFIG_NTEX__SHIFT) & A6XX_SP_GS_CONFIG_NTEX__MASK
def A6XX_SP_GS_CONFIG_NSAMP(val): return (val << A6XX_SP_GS_CONFIG_NSAMP__SHIFT) & A6XX_SP_GS_CONFIG_NSAMP__MASK
def A6XX_SP_GS_CONFIG_NIBO(val): return (val << A6XX_SP_GS_CONFIG_NIBO__SHIFT) & A6XX_SP_GS_CONFIG_NIBO__MASK
def A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET(val): return (val << A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK
def A6XX_SP_FS_CTRL_REG0_THREADMODE(val): return (val << A6XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_FS_CTRL_REG0_THREADMODE__MASK
def A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(val): return (val << A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK
def A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(val): return (val << A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK
def A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(val): return (val << A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK
def A6XX_SP_FS_CTRL_REG0_THREADSIZE(val): return (val << A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK
def A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM(val): return (val << A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK
def A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(val): return (val << A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK
def A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(val): return (val << A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK
def A6XX_SP_BLEND_CNTL_ENABLE_BLEND(val): return (val << A6XX_SP_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A6XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK
def A6XX_SP_FS_RENDER_COMPONENTS_RT0(val): return (val << A6XX_SP_FS_RENDER_COMPONENTS_RT0__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT0__MASK
def A6XX_SP_FS_RENDER_COMPONENTS_RT1(val): return (val << A6XX_SP_FS_RENDER_COMPONENTS_RT1__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT1__MASK
def A6XX_SP_FS_RENDER_COMPONENTS_RT2(val): return (val << A6XX_SP_FS_RENDER_COMPONENTS_RT2__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT2__MASK
def A6XX_SP_FS_RENDER_COMPONENTS_RT3(val): return (val << A6XX_SP_FS_RENDER_COMPONENTS_RT3__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT3__MASK
def A6XX_SP_FS_RENDER_COMPONENTS_RT4(val): return (val << A6XX_SP_FS_RENDER_COMPONENTS_RT4__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT4__MASK
def A6XX_SP_FS_RENDER_COMPONENTS_RT5(val): return (val << A6XX_SP_FS_RENDER_COMPONENTS_RT5__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT5__MASK
def A6XX_SP_FS_RENDER_COMPONENTS_RT6(val): return (val << A6XX_SP_FS_RENDER_COMPONENTS_RT6__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT6__MASK
def A6XX_SP_FS_RENDER_COMPONENTS_RT7(val): return (val << A6XX_SP_FS_RENDER_COMPONENTS_RT7__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT7__MASK
def A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(val): return (val << A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__MASK
def A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(val): return (val << A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__MASK
def A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID(val): return (val << A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__MASK
def A6XX_SP_FS_OUTPUT_CNTL1_MRT(val): return (val << A6XX_SP_FS_OUTPUT_CNTL1_MRT__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL1_MRT__MASK
def A6XX_SP_FS_OUTPUT_REG_REGID(val): return (val << A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_REG_REGID__MASK
def A6XX_SP_FS_MRT_REG_COLOR_FORMAT(val): return (val << A6XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT) & A6XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK
def A6XX_SP_FS_PREFETCH_CNTL_COUNT(val): return (val << A6XX_SP_FS_PREFETCH_CNTL_COUNT__SHIFT) & A6XX_SP_FS_PREFETCH_CNTL_COUNT__MASK
def A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID(val): return (val << A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID__SHIFT) & A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID__MASK
def A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID4COORD(val): return (val << A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID4COORD__SHIFT) & A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID4COORD__MASK
def A6XX_SP_FS_PREFETCH_CMD_SRC(val): return (val << A6XX_SP_FS_PREFETCH_CMD_SRC__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_SRC__MASK
def A6XX_SP_FS_PREFETCH_CMD_SAMP_ID(val): return (val << A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__MASK
def A6XX_SP_FS_PREFETCH_CMD_TEX_ID(val): return (val << A6XX_SP_FS_PREFETCH_CMD_TEX_ID__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_TEX_ID__MASK
def A6XX_SP_FS_PREFETCH_CMD_DST(val): return (val << A6XX_SP_FS_PREFETCH_CMD_DST__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_DST__MASK
def A6XX_SP_FS_PREFETCH_CMD_WRMASK(val): return (val << A6XX_SP_FS_PREFETCH_CMD_WRMASK__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_WRMASK__MASK
def A6XX_SP_FS_PREFETCH_CMD_CMD(val): return (val << A6XX_SP_FS_PREFETCH_CMD_CMD__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_CMD__MASK
def A7XX_SP_FS_PREFETCH_CMD_SRC(val): return (val << A7XX_SP_FS_PREFETCH_CMD_SRC__SHIFT) & A7XX_SP_FS_PREFETCH_CMD_SRC__MASK
def A7XX_SP_FS_PREFETCH_CMD_SAMP_ID(val): return (val << A7XX_SP_FS_PREFETCH_CMD_SAMP_ID__SHIFT) & A7XX_SP_FS_PREFETCH_CMD_SAMP_ID__MASK
def A7XX_SP_FS_PREFETCH_CMD_TEX_ID(val): return (val << A7XX_SP_FS_PREFETCH_CMD_TEX_ID__SHIFT) & A7XX_SP_FS_PREFETCH_CMD_TEX_ID__MASK
def A7XX_SP_FS_PREFETCH_CMD_DST(val): return (val << A7XX_SP_FS_PREFETCH_CMD_DST__SHIFT) & A7XX_SP_FS_PREFETCH_CMD_DST__MASK
def A7XX_SP_FS_PREFETCH_CMD_WRMASK(val): return (val << A7XX_SP_FS_PREFETCH_CMD_WRMASK__SHIFT) & A7XX_SP_FS_PREFETCH_CMD_WRMASK__MASK
def A7XX_SP_FS_PREFETCH_CMD_CMD(val): return (val << A7XX_SP_FS_PREFETCH_CMD_CMD__SHIFT) & A7XX_SP_FS_PREFETCH_CMD_CMD__MASK
def A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID(val): return (val << A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__SHIFT) & A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__MASK
def A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID(val): return (val << A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__SHIFT) & A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__MASK
def A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET(val): return (val << A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK
def A6XX_SP_CS_CTRL_REG0_THREADMODE(val): return (val << A6XX_SP_CS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_CS_CTRL_REG0_THREADMODE__MASK
def A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(val): return (val << A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK
def A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(val): return (val << A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK
def A6XX_SP_CS_CTRL_REG0_BRANCHSTACK(val): return (val << A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK
def A6XX_SP_CS_CTRL_REG0_THREADSIZE(val): return (val << A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK
def A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE(val): return (val << A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__SHIFT) & A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__MASK
def A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM(val): return (val << A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK
def A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(val): return (val << A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK
def A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(val): return (val << A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK
def A6XX_SP_CS_CONFIG_NTEX(val): return (val << A6XX_SP_CS_CONFIG_NTEX__SHIFT) & A6XX_SP_CS_CONFIG_NTEX__MASK
def A6XX_SP_CS_CONFIG_NSAMP(val): return (val << A6XX_SP_CS_CONFIG_NSAMP__SHIFT) & A6XX_SP_CS_CONFIG_NSAMP__MASK
def A6XX_SP_CS_CONFIG_NIBO(val): return (val << A6XX_SP_CS_CONFIG_NIBO__SHIFT) & A6XX_SP_CS_CONFIG_NIBO__MASK
def A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET(val): return (val << A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK
def A6XX_SP_CS_CNTL_0_WGIDCONSTID(val): return (val << A6XX_SP_CS_CNTL_0_WGIDCONSTID__SHIFT) & A6XX_SP_CS_CNTL_0_WGIDCONSTID__MASK
def A6XX_SP_CS_CNTL_0_WGSIZECONSTID(val): return (val << A6XX_SP_CS_CNTL_0_WGSIZECONSTID__SHIFT) & A6XX_SP_CS_CNTL_0_WGSIZECONSTID__MASK
def A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID(val): return (val << A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID__SHIFT) & A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID__MASK
def A6XX_SP_CS_CNTL_0_LOCALIDREGID(val): return (val << A6XX_SP_CS_CNTL_0_LOCALIDREGID__SHIFT) & A6XX_SP_CS_CNTL_0_LOCALIDREGID__MASK
def A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID(val): return (val << A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT) & A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__MASK
def A6XX_SP_CS_CNTL_1_THREADSIZE(val): return (val << A6XX_SP_CS_CNTL_1_THREADSIZE__SHIFT) & A6XX_SP_CS_CNTL_1_THREADSIZE__MASK
def A7XX_SP_CS_CNTL_1_LINEARLOCALIDREGID(val): return (val << A7XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT) & A7XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__MASK
def A7XX_SP_CS_CNTL_1_THREADSIZE(val): return (val << A7XX_SP_CS_CNTL_1_THREADSIZE__SHIFT) & A7XX_SP_CS_CNTL_1_THREADSIZE__MASK
def A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(val): return (val << A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT) & A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK
def A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR(val): return (val << A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT) & A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK
def A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(val): return (val << A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT) & A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK
def A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR(val): return (val << A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT) & A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK
def A7XX_SP_PS_ALIASED_COMPONENTS_RT0(val): return (val << A7XX_SP_PS_ALIASED_COMPONENTS_RT0__SHIFT) & A7XX_SP_PS_ALIASED_COMPONENTS_RT0__MASK
def A7XX_SP_PS_ALIASED_COMPONENTS_RT1(val): return (val << A7XX_SP_PS_ALIASED_COMPONENTS_RT1__SHIFT) & A7XX_SP_PS_ALIASED_COMPONENTS_RT1__MASK
def A7XX_SP_PS_ALIASED_COMPONENTS_RT2(val): return (val << A7XX_SP_PS_ALIASED_COMPONENTS_RT2__SHIFT) & A7XX_SP_PS_ALIASED_COMPONENTS_RT2__MASK
def A7XX_SP_PS_ALIASED_COMPONENTS_RT3(val): return (val << A7XX_SP_PS_ALIASED_COMPONENTS_RT3__SHIFT) & A7XX_SP_PS_ALIASED_COMPONENTS_RT3__MASK
def A7XX_SP_PS_ALIASED_COMPONENTS_RT4(val): return (val << A7XX_SP_PS_ALIASED_COMPONENTS_RT4__SHIFT) & A7XX_SP_PS_ALIASED_COMPONENTS_RT4__MASK
def A7XX_SP_PS_ALIASED_COMPONENTS_RT5(val): return (val << A7XX_SP_PS_ALIASED_COMPONENTS_RT5__SHIFT) & A7XX_SP_PS_ALIASED_COMPONENTS_RT5__MASK
def A7XX_SP_PS_ALIASED_COMPONENTS_RT6(val): return (val << A7XX_SP_PS_ALIASED_COMPONENTS_RT6__SHIFT) & A7XX_SP_PS_ALIASED_COMPONENTS_RT6__MASK
def A7XX_SP_PS_ALIASED_COMPONENTS_RT7(val): return (val << A7XX_SP_PS_ALIASED_COMPONENTS_RT7__SHIFT) & A7XX_SP_PS_ALIASED_COMPONENTS_RT7__MASK
def A6XX_SP_MODE_CONTROL_ISAMMODE(val): return (val << A6XX_SP_MODE_CONTROL_ISAMMODE__SHIFT) & A6XX_SP_MODE_CONTROL_ISAMMODE__MASK
def A6XX_SP_FS_CONFIG_NTEX(val): return (val << A6XX_SP_FS_CONFIG_NTEX__SHIFT) & A6XX_SP_FS_CONFIG_NTEX__MASK
def A6XX_SP_FS_CONFIG_NSAMP(val): return (val << A6XX_SP_FS_CONFIG_NSAMP__SHIFT) & A6XX_SP_FS_CONFIG_NSAMP__MASK
def A6XX_SP_FS_CONFIG_NIBO(val): return (val << A6XX_SP_FS_CONFIG_NIBO__SHIFT) & A6XX_SP_FS_CONFIG_NIBO__MASK
def A6XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(val): return (val << A6XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT) & A6XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK
def A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR(val): return (val << A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT) & A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK
def A7XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(val): return (val << A7XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT) & A7XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK
def A7XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR(val): return (val << A7XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT) & A7XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK
def A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT(val): return (val << A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__SHIFT) & A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__MASK
def A6XX_SP_2D_DST_FORMAT_MASK(val): return (val << A6XX_SP_2D_DST_FORMAT_MASK__SHIFT) & A6XX_SP_2D_DST_FORMAT_MASK__MASK
def A7XX_SP_2D_DST_FORMAT_COLOR_FORMAT(val): return (val << A7XX_SP_2D_DST_FORMAT_COLOR_FORMAT__SHIFT) & A7XX_SP_2D_DST_FORMAT_COLOR_FORMAT__MASK
def A7XX_SP_2D_DST_FORMAT_MASK(val): return (val << A7XX_SP_2D_DST_FORMAT_MASK__SHIFT) & A7XX_SP_2D_DST_FORMAT_MASK__MASK
def A7XX_SP_READ_SEL_LOCATION(val): return (val << A7XX_SP_READ_SEL_LOCATION__SHIFT) & A7XX_SP_READ_SEL_LOCATION__MASK
def A7XX_SP_READ_SEL_PIPE(val): return (val << A7XX_SP_READ_SEL_PIPE__SHIFT) & A7XX_SP_READ_SEL_PIPE__MASK
def A7XX_SP_READ_SEL_STATETYPE(val): return (val << A7XX_SP_READ_SEL_STATETYPE__SHIFT) & A7XX_SP_READ_SEL_STATETYPE__MASK
def A7XX_SP_READ_SEL_USPTP(val): return (val << A7XX_SP_READ_SEL_USPTP__SHIFT) & A7XX_SP_READ_SEL_USPTP__MASK
def A7XX_SP_READ_SEL_SPTP(val): return (val << A7XX_SP_READ_SEL_SPTP__SHIFT) & A7XX_SP_READ_SEL_SPTP__MASK
def A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES(val): return (val << A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK
def A6XX_SP_TP_RAS_MSAA_CNTL_UNK2(val): return (val << A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__SHIFT) & A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__MASK
def A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES(val): return (val << A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__MASK
def A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X(val): return (val << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK
def A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y(val): return (val << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK
def A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X(val): return (val << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK
def A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y(val): return (val << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK
def A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X(val): return (val << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK
def A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y(val): return (val << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK
def A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X(val): return (val << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK
def A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y(val): return (val << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK
def A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X(val): return (val << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK
def A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y(val): return (val << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK
def A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X(val): return (val << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK
def A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y(val): return (val << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK
def A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X(val): return (val << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK
def A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y(val): return (val << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK
def A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X(val): return (val << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK
def A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y(val): return (val << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK
def A6XX_SP_TP_WINDOW_OFFSET_X(val): return (val << A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT) & A6XX_SP_TP_WINDOW_OFFSET_X__MASK
def A6XX_SP_TP_WINDOW_OFFSET_Y(val): return (val << A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT) & A6XX_SP_TP_WINDOW_OFFSET_Y__MASK
def A6XX_SP_TP_MODE_CNTL_ISAMMODE(val): return (val << A6XX_SP_TP_MODE_CNTL_ISAMMODE__SHIFT) & A6XX_SP_TP_MODE_CNTL_ISAMMODE__MASK
def A6XX_SP_TP_MODE_CNTL_UNK3(val): return (val << A6XX_SP_TP_MODE_CNTL_UNK3__SHIFT) & A6XX_SP_TP_MODE_CNTL_UNK3__MASK
def A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT(val): return (val << A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK
def A6XX_SP_PS_2D_SRC_INFO_TILE_MODE(val): return (val << A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK
def A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP(val): return (val << A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK
def A6XX_SP_PS_2D_SRC_INFO_SAMPLES(val): return (val << A6XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK
def A6XX_SP_PS_2D_SRC_INFO_UNK23(val): return (val << A6XX_SP_PS_2D_SRC_INFO_UNK23__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_UNK23__MASK
def A6XX_SP_PS_2D_SRC_SIZE_WIDTH(val): return (val << A6XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT) & A6XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK
def A6XX_SP_PS_2D_SRC_SIZE_HEIGHT(val): return (val << A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT) & A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK
def A6XX_SP_PS_2D_SRC_PITCH_UNK0(val): return (val << A6XX_SP_PS_2D_SRC_PITCH_UNK0__SHIFT) & A6XX_SP_PS_2D_SRC_PITCH_UNK0__MASK
def A6XX_SP_PS_2D_SRC_PITCH_PITCH(val): return (val << A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK
def A7XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT(val): return (val << A7XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT) & A7XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK
def A7XX_SP_PS_2D_SRC_INFO_TILE_MODE(val): return (val << A7XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT) & A7XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK
def A7XX_SP_PS_2D_SRC_INFO_COLOR_SWAP(val): return (val << A7XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT) & A7XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK
def A7XX_SP_PS_2D_SRC_INFO_SAMPLES(val): return (val << A7XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT) & A7XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK
def A7XX_SP_PS_2D_SRC_INFO_UNK23(val): return (val << A7XX_SP_PS_2D_SRC_INFO_UNK23__SHIFT) & A7XX_SP_PS_2D_SRC_INFO_UNK23__MASK
def A7XX_SP_PS_2D_SRC_SIZE_WIDTH(val): return (val << A7XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT) & A7XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK
def A7XX_SP_PS_2D_SRC_SIZE_HEIGHT(val): return (val << A7XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT) & A7XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK
def A7XX_SP_PS_2D_SRC_PITCH_UNK0(val): return (val << A7XX_SP_PS_2D_SRC_PITCH_UNK0__SHIFT) & A7XX_SP_PS_2D_SRC_PITCH_UNK0__MASK
def A7XX_SP_PS_2D_SRC_PITCH_PITCH(val): return (val << A7XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT) & A7XX_SP_PS_2D_SRC_PITCH_PITCH__MASK
def A6XX_SP_PS_2D_SRC_PLANE_PITCH(val): return (val << A6XX_SP_PS_2D_SRC_PLANE_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_PLANE_PITCH__MASK
def A7XX_SP_PS_2D_SRC_PLANE_PITCH(val): return (val << A7XX_SP_PS_2D_SRC_PLANE_PITCH__SHIFT) & A7XX_SP_PS_2D_SRC_PLANE_PITCH__MASK
def A6XX_SP_PS_2D_SRC_FLAGS_PITCH(val): return (val << A6XX_SP_PS_2D_SRC_FLAGS_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_FLAGS_PITCH__MASK
def A7XX_SP_PS_2D_SRC_FLAGS_PITCH(val): return (val << A7XX_SP_PS_2D_SRC_FLAGS_PITCH__SHIFT) & A7XX_SP_PS_2D_SRC_FLAGS_PITCH__MASK
def A6XX_SP_WINDOW_OFFSET_X(val): return (val << A6XX_SP_WINDOW_OFFSET_X__SHIFT) & A6XX_SP_WINDOW_OFFSET_X__MASK
def A6XX_SP_WINDOW_OFFSET_Y(val): return (val << A6XX_SP_WINDOW_OFFSET_Y__SHIFT) & A6XX_SP_WINDOW_OFFSET_Y__MASK
def A7XX_SP_PS_2D_WINDOW_OFFSET_X(val): return (val << A7XX_SP_PS_2D_WINDOW_OFFSET_X__SHIFT) & A7XX_SP_PS_2D_WINDOW_OFFSET_X__MASK
def A7XX_SP_PS_2D_WINDOW_OFFSET_Y(val): return (val << A7XX_SP_PS_2D_WINDOW_OFFSET_Y__SHIFT) & A7XX_SP_PS_2D_WINDOW_OFFSET_Y__MASK
def A7XX_SP_WINDOW_OFFSET_X(val): return (val << A7XX_SP_WINDOW_OFFSET_X__SHIFT) & A7XX_SP_WINDOW_OFFSET_X__MASK
def A7XX_SP_WINDOW_OFFSET_Y(val): return (val << A7XX_SP_WINDOW_OFFSET_Y__SHIFT) & A7XX_SP_WINDOW_OFFSET_Y__MASK
def A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT(val): return (val << A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__SHIFT) & A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__MASK
def A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT(val): return (val << A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__SHIFT) & A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__MASK
def A6XX_TPL1_NC_MODE_CNTL_UNK6(val): return (val << A6XX_TPL1_NC_MODE_CNTL_UNK6__SHIFT) & A6XX_TPL1_NC_MODE_CNTL_UNK6__MASK
def A6XX_HLSQ_VS_CNTL_CONSTLEN(val): return (val << A6XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK
def A6XX_HLSQ_HS_CNTL_CONSTLEN(val): return (val << A6XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_HS_CNTL_CONSTLEN__MASK
def A6XX_HLSQ_DS_CNTL_CONSTLEN(val): return (val << A6XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_DS_CNTL_CONSTLEN__MASK
def A6XX_HLSQ_GS_CNTL_CONSTLEN(val): return (val << A6XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK
def A7XX_HLSQ_VS_CNTL_CONSTLEN(val): return (val << A7XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT) & A7XX_HLSQ_VS_CNTL_CONSTLEN__MASK
def A7XX_HLSQ_HS_CNTL_CONSTLEN(val): return (val << A7XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT) & A7XX_HLSQ_HS_CNTL_CONSTLEN__MASK
def A7XX_HLSQ_DS_CNTL_CONSTLEN(val): return (val << A7XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT) & A7XX_HLSQ_DS_CNTL_CONSTLEN__MASK
def A7XX_HLSQ_GS_CNTL_CONSTLEN(val): return (val << A7XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT) & A7XX_HLSQ_GS_CNTL_CONSTLEN__MASK
def A7XX_HLSQ_UNKNOWN_A9AE_SYSVAL_REGS_COUNT(val): return (val << A7XX_HLSQ_UNKNOWN_A9AE_SYSVAL_REGS_COUNT__SHIFT) & A7XX_HLSQ_UNKNOWN_A9AE_SYSVAL_REGS_COUNT__MASK
def A6XX_HLSQ_FS_CNTL_0_THREADSIZE(val): return (val << A6XX_HLSQ_FS_CNTL_0_THREADSIZE__SHIFT) & A6XX_HLSQ_FS_CNTL_0_THREADSIZE__MASK
def A6XX_HLSQ_FS_CNTL_0_UNK2(val): return (val << A6XX_HLSQ_FS_CNTL_0_UNK2__SHIFT) & A6XX_HLSQ_FS_CNTL_0_UNK2__MASK
def A6XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD(val): return (val << A6XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT) & A6XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK
def A6XX_HLSQ_CONTROL_2_REG_FACEREGID(val): return (val << A6XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK
def A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(val): return (val << A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK
def A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(val): return (val << A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK
def A6XX_HLSQ_CONTROL_2_REG_CENTERRHW(val): return (val << A6XX_HLSQ_CONTROL_2_REG_CENTERRHW__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_CENTERRHW__MASK
def A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(val): return (val << A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK
def A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(val): return (val << A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK
def A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(val): return (val << A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK
def A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(val): return (val << A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK
def A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(val): return (val << A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK
def A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(val): return (val << A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK
def A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(val): return (val << A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK
def A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(val): return (val << A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK
def A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID(val): return (val << A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__SHIFT) & A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__MASK
def A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID(val): return (val << A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__SHIFT) & A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__MASK
def A6XX_HLSQ_CS_CNTL_CONSTLEN(val): return (val << A6XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_CS_CNTL_CONSTLEN__MASK
def A7XX_HLSQ_FS_CNTL_0_THREADSIZE(val): return (val << A7XX_HLSQ_FS_CNTL_0_THREADSIZE__SHIFT) & A7XX_HLSQ_FS_CNTL_0_THREADSIZE__MASK
def A7XX_HLSQ_FS_CNTL_0_UNK2(val): return (val << A7XX_HLSQ_FS_CNTL_0_UNK2__SHIFT) & A7XX_HLSQ_FS_CNTL_0_UNK2__MASK
def A7XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD(val): return (val << A7XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT) & A7XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK
def A7XX_HLSQ_CONTROL_2_REG_FACEREGID(val): return (val << A7XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A7XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK
def A7XX_HLSQ_CONTROL_2_REG_SAMPLEID(val): return (val << A7XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT) & A7XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK
def A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(val): return (val << A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT) & A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK
def A7XX_HLSQ_CONTROL_2_REG_CENTERRHW(val): return (val << A7XX_HLSQ_CONTROL_2_REG_CENTERRHW__SHIFT) & A7XX_HLSQ_CONTROL_2_REG_CENTERRHW__MASK
def A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(val): return (val << A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT) & A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK
def A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(val): return (val << A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT) & A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK
def A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(val): return (val << A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT) & A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK
def A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(val): return (val << A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT) & A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK
def A7XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(val): return (val << A7XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT) & A7XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK
def A7XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(val): return (val << A7XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT) & A7XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK
def A7XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(val): return (val << A7XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT) & A7XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK
def A7XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(val): return (val << A7XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT) & A7XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK
def A7XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID(val): return (val << A7XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__SHIFT) & A7XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__MASK
def A7XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID(val): return (val << A7XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__SHIFT) & A7XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__MASK
def A7XX_HLSQ_CS_CNTL_CONSTLEN(val): return (val << A7XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT) & A7XX_HLSQ_CS_CNTL_CONSTLEN__MASK
def A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM(val): return (val << A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK
def A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(val): return (val << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK
def A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(val): return (val << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK
def A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(val): return (val << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK
def A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X(val): return (val << A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT) & A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK
def A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X(val): return (val << A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT) & A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK
def A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y(val): return (val << A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT) & A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK
def A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y(val): return (val << A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT) & A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK
def A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z(val): return (val << A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT) & A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK
def A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z(val): return (val << A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT) & A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK
def A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(val): return (val << A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK
def A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID(val): return (val << A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__MASK
def A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID(val): return (val << A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__MASK
def A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(val): return (val << A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK
def A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID(val): return (val << A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT) & A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__MASK
def A6XX_HLSQ_CS_CNTL_1_THREADSIZE(val): return (val << A6XX_HLSQ_CS_CNTL_1_THREADSIZE__SHIFT) & A6XX_HLSQ_CS_CNTL_1_THREADSIZE__MASK
def A7XX_HLSQ_CS_NDRANGE_0_KERNELDIM(val): return (val << A7XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT) & A7XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK
def A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(val): return (val << A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT) & A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK
def A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(val): return (val << A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT) & A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK
def A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(val): return (val << A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT) & A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK
def A7XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X(val): return (val << A7XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT) & A7XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK
def A7XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X(val): return (val << A7XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT) & A7XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK
def A7XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y(val): return (val << A7XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT) & A7XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK
def A7XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y(val): return (val << A7XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT) & A7XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK
def A7XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z(val): return (val << A7XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT) & A7XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK
def A7XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z(val): return (val << A7XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT) & A7XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK
def A7XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID(val): return (val << A7XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT) & A7XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__MASK
def A7XX_HLSQ_CS_CNTL_1_THREADSIZE(val): return (val << A7XX_HLSQ_CS_CNTL_1_THREADSIZE__SHIFT) & A7XX_HLSQ_CS_CNTL_1_THREADSIZE__MASK
def A7XX_HLSQ_CS_CNTL_1_YALIGN(val): return (val << A7XX_HLSQ_CS_CNTL_1_YALIGN__SHIFT) & A7XX_HLSQ_CS_CNTL_1_YALIGN__MASK
def A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEX(val): return (val << A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEX__SHIFT) & A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEX__MASK
def A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEY(val): return (val << A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEY__SHIFT) & A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEY__MASK
def A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEZ(val): return (val << A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEZ__SHIFT) & A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEZ__MASK
def A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(val): return (val << A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT) & A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK
def A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR(val): return (val << A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT) & A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK
def A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE(val): return (val << A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE__SHIFT) & A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE__MASK
def A6XX_HLSQ_DRAW_CMD_STATE_ID(val): return (val << A6XX_HLSQ_DRAW_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_DRAW_CMD_STATE_ID__MASK
def A6XX_HLSQ_DISPATCH_CMD_STATE_ID(val): return (val << A6XX_HLSQ_DISPATCH_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_DISPATCH_CMD_STATE_ID__MASK
def A6XX_HLSQ_EVENT_CMD_STATE_ID(val): return (val << A6XX_HLSQ_EVENT_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_EVENT_CMD_STATE_ID__MASK
def A6XX_HLSQ_EVENT_CMD_EVENT(val): return (val << A6XX_HLSQ_EVENT_CMD_EVENT__SHIFT) & A6XX_HLSQ_EVENT_CMD_EVENT__MASK
def A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS(val): return (val << A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__SHIFT) & A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__MASK
def A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS(val): return (val << A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__SHIFT) & A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__MASK
def A7XX_HLSQ_DRAW_CMD_STATE_ID(val): return (val << A7XX_HLSQ_DRAW_CMD_STATE_ID__SHIFT) & A7XX_HLSQ_DRAW_CMD_STATE_ID__MASK
def A7XX_HLSQ_DISPATCH_CMD_STATE_ID(val): return (val << A7XX_HLSQ_DISPATCH_CMD_STATE_ID__SHIFT) & A7XX_HLSQ_DISPATCH_CMD_STATE_ID__MASK
def A7XX_HLSQ_EVENT_CMD_STATE_ID(val): return (val << A7XX_HLSQ_EVENT_CMD_STATE_ID__SHIFT) & A7XX_HLSQ_EVENT_CMD_STATE_ID__MASK
def A7XX_HLSQ_EVENT_CMD_EVENT(val): return (val << A7XX_HLSQ_EVENT_CMD_EVENT__SHIFT) & A7XX_HLSQ_EVENT_CMD_EVENT__MASK
def A7XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS(val): return (val << A7XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__SHIFT) & A7XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__MASK
def A7XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS(val): return (val << A7XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__SHIFT) & A7XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__MASK
def A6XX_HLSQ_FS_CNTL_CONSTLEN(val): return (val << A6XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_FS_CNTL_CONSTLEN__MASK
def A7XX_HLSQ_FS_CNTL_CONSTLEN(val): return (val << A7XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT) & A7XX_HLSQ_FS_CNTL_CONSTLEN__MASK
def A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(val): return (val << A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT) & A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK
def A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR(val): return (val << A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT) & A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK
def A6XX_HLSQ_2D_EVENT_CMD_STATE_ID(val): return (val << A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__MASK
def A6XX_HLSQ_2D_EVENT_CMD_EVENT(val): return (val << A6XX_HLSQ_2D_EVENT_CMD_EVENT__SHIFT) & A6XX_HLSQ_2D_EVENT_CMD_EVENT__MASK
def A6XX_CP_EVENT_START_STATE_ID(val): return (val << A6XX_CP_EVENT_START_STATE_ID__SHIFT) & A6XX_CP_EVENT_START_STATE_ID__MASK
def A6XX_CP_EVENT_END_STATE_ID(val): return (val << A6XX_CP_EVENT_END_STATE_ID__SHIFT) & A6XX_CP_EVENT_END_STATE_ID__MASK
def A6XX_CP_2D_EVENT_START_STATE_ID(val): return (val << A6XX_CP_2D_EVENT_START_STATE_ID__SHIFT) & A6XX_CP_2D_EVENT_START_STATE_ID__MASK
def A6XX_CP_2D_EVENT_END_STATE_ID(val): return (val << A6XX_CP_2D_EVENT_END_STATE_ID__SHIFT) & A6XX_CP_2D_EVENT_END_STATE_ID__MASK
def A6XX_TEX_SAMP_0_XY_MAG(val): return (val << A6XX_TEX_SAMP_0_XY_MAG__SHIFT) & A6XX_TEX_SAMP_0_XY_MAG__MASK
def A6XX_TEX_SAMP_0_XY_MIN(val): return (val << A6XX_TEX_SAMP_0_XY_MIN__SHIFT) & A6XX_TEX_SAMP_0_XY_MIN__MASK
def A6XX_TEX_SAMP_0_WRAP_S(val): return (val << A6XX_TEX_SAMP_0_WRAP_S__SHIFT) & A6XX_TEX_SAMP_0_WRAP_S__MASK
def A6XX_TEX_SAMP_0_WRAP_T(val): return (val << A6XX_TEX_SAMP_0_WRAP_T__SHIFT) & A6XX_TEX_SAMP_0_WRAP_T__MASK
def A6XX_TEX_SAMP_0_WRAP_R(val): return (val << A6XX_TEX_SAMP_0_WRAP_R__SHIFT) & A6XX_TEX_SAMP_0_WRAP_R__MASK
def A6XX_TEX_SAMP_0_ANISO(val): return (val << A6XX_TEX_SAMP_0_ANISO__SHIFT) & A6XX_TEX_SAMP_0_ANISO__MASK
def A6XX_TEX_SAMP_0_LOD_BIAS(val): return (val << A6XX_TEX_SAMP_0_LOD_BIAS__SHIFT) & A6XX_TEX_SAMP_0_LOD_BIAS__MASK
def A6XX_TEX_SAMP_1_COMPARE_FUNC(val): return (val << A6XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & A6XX_TEX_SAMP_1_COMPARE_FUNC__MASK
def A6XX_TEX_SAMP_1_MAX_LOD(val): return (val << A6XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A6XX_TEX_SAMP_1_MAX_LOD__MASK
def A6XX_TEX_SAMP_1_MIN_LOD(val): return (val << A6XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A6XX_TEX_SAMP_1_MIN_LOD__MASK
def A6XX_TEX_SAMP_2_REDUCTION_MODE(val): return (val << A6XX_TEX_SAMP_2_REDUCTION_MODE__SHIFT) & A6XX_TEX_SAMP_2_REDUCTION_MODE__MASK
def A6XX_TEX_SAMP_2_BCOLOR(val): return (val << A6XX_TEX_SAMP_2_BCOLOR__SHIFT) & A6XX_TEX_SAMP_2_BCOLOR__MASK
def A6XX_TEX_CONST_0_TILE_MODE(val): return (val << A6XX_TEX_CONST_0_TILE_MODE__SHIFT) & A6XX_TEX_CONST_0_TILE_MODE__MASK
def A6XX_TEX_CONST_0_SWIZ_X(val): return (val << A6XX_TEX_CONST_0_SWIZ_X__SHIFT) & A6XX_TEX_CONST_0_SWIZ_X__MASK
def A6XX_TEX_CONST_0_SWIZ_Y(val): return (val << A6XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A6XX_TEX_CONST_0_SWIZ_Y__MASK
def A6XX_TEX_CONST_0_SWIZ_Z(val): return (val << A6XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A6XX_TEX_CONST_0_SWIZ_Z__MASK
def A6XX_TEX_CONST_0_SWIZ_W(val): return (val << A6XX_TEX_CONST_0_SWIZ_W__SHIFT) & A6XX_TEX_CONST_0_SWIZ_W__MASK
def A6XX_TEX_CONST_0_MIPLVLS(val): return (val << A6XX_TEX_CONST_0_MIPLVLS__SHIFT) & A6XX_TEX_CONST_0_MIPLVLS__MASK
def A6XX_TEX_CONST_0_SAMPLES(val): return (val << A6XX_TEX_CONST_0_SAMPLES__SHIFT) & A6XX_TEX_CONST_0_SAMPLES__MASK
def A6XX_TEX_CONST_0_FMT(val): return (val << A6XX_TEX_CONST_0_FMT__SHIFT) & A6XX_TEX_CONST_0_FMT__MASK
def A6XX_TEX_CONST_0_SWAP(val): return (val << A6XX_TEX_CONST_0_SWAP__SHIFT) & A6XX_TEX_CONST_0_SWAP__MASK
def A6XX_TEX_CONST_1_WIDTH(val): return (val << A6XX_TEX_CONST_1_WIDTH__SHIFT) & A6XX_TEX_CONST_1_WIDTH__MASK
def A6XX_TEX_CONST_1_HEIGHT(val): return (val << A6XX_TEX_CONST_1_HEIGHT__SHIFT) & A6XX_TEX_CONST_1_HEIGHT__MASK
def A6XX_TEX_CONST_2_STRUCTSIZETEXELS(val): return (val << A6XX_TEX_CONST_2_STRUCTSIZETEXELS__SHIFT) & A6XX_TEX_CONST_2_STRUCTSIZETEXELS__MASK
def A6XX_TEX_CONST_2_STARTOFFSETTEXELS(val): return (val << A6XX_TEX_CONST_2_STARTOFFSETTEXELS__SHIFT) & A6XX_TEX_CONST_2_STARTOFFSETTEXELS__MASK
def A6XX_TEX_CONST_2_PITCHALIGN(val): return (val << A6XX_TEX_CONST_2_PITCHALIGN__SHIFT) & A6XX_TEX_CONST_2_PITCHALIGN__MASK
def A6XX_TEX_CONST_2_PITCH(val): return (val << A6XX_TEX_CONST_2_PITCH__SHIFT) & A6XX_TEX_CONST_2_PITCH__MASK
def A6XX_TEX_CONST_2_TYPE(val): return (val << A6XX_TEX_CONST_2_TYPE__SHIFT) & A6XX_TEX_CONST_2_TYPE__MASK
def A6XX_TEX_CONST_3_ARRAY_PITCH(val): return (val << A6XX_TEX_CONST_3_ARRAY_PITCH__SHIFT) & A6XX_TEX_CONST_3_ARRAY_PITCH__MASK
def A6XX_TEX_CONST_3_MIN_LAYERSZ(val): return (val << A6XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT) & A6XX_TEX_CONST_3_MIN_LAYERSZ__MASK
def A6XX_TEX_CONST_4_BASE_LO(val): return (val << A6XX_TEX_CONST_4_BASE_LO__SHIFT) & A6XX_TEX_CONST_4_BASE_LO__MASK
def A6XX_TEX_CONST_5_BASE_HI(val): return (val << A6XX_TEX_CONST_5_BASE_HI__SHIFT) & A6XX_TEX_CONST_5_BASE_HI__MASK
def A6XX_TEX_CONST_5_DEPTH(val): return (val << A6XX_TEX_CONST_5_DEPTH__SHIFT) & A6XX_TEX_CONST_5_DEPTH__MASK
def A6XX_TEX_CONST_6_MIN_LOD_CLAMP(val): return (val << A6XX_TEX_CONST_6_MIN_LOD_CLAMP__SHIFT) & A6XX_TEX_CONST_6_MIN_LOD_CLAMP__MASK
def A6XX_TEX_CONST_6_PLANE_PITCH(val): return (val << A6XX_TEX_CONST_6_PLANE_PITCH__SHIFT) & A6XX_TEX_CONST_6_PLANE_PITCH__MASK
def A6XX_TEX_CONST_7_FLAG_LO(val): return (val << A6XX_TEX_CONST_7_FLAG_LO__SHIFT) & A6XX_TEX_CONST_7_FLAG_LO__MASK
def A6XX_TEX_CONST_8_FLAG_HI(val): return (val << A6XX_TEX_CONST_8_FLAG_HI__SHIFT) & A6XX_TEX_CONST_8_FLAG_HI__MASK
def A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH(val): return (val << A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__MASK
def A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH(val): return (val << A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__SHIFT) & A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__MASK
def A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW(val): return (val << A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__SHIFT) & A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__MASK
def A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH(val): return (val << A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__SHIFT) & A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__MASK
def A6XX_UBO_0_BASE_LO(val): return (val << A6XX_UBO_0_BASE_LO__SHIFT) & A6XX_UBO_0_BASE_LO__MASK
def A6XX_UBO_1_BASE_HI(val): return (val << A6XX_UBO_1_BASE_HI__SHIFT) & A6XX_UBO_1_BASE_HI__MASK
def A6XX_UBO_1_SIZE(val): return (val << A6XX_UBO_1_SIZE__SHIFT) & A6XX_UBO_1_SIZE__MASK
def A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX(val): return (val << A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__MASK
def A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL(val): return (val << A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__MASK
def A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN(val): return (val << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK
def A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU(val): return (val << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK
def A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT(val): return (val << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK
def A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(val): return (val << A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK
def A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0(val): return (val << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK
def A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1(val): return (val << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK
def A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2(val): return (val << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK
def A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3(val): return (val << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK
def A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4(val): return (val << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK
def A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5(val): return (val << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK
def A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6(val): return (val << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK
def A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7(val): return (val << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK
def A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8(val): return (val << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK
def A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9(val): return (val << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK
def A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10(val): return (val << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK
def A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11(val): return (val << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK
def A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12(val): return (val << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK
def A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13(val): return (val << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK
def A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14(val): return (val << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK
def A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(val): return (val << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK