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84 lines
1.7 KiB
84 lines
1.7 KiB
void can_init(CAN_TypeDef *CAN) {
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// enable CAN busses
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if (CAN == CAN1) {
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// CAN1_EN
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GPIOB->ODR |= (1 << 3);
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} else if (CAN == CAN2) {
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// CAN2_EN
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GPIOB->ODR |= (1 << 4);
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}
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CAN->MCR = CAN_MCR_TTCM | CAN_MCR_INRQ;
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while((CAN->MSR & CAN_MSR_INAK) != CAN_MSR_INAK);
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puts("CAN initting\n");
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// PCLK = 24000000, 500000 is 48 clocks
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// from http://www.bittiming.can-wiki.ino/
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CAN->BTR = 0x001c0002;
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// loopback mode for debugging
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#ifdef CAN_LOOPBACK_MODE
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CAN->BTR |= CAN_BTR_SILM | CAN_BTR_LBKM;
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#endif
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// reset
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CAN->MCR = CAN_MCR_TTCM;
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while((CAN->MSR & CAN_MSR_INAK) == CAN_MSR_INAK);
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puts("CAN init done\n");
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// accept all filter
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CAN->FMR |= CAN_FMR_FINIT;
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// no mask
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CAN->sFilterRegister[0].FR1 = 0;
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CAN->sFilterRegister[0].FR2 = 0;
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CAN->sFilterRegister[14].FR1 = 0;
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CAN->sFilterRegister[14].FR2 = 0;
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CAN->FA1R |= 1 | (1 << 14);
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CAN->FMR &= ~(CAN_FMR_FINIT);
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// enable all CAN interrupts
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CAN->IER = 0xFFFFFFFF;
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//CAN->IER = CAN_IER_TMEIE | CAN_IER_FMPIE0 | CAN_IER_FMPIE1;
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}
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// CAN error
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void can_sce(CAN_TypeDef *CAN) {
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#ifdef DEBUG
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puts("MSR:");
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puth(CAN->MSR);
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puts(" TSR:");
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puth(CAN->TSR);
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puts(" RF0R:");
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puth(CAN->RF0R);
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puts(" RF1R:");
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puth(CAN->RF1R);
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puts(" ESR:");
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puth(CAN->ESR);
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puts("\n");
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#endif
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// clear
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//CAN->sTxMailBox[0].TIR &= ~(CAN_TI0R_TXRQ);
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CAN->TSR |= CAN_TSR_ABRQ0;
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//CAN->ESR |= CAN_ESR_LEC;
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//CAN->MSR &= ~(CAN_MSR_ERRI);
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CAN->MSR = CAN->MSR;
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}
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int can_cksum(uint8_t *dat, int len, int addr, int idx) {
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int i;
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int s = 0;
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for (i = 0; i < len; i++) {
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s += (dat[i] >> 4);
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s += dat[i] & 0xF;
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}
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s += (addr>>0)&0xF;
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s += (addr>>4)&0xF;
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s += (addr>>8)&0xF;
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s += idx;
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s = 8-s;
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return s&0xF;
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}
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