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59 lines
2.2 KiB
59 lines
2.2 KiB
#include <stdio.h>
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#include <fcntl.h>
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#include <sys/mman.h>
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void hexdump(uint32_t *d, int l) {
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for (int i = 0; i < l; i++) {
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if (i%0x10 == 0 && i != 0) printf("\n");
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printf("%8x ", d[i]);
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}
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printf("\n");
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}
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/* Power cluster primary PLL */
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#define C0_PLL_MODE 0x0
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#define C0_PLL_L_VAL 0x4
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#define C0_PLL_ALPHA 0x8
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#define C0_PLL_USER_CTL 0x10
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#define C0_PLL_CONFIG_CTL 0x18
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#define C0_PLL_CONFIG_CTL_HI 0x1C
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#define C0_PLL_STATUS 0x28
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#define C0_PLL_TEST_CTL_LO 0x20
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#define C0_PLL_TEST_CTL_HI 0x24
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/* Power cluster alt PLL */
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#define C0_PLLA_MODE 0x100
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#define C0_PLLA_L_VAL 0x104
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#define C0_PLLA_ALPHA 0x108
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#define C0_PLLA_USER_CTL 0x110
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#define C0_PLLA_CONFIG_CTL 0x118
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#define C0_PLLA_STATUS 0x128
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#define C0_PLLA_TEST_CTL_LO 0x120
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#define APC_DIAG_OFFSET 0x48
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#define CLK_CTL_OFFSET 0x44
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#define MUX_OFFSET 0x40
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#define MDD_DROOP_CODE 0x7c
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#define SSSCTL_OFFSET 0x160
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#define PSCTL_OFFSET 0x164
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int main() {
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int fd = open("/dev/mem", O_RDWR);
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volatile uint32_t *mb = (uint32_t*)mmap(0,0x1000,PROT_READ | PROT_WRITE,MAP_SHARED,fd,0x06400000);
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volatile uint32_t *mc = (uint32_t*)mmap(0,0x1000,PROT_READ | PROT_WRITE,MAP_SHARED,fd,0x06480000);
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volatile uint32_t *md = (uint32_t*)mmap(0,0x1000,PROT_READ | PROT_WRITE,MAP_SHARED,fd,0x09A20000);
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while (1) {
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printf("PLL MODE:%x L_VAL:%x ALPHA:%x USER_CTL:%x CONFIG_CTL:%x CONFIG_CTL_HI:%x STATUS:%x TEST_CTL_LO:%x TEST_CTL_HI:%x\n",
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mb[C0_PLL_MODE/4], mb[C0_PLL_L_VAL/4], mb[C0_PLL_ALPHA/4],
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mb[C0_PLL_USER_CTL/4], mb[C0_PLL_CONFIG_CTL/4], mb[C0_PLL_CONFIG_CTL_HI/4],
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mb[C0_PLL_STATUS/4], mb[C0_PLL_TEST_CTL_LO/4], mb[C0_PLL_TEST_CTL_HI/4]);
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printf(" MUX_OFFSET:%x CLK_CTL_OFFSET:%x APC_DIAG_OFFSET:%x MDD_DROOP_CODE:%x\n",
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mb[MUX_OFFSET/4], mb[CLK_CTL_OFFSET/4], mb[APC_DIAG_OFFSET/4], mb[MDD_DROOP_CODE/4]);
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printf(" PLLA MODE:%x L_VAL:%x ALPHA:%x USER_CTL:%x CONFIG_CTL:%x STATUS:%x TEST_CTL_LO:%x SSSCTL_OFFSET:%x PSCTL_OFFSET:%x\n",
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mb[C0_PLLA_MODE/4], mb[C0_PLLA_L_VAL/4], mb[C0_PLLA_ALPHA/4], mb[C0_PLLA_USER_CTL/4],
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mb[C0_PLLA_CONFIG_CTL/4], mb[C0_PLLA_STATUS/4], mb[C0_PLLA_TEST_CTL_LO/4],
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mb[SSSCTL_OFFSET/4], mb[PSCTL_OFFSET/4]);
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usleep(1000*100);
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}
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}
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