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132 lines
4.1 KiB
132 lines
4.1 KiB
#include "debug/include/adreno_pm4types.h"
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#define REG_A5XX_TPL1_CS_TEX_CONST_LO 0x0000e760
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#define REG_A5XX_TPL1_CS_TEX_SAMP_LO 0x0000e75c
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#define REG_A5XX_SP_CS_CTRL_REG0 0x0000e5f0
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std::map<int, std::string> regs = {
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{0x0000e760, "REG_A5XX_TPL1_CS_TEX_CONST_LO"},
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{0x0000e75c, "REG_A5XX_TPL1_CS_TEX_SAMP_LO"},
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{0x00000e06, "REG_A5XX_HLSQ_MODE_CNTL"},
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{0x00000e91, "REG_A5XX_UCHE_CACHE_INVALIDATE_MIN_LO"},
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{0x00000ec2, "REG_A5XX_SP_MODE_CNTL"},
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{0x0000e580, "REG_A5XX_SP_SP_CNTL"},
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{0x0000e5f0, "REG_A5XX_SP_CS_CTRL_REG0"},
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{0x0000e796, "REG_A5XX_HLSQ_CS_CNTL"},
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{0x0000e784, "REG_A5XX_HLSQ_CONTROL_0_REG"},
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{0x0000e7b0, "REG_A5XX_HLSQ_CS_NDRANGE_0"},
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{0x0000e7b9, "REG_A5XX_HLSQ_CS_KERNEL_GROUP_X"},
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{0x00000cdd, "REG_A5XX_VSC_RESOLVE_CNTL"},
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};
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std::map<int, std::string> ops = {
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{33, "CP_REG_RMW"},
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{62, "CP_REG_TO_MEM"},
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{49, "CP_RUN_OPENCL"},
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{16, "CP_NOP"},
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{38, "CP_WAIT_FOR_IDLE"},
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{110, "CP_COMPUTE_CHECKPOINT"},
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{48, "CP_LOAD_STATE"},
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};
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void CachedCommand::disassemble() {
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uint32_t *src = (uint32_t *)cmds[1].gpuaddr;
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int len = cmds[1].size/4;
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printf("disassemble %p %d\n", src, len);
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int i = 0;
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while (i < len) {
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int pktsize;
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int pkttype = -1;
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if (pkt_is_type0(src[i])) {
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pkttype = 0;
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pktsize = type0_pkt_size(src[i]);
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} else if (pkt_is_type3(src[i])) {
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pkttype = 3;
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pktsize = type3_pkt_size(src[i]);
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} else if (pkt_is_type4(src[i])) {
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pkttype = 4;
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pktsize = type4_pkt_size(src[i]);
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} else if (pkt_is_type7(src[i])) {
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pkttype = 7;
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pktsize = type7_pkt_size(src[i]);
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}
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printf("%3d: type:%d size:%d ", i, pkttype, pktsize);
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if (pkttype == 7) {
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int op = cp_type7_opcode(src[i]);
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if (ops.find(op) != ops.end()) {
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printf("%-40s ", ops[op].c_str());
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} else {
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printf("op: %4d ", op);
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}
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}
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if (pkttype == 4) {
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int reg = cp_type4_base_index_one_reg_wr(src[i]);
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if (regs.find(reg) != regs.end()) {
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printf("%-40s ", regs[reg].c_str());
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} else {
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printf("reg: %4x ", reg);
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}
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}
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for (int j = 0; j < pktsize+1; j++) {
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printf("%8.8X ", src[i+j]);
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}
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printf("\n");
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uint64_t addr;
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if (pkttype == 7) {
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switch (cp_type7_opcode(src[i])) {
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case CP_LOAD_STATE:
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int dst_off = src[i+1] & 0x1FFF;
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int state_src = (src[i+1] >> 16) & 3;
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int state_block = (src[i+1] >> 18) & 7;
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int state_type = src[i+2] & 3;
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int num_unit = (src[i+1] & 0xffc00000) >> 22;
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printf(" dst_off: %x state_src: %d state_block: %d state_type: %d num_unit: %d\n",
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dst_off, state_src, state_block, state_type, num_unit);
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addr = (uint64_t)(src[i+2] & 0xfffffffc) | ((uint64_t)(src[i+3]) << 32);
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if (state_block == 5 && state_type == 0) {
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if (!(addr&0xFFF)) {
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int len = 0x1000;
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if (num_unit >= 32) len += 0x1000;
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//hexdump((uint32_t *)addr, len);
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char fn[0x100];
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snprintf(fn, sizeof(fn), "/tmp/0x%lx.shader", addr);
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printf("dumping %s\n", fn);
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FILE *f = fopen(fn, "wb");
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// groups of 16 instructions
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fwrite((void*)addr, 1, len, f);
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fclose(f);
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}
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}
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break;
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}
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}
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/*if (pkttype == 4) {
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switch (cp_type4_base_index_one_reg_wr(src[i])) {
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case REG_A5XX_SP_CS_CTRL_REG0:
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addr = (uint64_t)(src[i+4] & 0xfffffffc) | ((uint64_t)(src[i+5]) << 32);
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hexdump((uint32_t *)addr, 0x1000);
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break;
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}
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}*/
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/*if (pkttype == 4 && cp_type4_base_index_one_reg_wr(src[i]) == REG_A5XX_TPL1_CS_TEX_CONST_LO) {
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uint64_t addr = (uint64_t)(src[i+1] & 0xffffffff) | ((uint64_t)(src[i+2]) << 32);
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hexdump((uint32_t *)addr, 0x40);
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}
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if (pkttype == 4 && cp_type4_base_index_one_reg_wr(src[i]) == REG_A5XX_TPL1_CS_TEX_SAMP_LO) {
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uint64_t addr = (uint64_t)(src[i+1] & 0xffffffff) | ((uint64_t)(src[i+2]) << 32);
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hexdump((uint32_t *)addr, 0x40);
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}*/
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if (pkttype == -1) break;
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i += (1+pktsize);
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}
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assert(i == len);
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}
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